Unified Coverage Report :: Group Instance : key_version

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6628

1

T4

7

T14

56

T16

5

auto[1]

291

1

T122

7

T138

9

T139

12

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	2818	1			T4	3		T14	25		T16	2
auto[134217728:268435455]	173	1			T18	2		T32	1		T137	1
auto[268435456:402653183]	138	1			T14	1		T102	1		T48	1
auto[402653184:536870911]	140	1			T4	2		T14	1		T36	1
auto[536870912:671088639]	150	1			T104	1		T29	1		T48	2
auto[671088640:805306367]	122	1			T14	3		T29	1		T48	1
auto[805306368:939524095]	145	1			T14	1		T79	1		T68	1
auto[939524096:1073741823]	135	1			T79	1		T104	1		T29	1
auto[1073741824:1207959551]	126	1			T4	1		T14	2		T29	2
auto[1207959552:1342177279]	134	1			T79	1		T29	2		T102	1
auto[1342177280:1476395007]	136	1			T14	2		T79	1		T68	1
auto[1476395008:1610612735]	139	1			T4	1		T36	1		T137	1
auto[1610612736:1744830463]	133	1			T14	2		T68	1		T29	1
auto[1744830464:1879048191]	136	1			T14	2		T29	1		T24	1
auto[1879048192:2013265919]	146	1			T14	3		T79	1		T28	1
auto[2013265920:2147483647]	135	1			T14	1		T28	1		T29	1
auto[2147483648:2281701375]	125	1			T14	2		T68	1		T48	1
auto[2281701376:2415919103]	118	1			T14	2		T104	1		T29	1
auto[2415919104:2550136831]	118	1			T29	1		T24	1		T137	1
auto[2550136832:2684354559]	106	1			T14	1		T28	1		T68	1
auto[2684354560:2818572287]	124	1			T48	1		T89	1		T52	1
auto[2818572288:2952790015]	110	1			T79	1		T29	1		T51	1
auto[2952790016:3087007743]	136	1			T104	1		T68	1		T24	1
auto[3087007744:3221225471]	122	1			T14	2		T28	1		T29	1
auto[3221225472:3355443199]	141	1			T16	1		T36	1		T51	1
auto[3355443200:3489660927]	121	1			T104	1		T29	1		T48	3
auto[3489660928:3623878655]	140	1			T16	1		T29	1		T102	1
auto[3623878656:3758096383]	115	1			T14	1		T29	2		T102	1
auto[3758096384:3892314111]	142	1			T14	3		T58	1		T29	1
auto[3892314112:4026531839]	133	1			T14	1		T79	2		T28	1
auto[4026531840:4160749567]	143	1			T16	1		T68	1		T184	1
auto[4160749568:4294967295]	119	1			T14	1		T104	1		T29	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	2810	1			T4	3		T14	25		T16	2
auto[0:134217727]	auto[1]	8	1			T139	2		T225	1		T107	1
auto[134217728:268435455]	auto[0]	158	1			T18	2		T32	1		T137	1
auto[134217728:268435455]	auto[1]	15	1			T122	2		T138	2		T139	1
auto[268435456:402653183]	auto[0]	126	1			T14	1		T102	1		T48	1
auto[268435456:402653183]	auto[1]	12	1			T138	1		T139	1		T222	1
auto[402653184:536870911]	auto[0]	131	1			T4	2		T14	1		T36	1
auto[402653184:536870911]	auto[1]	9	1			T138	1		T340	1		T350	2
auto[536870912:671088639]	auto[0]	141	1			T104	1		T29	1		T48	2
auto[536870912:671088639]	auto[1]	9	1			T223	1		T225	1		T321	2
auto[671088640:805306367]	auto[0]	118	1			T14	3		T29	1		T48	1
auto[671088640:805306367]	auto[1]	4	1			T223	1		T350	1		T411	1
auto[805306368:939524095]	auto[0]	136	1			T14	1		T79	1		T68	1
auto[805306368:939524095]	auto[1]	9	1			T400	1		T332	2		T242	1
auto[939524096:1073741823]	auto[0]	127	1			T79	1		T104	1		T29	1
auto[939524096:1073741823]	auto[1]	8	1			T107	1		T354	1		T242	1
auto[1073741824:1207959551]	auto[0]	113	1			T4	1		T14	2		T29	2
auto[1073741824:1207959551]	auto[1]	13	1			T122	1		T138	1		T247	3
auto[1207959552:1342177279]	auto[0]	125	1			T79	1		T29	2		T102	1
auto[1207959552:1342177279]	auto[1]	9	1			T247	2		T340	1		T297	1
auto[1342177280:1476395007]	auto[0]	127	1			T14	2		T79	1		T68	1
auto[1342177280:1476395007]	auto[1]	9	1			T138	1		T223	1		T225	1
auto[1476395008:1610612735]	auto[0]	131	1			T4	1		T36	1		T137	1
auto[1476395008:1610612735]	auto[1]	8	1			T122	1		T107	1		T400	1
auto[1610612736:1744830463]	auto[0]	123	1			T14	2		T68	1		T29	1
auto[1610612736:1744830463]	auto[1]	10	1			T247	2		T242	1		T297	1
auto[1744830464:1879048191]	auto[0]	122	1			T14	2		T29	1		T24	1
auto[1744830464:1879048191]	auto[1]	14	1			T122	1		T139	1		T225	2
auto[1879048192:2013265919]	auto[0]	138	1			T14	3		T79	1		T28	1
auto[1879048192:2013265919]	auto[1]	8	1			T107	1		T321	1		T400	1
auto[2013265920:2147483647]	auto[0]	125	1			T14	1		T28	1		T29	1
auto[2013265920:2147483647]	auto[1]	10	1			T225	2		T107	1		T297	1
auto[2147483648:2281701375]	auto[0]	116	1			T14	2		T68	1		T48	1
auto[2147483648:2281701375]	auto[1]	9	1			T107	1		T285	1		T321	1
auto[2281701376:2415919103]	auto[0]	112	1			T14	2		T104	1		T29	1
auto[2281701376:2415919103]	auto[1]	6	1			T139	2		T223	1		T242	1
auto[2415919104:2550136831]	auto[0]	111	1			T29	1		T24	1		T137	1
auto[2415919104:2550136831]	auto[1]	7	1			T122	1		T107	2		T247	1
auto[2550136832:2684354559]	auto[0]	102	1			T14	1		T28	1		T68	1
auto[2550136832:2684354559]	auto[1]	4	1			T400	1		T354	1		T242	1
auto[2684354560:2818572287]	auto[0]	114	1			T48	1		T89	1		T52	1
auto[2684354560:2818572287]	auto[1]	10	1			T107	2		T321	1		T297	1
auto[2818572288:2952790015]	auto[0]	103	1			T79	1		T29	1		T51	1
auto[2818572288:2952790015]	auto[1]	7	1			T139	1		T321	1		T380	1
auto[2952790016:3087007743]	auto[0]	124	1			T104	1		T68	1		T24	1
auto[2952790016:3087007743]	auto[1]	12	1			T223	1		T247	1		T354	1
auto[3087007744:3221225471]	auto[0]	112	1			T14	2		T28	1		T29	1
auto[3087007744:3221225471]	auto[1]	10	1			T138	1		T223	1		T321	1
auto[3221225472:3355443199]	auto[0]	132	1			T16	1		T36	1		T51	1
auto[3221225472:3355443199]	auto[1]	9	1			T138	1		T107	1		T222	1
auto[3355443200:3489660927]	auto[0]	114	1			T104	1		T29	1		T48	3
auto[3355443200:3489660927]	auto[1]	7	1			T411	1		T229	1		T401	1
auto[3489660928:3623878655]	auto[0]	126	1			T16	1		T29	1		T102	1
auto[3489660928:3623878655]	auto[1]	14	1			T139	1		T225	2		T107	2
auto[3623878656:3758096383]	auto[0]	111	1			T14	1		T29	2		T102	1
auto[3623878656:3758096383]	auto[1]	4	1			T139	1		T107	1		T309	1
auto[3758096384:3892314111]	auto[0]	132	1			T14	3		T58	1		T29	1
auto[3758096384:3892314111]	auto[1]	10	1			T122	1		T139	1		T107	1
auto[3892314112:4026531839]	auto[0]	126	1			T14	1		T79	2		T28	1
auto[3892314112:4026531839]	auto[1]	7	1			T138	1		T297	1		T403	1
auto[4026531840:4160749567]	auto[0]	131	1			T16	1		T68	1		T184	1
auto[4026531840:4160749567]	auto[1]	12	1			T139	1		T225	1		T107	1
auto[4160749568:4294967295]	auto[0]	111	1			T14	1		T104	1		T29	1
auto[4160749568:4294967295]	auto[1]	8	1			T225	1		T107	1		T400	1