Unified Coverage Report :: Group Instance : max_creator_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4364

1

T4

4

T14

36

T16

4

auto[1]

2005

1

T4

2

T14

6

T16

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	226	1			T14	2		T101	2		T29	6
auto[134217728:268435455]	190	1			T14	2		T28	2		T68	2
auto[268435456:402653183]	212	1			T14	2		T29	2		T19	2
auto[402653184:536870911]	224	1			T48	4		T20	2		T26	2
auto[536870912:671088639]	204	1			T14	4		T79	4		T28	2
auto[671088640:805306367]	210	1			T4	2		T104	2		T24	2
auto[805306368:939524095]	198	1			T16	2		T184	2		T19	2
auto[939524096:1073741823]	207	1			T4	2		T14	2		T18	2
auto[1073741824:1207959551]	222	1			T14	4		T32	2		T137	2
auto[1207959552:1342177279]	184	1			T102	2		T26	2		T122	2
auto[1342177280:1476395007]	218	1			T79	4		T29	2		T102	4
auto[1476395008:1610612735]	194	1			T36	2		T24	2		T48	2
auto[1610612736:1744830463]	214	1			T14	4		T36	2		T104	2
auto[1744830464:1879048191]	216	1			T29	4		T137	2		T48	2
auto[1879048192:2013265919]	202	1			T29	4		T51	2		T122	2
auto[2013265920:2147483647]	180	1			T4	2		T68	2		T25	2
auto[2147483648:2281701375]	202	1			T14	4		T28	2		T68	4
auto[2281701376:2415919103]	200	1			T29	2		T137	2		T48	4
auto[2415919104:2550136831]	180	1			T20	2		T43	4		T189	2
auto[2550136832:2684354559]	174	1			T104	2		T48	2		T25	2
auto[2684354560:2818572287]	210	1			T79	2		T29	2		T48	2
auto[2818572288:2952790015]	200	1			T14	4		T184	2		T43	2
auto[2952790016:3087007743]	174	1			T14	2		T79	2		T137	2
auto[3087007744:3221225471]	168	1			T29	2		T48	4		T64	2
auto[3221225472:3355443199]	216	1			T29	2		T102	2		T24	2
auto[3355443200:3489660927]	164	1			T14	2		T16	2		T18	2
auto[3489660928:3623878655]	166	1			T14	2		T79	2		T104	4
auto[3623878656:3758096383]	214	1			T104	2		T48	4		T49	2
auto[3758096384:3892314111]	206	1			T14	4		T29	4		T32	2
auto[3892314112:4026531839]	198	1			T14	2		T16	2		T48	2
auto[4026531840:4160749567]	186	1			T68	2		T48	2		T64	2
auto[4160749568:4294967295]	210	1			T14	2		T28	2		T104	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	166	1			T14	2		T29	2		T138	2
auto[0:134217727]	auto[1]	60	1			T101	2		T29	4		T51	4
auto[134217728:268435455]	auto[0]	130	1			T14	2		T28	2		T68	2
auto[134217728:268435455]	auto[1]	60	1			T184	2		T26	2		T56	4
auto[268435456:402653183]	auto[0]	140	1			T14	2		T29	2		T64	2
auto[268435456:402653183]	auto[1]	72	1			T19	2		T27	2		T249	2
auto[402653184:536870911]	auto[0]	146	1			T48	2		T20	2		T138	2
auto[402653184:536870911]	auto[1]	78	1			T48	2		T26	2		T65	2
auto[536870912:671088639]	auto[0]	140	1			T14	2		T79	4		T48	2
auto[536870912:671088639]	auto[1]	64	1			T14	2		T28	2		T25	2
auto[671088640:805306367]	auto[0]	148	1			T104	2		T122	2		T65	2
auto[671088640:805306367]	auto[1]	62	1			T4	2		T24	2		T48	2
auto[805306368:939524095]	auto[0]	152	1			T184	2		T19	2		T43	2
auto[805306368:939524095]	auto[1]	46	1			T16	2		T138	2		T202	2
auto[939524096:1073741823]	auto[0]	144	1			T4	2		T18	2		T51	2
auto[939524096:1073741823]	auto[1]	63	1			T14	2		T79	2		T89	2
auto[1073741824:1207959551]	auto[0]	138	1			T14	4		T137	2		T48	4
auto[1073741824:1207959551]	auto[1]	84	1			T32	2		T26	2		T44	2
auto[1207959552:1342177279]	auto[0]	122	1			T122	2		T223	2		T224	4
auto[1207959552:1342177279]	auto[1]	62	1			T102	2		T26	2		T44	6
auto[1342177280:1476395007]	auto[0]	150	1			T79	2		T29	2		T102	2
auto[1342177280:1476395007]	auto[1]	68	1			T79	2		T102	2		T271	2
auto[1476395008:1610612735]	auto[0]	130	1			T64	2		T385	2		T249	2
auto[1476395008:1610612735]	auto[1]	64	1			T36	2		T24	2		T48	2
auto[1610612736:1744830463]	auto[0]	152	1			T14	4		T104	2		T68	2
auto[1610612736:1744830463]	auto[1]	62	1			T36	2		T103	2		T56	2
auto[1744830464:1879048191]	auto[0]	140	1			T29	2		T137	2		T48	2
auto[1744830464:1879048191]	auto[1]	76	1			T29	2		T385	2		T56	2
auto[1879048192:2013265919]	auto[0]	144	1			T29	2		T51	2		T122	2
auto[1879048192:2013265919]	auto[1]	58	1			T29	2		T56	4		T83	2
auto[2013265920:2147483647]	auto[0]	120	1			T4	2		T68	2		T25	2
auto[2013265920:2147483647]	auto[1]	60	1			T379	2		T412	2		T203	2
auto[2147483648:2281701375]	auto[0]	130	1			T14	4		T28	2		T68	4
auto[2147483648:2281701375]	auto[1]	72	1			T29	2		T32	2		T24	2
auto[2281701376:2415919103]	auto[0]	156	1			T29	2		T137	2		T48	2
auto[2281701376:2415919103]	auto[1]	44	1			T48	2		T45	2		T253	2
auto[2415919104:2550136831]	auto[0]	122	1			T20	2		T43	4		T189	2
auto[2415919104:2550136831]	auto[1]	58	1			T27	2		T9	2		T187	2
auto[2550136832:2684354559]	auto[0]	122	1			T48	2		T25	2		T139	2
auto[2550136832:2684354559]	auto[1]	52	1			T104	2		T248	2		T239	4
auto[2684354560:2818572287]	auto[0]	136	1			T79	2		T29	2		T48	2
auto[2684354560:2818572287]	auto[1]	74	1			T89	2		T379	2		T11	2
auto[2818572288:2952790015]	auto[0]	130	1			T14	4		T184	2		T43	2
auto[2818572288:2952790015]	auto[1]	70	1			T56	2		T44	2		T45	2
auto[2952790016:3087007743]	auto[0]	118	1			T14	2		T79	2		T184	2
auto[2952790016:3087007743]	auto[1]	56	1			T137	2		T43	2		T89	2
auto[3087007744:3221225471]	auto[0]	116	1			T29	2		T48	4		T64	2
auto[3087007744:3221225471]	auto[1]	52	1			T53	2		T186	2		T187	2
auto[3221225472:3355443199]	auto[0]	136	1			T24	2		T48	2		T49	2
auto[3221225472:3355443199]	auto[1]	80	1			T29	2		T102	2		T89	2
auto[3355443200:3489660927]	auto[0]	108	1			T16	2		T18	2		T20	4
auto[3355443200:3489660927]	auto[1]	56	1			T14	2		T52	2		T40	4
auto[3489660928:3623878655]	auto[0]	118	1			T14	2		T79	2		T104	4
auto[3489660928:3623878655]	auto[1]	48	1			T101	2		T102	2		T103	2
auto[3623878656:3758096383]	auto[0]	162	1			T104	2		T48	4		T49	2
auto[3623878656:3758096383]	auto[1]	52	1			T56	2		T44	2		T413	2
auto[3758096384:3892314111]	auto[0]	140	1			T14	4		T29	4		T244	2
auto[3758096384:3892314111]	auto[1]	66	1			T32	2		T138	2		T183	2
auto[3892314112:4026531839]	auto[0]	140	1			T14	2		T16	2		T48	2
auto[3892314112:4026531839]	auto[1]	58	1			T30	2		T65	2		T187	2
auto[4026531840:4160749567]	auto[0]	132	1			T68	2		T48	2		T64	2
auto[4026531840:4160749567]	auto[1]	54	1			T339	2		T281	2		T189	2
auto[4160749568:4294967295]	auto[0]	136	1			T14	2		T104	2		T68	2
auto[4160749568:4294967295]	auto[1]	74	1			T28	2		T58	2		T89	2