Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.82	99.10	98.11	98.36	100.00	99.11	98.41	91.66

Total test records in report: 1068

T311	/workspace/coverage/default/34.keymgr_sideload_protect.801058090	Apr 20 04:08:17 PM PDT 24	Apr 20 04:08:20 PM PDT 24	57770601 ps
T1014	/workspace/coverage/default/5.keymgr_sideload_otbn.4271766811	Apr 20 04:05:09 PM PDT 24	Apr 20 04:05:22 PM PDT 24	447415107 ps
T1015	/workspace/coverage/default/28.keymgr_sideload_otbn.1415458939	Apr 20 04:07:40 PM PDT 24	Apr 20 04:07:43 PM PDT 24	769073356 ps
T218	/workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.2671437020	Apr 20 04:09:06 PM PDT 24	Apr 20 04:09:18 PM PDT 24	456666229 ps
T1016	/workspace/coverage/default/5.keymgr_lc_disable.2466131668	Apr 20 04:05:10 PM PDT 24	Apr 20 04:05:14 PM PDT 24	684686404 ps
T1017	/workspace/coverage/default/28.keymgr_alert_test.3911791589	Apr 20 04:07:46 PM PDT 24	Apr 20 04:07:47 PM PDT 24	29290165 ps
T1018	/workspace/coverage/default/12.keymgr_custom_cm.2417548086	Apr 20 04:06:08 PM PDT 24	Apr 20 04:06:13 PM PDT 24	151128017 ps
T1019	/workspace/coverage/default/12.keymgr_hwsw_invalid_input.797948739	Apr 20 04:06:05 PM PDT 24	Apr 20 04:06:13 PM PDT 24	381885923 ps
T1020	/workspace/coverage/default/29.keymgr_sw_invalid_input.1397891051	Apr 20 04:07:54 PM PDT 24	Apr 20 04:07:59 PM PDT 24	683700482 ps
T421	/workspace/coverage/default/5.keymgr_cfg_regwen.2330401967	Apr 20 04:05:10 PM PDT 24	Apr 20 04:05:13 PM PDT 24	129966662 ps
T1021	/workspace/coverage/default/34.keymgr_random.889537068	Apr 20 04:08:16 PM PDT 24	Apr 20 04:08:20 PM PDT 24	80702626 ps
T1022	/workspace/coverage/default/14.keymgr_hwsw_invalid_input.295308824	Apr 20 04:06:18 PM PDT 24	Apr 20 04:06:23 PM PDT 24	183094744 ps
T1023	/workspace/coverage/default/32.keymgr_kmac_rsp_err.2499039893	Apr 20 04:08:08 PM PDT 24	Apr 20 04:08:12 PM PDT 24	56917284 ps
T1024	/workspace/coverage/default/12.keymgr_smoke.4033337902	Apr 20 04:05:59 PM PDT 24	Apr 20 04:06:03 PM PDT 24	231055614 ps
T1025	/workspace/coverage/default/28.keymgr_sideload.3360290180	Apr 20 04:07:40 PM PDT 24	Apr 20 04:07:46 PM PDT 24	663490614 ps
T1026	/workspace/coverage/default/10.keymgr_custom_cm.2120442560	Apr 20 04:05:49 PM PDT 24	Apr 20 04:06:04 PM PDT 24	805327489 ps
T1027	/workspace/coverage/default/38.keymgr_lc_disable.4146197068	Apr 20 04:08:42 PM PDT 24	Apr 20 04:08:46 PM PDT 24	257092221 ps
T1028	/workspace/coverage/default/47.keymgr_sideload_kmac.2211117303	Apr 20 04:09:20 PM PDT 24	Apr 20 04:09:24 PM PDT 24	141752337 ps
T1029	/workspace/coverage/default/18.keymgr_stress_all.902758458	Apr 20 04:06:45 PM PDT 24	Apr 20 04:06:48 PM PDT 24	162142799 ps
T1030	/workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.568940478	Apr 20 04:05:09 PM PDT 24	Apr 20 04:05:18 PM PDT 24	202207431 ps
T1031	/workspace/coverage/default/27.keymgr_alert_test.3799368784	Apr 20 04:07:41 PM PDT 24	Apr 20 04:07:43 PM PDT 24	18566691 ps
T1032	/workspace/coverage/default/2.keymgr_sideload.206978411	Apr 20 04:04:37 PM PDT 24	Apr 20 04:04:46 PM PDT 24	1047681204 ps
T115	/workspace/coverage/default/30.keymgr_custom_cm.2871612017	Apr 20 04:07:59 PM PDT 24	Apr 20 04:08:05 PM PDT 24	157262477 ps
T1033	/workspace/coverage/default/14.keymgr_alert_test.825894718	Apr 20 04:06:16 PM PDT 24	Apr 20 04:06:17 PM PDT 24	45322177 ps
T1034	/workspace/coverage/default/44.keymgr_alert_test.3131970446	Apr 20 04:09:15 PM PDT 24	Apr 20 04:09:16 PM PDT 24	39428854 ps
T1035	/workspace/coverage/default/14.keymgr_kmac_rsp_err.2096172652	Apr 20 04:06:17 PM PDT 24	Apr 20 04:06:23 PM PDT 24	451167914 ps
T1036	/workspace/coverage/default/15.keymgr_stress_all.214299376	Apr 20 04:06:28 PM PDT 24	Apr 20 04:07:19 PM PDT 24	4747529502 ps
T1037	/workspace/coverage/default/49.keymgr_sideload_aes.3149731069	Apr 20 04:09:30 PM PDT 24	Apr 20 04:09:34 PM PDT 24	1281998045 ps
T1038	/workspace/coverage/default/5.keymgr_sideload_protect.2023069718	Apr 20 04:05:13 PM PDT 24	Apr 20 04:05:24 PM PDT 24	394096550 ps
T1039	/workspace/coverage/default/8.keymgr_hwsw_invalid_input.3551238279	Apr 20 04:05:35 PM PDT 24	Apr 20 04:05:40 PM PDT 24	106560337 ps
T1040	/workspace/coverage/default/10.keymgr_hwsw_invalid_input.3806237006	Apr 20 04:05:50 PM PDT 24	Apr 20 04:05:54 PM PDT 24	290808127 ps
T1041	/workspace/coverage/default/4.keymgr_sideload_aes.634148681	Apr 20 04:05:03 PM PDT 24	Apr 20 04:05:48 PM PDT 24	3642181768 ps
T1042	/workspace/coverage/default/49.keymgr_smoke.2348331150	Apr 20 04:09:28 PM PDT 24	Apr 20 04:09:40 PM PDT 24	523038205 ps
T417	/workspace/coverage/default/44.keymgr_cfg_regwen.4237382479	Apr 20 04:09:08 PM PDT 24	Apr 20 04:09:19 PM PDT 24	1565912885 ps
T1043	/workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.634386400	Apr 20 04:06:31 PM PDT 24	Apr 20 04:06:39 PM PDT 24	211754467 ps
T1044	/workspace/coverage/default/9.keymgr_sideload_protect.2853810192	Apr 20 04:05:43 PM PDT 24	Apr 20 04:05:49 PM PDT 24	641726196 ps
T1045	/workspace/coverage/default/11.keymgr_kmac_rsp_err.1493467993	Apr 20 04:05:57 PM PDT 24	Apr 20 04:06:05 PM PDT 24	3068834397 ps
T314	/workspace/coverage/default/38.keymgr_random.1876382546	Apr 20 04:08:38 PM PDT 24	Apr 20 04:09:23 PM PDT 24	6995516968 ps
T1046	/workspace/coverage/default/1.keymgr_sideload.3802545942	Apr 20 04:04:27 PM PDT 24	Apr 20 04:04:31 PM PDT 24	459071102 ps
T419	/workspace/coverage/default/40.keymgr_cfg_regwen.3325949639	Apr 20 04:08:49 PM PDT 24	Apr 20 04:08:53 PM PDT 24	225602164 ps
T1047	/workspace/coverage/default/45.keymgr_random.2765364789	Apr 20 04:09:13 PM PDT 24	Apr 20 04:09:19 PM PDT 24	828573284 ps
T305	/workspace/coverage/default/23.keymgr_stress_all.3478606357	Apr 20 04:07:16 PM PDT 24	Apr 20 04:08:03 PM PDT 24	7388565519 ps
T1048	/workspace/coverage/default/25.keymgr_direct_to_disabled.850391445	Apr 20 04:07:23 PM PDT 24	Apr 20 04:07:41 PM PDT 24	1559325682 ps
T1049	/workspace/coverage/default/46.keymgr_random.2027533499	Apr 20 04:09:20 PM PDT 24	Apr 20 04:09:30 PM PDT 24	480600076 ps
T1050	/workspace/coverage/default/25.keymgr_alert_test.3874825462	Apr 20 04:07:31 PM PDT 24	Apr 20 04:07:32 PM PDT 24	17415118 ps
T1051	/workspace/coverage/default/43.keymgr_cfg_regwen.1900845314	Apr 20 04:09:02 PM PDT 24	Apr 20 04:09:08 PM PDT 24	111372159 ps
T1052	/workspace/coverage/default/48.keymgr_random.2431492447	Apr 20 04:09:23 PM PDT 24	Apr 20 04:09:28 PM PDT 24	351738735 ps
T1053	/workspace/coverage/default/40.keymgr_sideload_kmac.3137912077	Apr 20 04:08:48 PM PDT 24	Apr 20 04:08:51 PM PDT 24	61521809 ps
T1054	/workspace/coverage/default/34.keymgr_alert_test.3755997966	Apr 20 04:08:19 PM PDT 24	Apr 20 04:08:21 PM PDT 24	12917363 ps
T420	/workspace/coverage/default/20.keymgr_cfg_regwen.647177283	Apr 20 04:06:56 PM PDT 24	Apr 20 04:07:04 PM PDT 24	520975993 ps
T106	/workspace/coverage/default/4.keymgr_sec_cm.4026969999	Apr 20 04:05:09 PM PDT 24	Apr 20 04:05:33 PM PDT 24	2774685651 ps
T1055	/workspace/coverage/default/24.keymgr_custom_cm.2230017085	Apr 20 04:07:20 PM PDT 24	Apr 20 04:07:22 PM PDT 24	295048812 ps
T424	/workspace/coverage/default/14.keymgr_cfg_regwen.3437788744	Apr 20 04:06:17 PM PDT 24	Apr 20 04:06:30 PM PDT 24	717858893 ps
T1056	/workspace/coverage/default/29.keymgr_smoke.938829213	Apr 20 04:07:47 PM PDT 24	Apr 20 04:07:51 PM PDT 24	61625767 ps
T1057	/workspace/coverage/default/39.keymgr_sideload_protect.1678395341	Apr 20 04:08:43 PM PDT 24	Apr 20 04:08:54 PM PDT 24	638667172 ps
T1058	/workspace/coverage/default/49.keymgr_hwsw_invalid_input.255931715	Apr 20 04:09:33 PM PDT 24	Apr 20 04:09:43 PM PDT 24	332150471 ps
T1059	/workspace/coverage/default/26.keymgr_sw_invalid_input.3017677378	Apr 20 04:07:36 PM PDT 24	Apr 20 04:08:45 PM PDT 24	10912823545 ps
T1060	/workspace/coverage/default/12.keymgr_random.3371680112	Apr 20 04:06:02 PM PDT 24	Apr 20 04:06:06 PM PDT 24	108389036 ps
T1061	/workspace/coverage/default/1.keymgr_sideload_protect.4292055270	Apr 20 04:04:31 PM PDT 24	Apr 20 04:04:35 PM PDT 24	180152823 ps
T1062	/workspace/coverage/default/8.keymgr_kmac_rsp_err.1627729751	Apr 20 04:05:39 PM PDT 24	Apr 20 04:05:50 PM PDT 24	1211097115 ps
T1063	/workspace/coverage/default/16.keymgr_sideload_aes.3595779822	Apr 20 04:06:26 PM PDT 24	Apr 20 04:06:34 PM PDT 24	482469269 ps
T160	/workspace/coverage/default/8.keymgr_sync_async_fault_cross.2869824635	Apr 20 04:05:38 PM PDT 24	Apr 20 04:05:42 PM PDT 24	69365019 ps
T1064	/workspace/coverage/default/35.keymgr_sideload_aes.1074874752	Apr 20 04:08:19 PM PDT 24	Apr 20 04:08:22 PM PDT 24	122430343 ps
T1065	/workspace/coverage/default/41.keymgr_smoke.3861538850	Apr 20 04:08:49 PM PDT 24	Apr 20 04:08:52 PM PDT 24	61240510 ps
T1066	/workspace/coverage/default/44.keymgr_sideload_kmac.1131196143	Apr 20 04:09:05 PM PDT 24	Apr 20 04:09:09 PM PDT 24	226463578 ps
T1067	/workspace/coverage/default/27.keymgr_sideload_otbn.3660805022	Apr 20 04:07:36 PM PDT 24	Apr 20 04:07:39 PM PDT 24	222538079 ps
T1068	/workspace/coverage/default/6.keymgr_sideload_aes.2999680404	Apr 20 04:05:16 PM PDT 24	Apr 20 04:05:20 PM PDT 24	102714510 ps
T423	/workspace/coverage/default/27.keymgr_cfg_regwen.1425424452	Apr 20 04:07:37 PM PDT 24	Apr 20 04:07:49 PM PDT 24	473401132 ps

Test location	/workspace/coverage/default/8.keymgr_stress_all.4156615382
Short name	T14
Test name
Test status
Simulation time	11199701032 ps
CPU time	79.78 seconds
Started	Apr 20 04:05:36 PM PDT 24
Finished	Apr 20 04:06:56 PM PDT 24
Peak memory	215692 kb
Host	smart-209a40b3-660f-4c79-8b3a-39e79dcdfe96
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156615382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.4156615382
Directory	/workspace/8.keymgr_stress_all/latest

Test location	/workspace/coverage/default/39.keymgr_stress_all.195094495
Short name	T29
Test name
Test status
Simulation time	1194813118 ps
CPU time	16.4 seconds
Started	Apr 20 04:08:40 PM PDT 24
Finished	Apr 20 04:08:57 PM PDT 24
Peak memory	215536 kb
Host	smart-c0b44452-42cd-405f-ab9e-6b7a6ee58c24
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195094495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.195094495
Directory	/workspace/39.keymgr_stress_all/latest

Test location	/workspace/coverage/default/22.keymgr_stress_all.584448373
Short name	T56
Test name
Test status
Simulation time	15627965721 ps
CPU time	118.67 seconds
Started	Apr 20 04:07:11 PM PDT 24
Finished	Apr 20 04:09:10 PM PDT 24
Peak memory	222588 kb
Host	smart-35ec972f-0b2f-4e01-ae9b-b151509b8419
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584448373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.584448373
Directory	/workspace/22.keymgr_stress_all/latest

Test location	/workspace/coverage/default/1.keymgr_sec_cm.2698169292
Short name	T6
Test name
Test status
Simulation time	6559978538 ps
CPU time	167.61 seconds
Started	Apr 20 04:04:35 PM PDT 24
Finished	Apr 20 04:07:23 PM PDT 24
Peak memory	286300 kb
Host	smart-c0faaf88-98ca-41c2-a544-24a2232805d1
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698169292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.2698169292
Directory	/workspace/1.keymgr_sec_cm/latest

Test location	/workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.3220266693
Short name	T101
Test name
Test status
Simulation time	303847511 ps
CPU time	5.27 seconds
Started	Apr 20 04:07:13 PM PDT 24
Finished	Apr 20 04:07:18 PM PDT 24
Peak memory	218780 kb
Host	smart-079edb86-5e28-42c4-8a2c-03ceed1f4f98
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220266693 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.3220266693
Directory	/workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/19.keymgr_stress_all.3690754553
Short name	T48
Test name
Test status
Simulation time	647998029 ps
CPU time	24.82 seconds
Started	Apr 20 04:06:51 PM PDT 24
Finished	Apr 20 04:07:16 PM PDT 24
Peak memory	222396 kb
Host	smart-c9905b75-10b0-42bd-9483-692524da42be
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690754553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.3690754553
Directory	/workspace/19.keymgr_stress_all/latest

Test location	/workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.3938001727
Short name	T61
Test name
Test status
Simulation time	363288472 ps
CPU time	18.41 seconds
Started	Apr 20 04:09:30 PM PDT 24
Finished	Apr 20 04:09:49 PM PDT 24
Peak memory	222748 kb
Host	smart-18b697f8-bf02-40d8-bfd0-aadd406d1b07
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938001727 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.3938001727
Directory	/workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/20.keymgr_custom_cm.1564059928
Short name	T10
Test name
Test status
Simulation time	51773009 ps
CPU time	3.29 seconds
Started	Apr 20 04:06:55 PM PDT 24
Finished	Apr 20 04:06:59 PM PDT 24
Peak memory	221564 kb
Host	smart-68521fd7-da0b-4053-93ce-f0d5f034821f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1564059928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.1564059928
Directory	/workspace/20.keymgr_custom_cm/latest

Test location	/workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.1994696494
Short name	T121
Test name
Test status
Simulation time	439599806 ps
CPU time	8.51 seconds
Started	Apr 20 04:10:08 PM PDT 24
Finished	Apr 20 04:10:17 PM PDT 24
Peak memory	214116 kb
Host	smart-e10c726c-307d-4068-b175-37d351d6a98b
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994696494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17 .keymgr_shadow_reg_errors_with_csr_rw.1994696494
Directory	/workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/default/22.keymgr_cfg_regwen.230299143
Short name	T107
Test name
Test status
Simulation time	4963020226 ps
CPU time	130.16 seconds
Started	Apr 20 04:07:05 PM PDT 24
Finished	Apr 20 04:09:16 PM PDT 24
Peak memory	215624 kb
Host	smart-e22565f1-cecb-4903-a2fd-ec2ddb68567c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=230299143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.230299143
Directory	/workspace/22.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/34.keymgr_kmac_rsp_err.3377770229
Short name	T26
Test name
Test status
Simulation time	187858585 ps
CPU time	7.06 seconds
Started	Apr 20 04:08:16 PM PDT 24
Finished	Apr 20 04:08:23 PM PDT 24
Peak memory	222532 kb
Host	smart-684d142d-88c0-4894-abb9-5813c13b7d10
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3377770229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.3377770229
Directory	/workspace/34.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/1.keymgr_stress_all.3423168517
Short name	T46
Test name
Test status
Simulation time	2244206669 ps
CPU time	13.29 seconds
Started	Apr 20 04:04:31 PM PDT 24
Finished	Apr 20 04:04:45 PM PDT 24
Peak memory	215800 kb
Host	smart-474e4675-ad11-4f87-b8eb-1c6ae07efde3
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423168517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.3423168517
Directory	/workspace/1.keymgr_stress_all/latest

Test location	/workspace/coverage/default/24.keymgr_stress_all.1544885472
Short name	T45
Test name
Test status
Simulation time	5303752501 ps
CPU time	50.93 seconds
Started	Apr 20 04:07:20 PM PDT 24
Finished	Apr 20 04:08:12 PM PDT 24
Peak memory	222564 kb
Host	smart-5d2a43d5-0aaa-4497-a79b-78b0d1668c23
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544885472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.1544885472
Directory	/workspace/24.keymgr_stress_all/latest

Test location	/workspace/coverage/default/23.keymgr_cfg_regwen.4047151200
Short name	T139
Test name
Test status
Simulation time	829718819 ps
CPU time	16.67 seconds
Started	Apr 20 04:07:16 PM PDT 24
Finished	Apr 20 04:07:33 PM PDT 24
Peak memory	215076 kb
Host	smart-d444b17e-dbc9-48ba-bd2c-9b5693f82966
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4047151200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.4047151200
Directory	/workspace/23.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.1233150983
Short name	T102
Test name
Test status
Simulation time	2918126156 ps
CPU time	9.21 seconds
Started	Apr 20 04:04:24 PM PDT 24
Finished	Apr 20 04:04:33 PM PDT 24
Peak memory	222600 kb
Host	smart-c5bf2257-cd71-424d-ae80-928089e1f4a4
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233150983 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.1233150983
Directory	/workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/34.keymgr_cfg_regwen.3805968034
Short name	T138
Test name
Test status
Simulation time	3522435158 ps
CPU time	40.29 seconds
Started	Apr 20 04:08:17 PM PDT 24
Finished	Apr 20 04:08:58 PM PDT 24
Peak memory	214412 kb
Host	smart-5dd7203e-6f9e-4a4e-a005-1d0ddacbd97b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3805968034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.3805968034
Directory	/workspace/34.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/21.keymgr_kmac_rsp_err.1872383384
Short name	T68
Test name
Test status
Simulation time	376839643 ps
CPU time	5.18 seconds
Started	Apr 20 04:06:57 PM PDT 24
Finished	Apr 20 04:07:02 PM PDT 24
Peak memory	210292 kb
Host	smart-a34a5fc6-c21f-4cce-8acf-d96dbf226488
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1872383384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.1872383384
Directory	/workspace/21.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/48.keymgr_cfg_regwen.1346327139
Short name	T380
Test name
Test status
Simulation time	145464134 ps
CPU time	7.9 seconds
Started	Apr 20 04:09:25 PM PDT 24
Finished	Apr 20 04:09:33 PM PDT 24
Peak memory	214440 kb
Host	smart-18a27959-0f56-4bf6-9187-88d9a8dcdeb4
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1346327139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.1346327139
Directory	/workspace/48.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/3.keymgr_stress_all.3836569193
Short name	T248
Test name
Test status
Simulation time	4278869239 ps
CPU time	39.31 seconds
Started	Apr 20 04:05:00 PM PDT 24
Finished	Apr 20 04:05:40 PM PDT 24
Peak memory	222572 kb
Host	smart-e5513fe2-5337-484b-aca7-770e2624f6e6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836569193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.3836569193
Directory	/workspace/3.keymgr_stress_all/latest

Test location	/workspace/coverage/default/27.keymgr_cfg_regwen.1425424452
Short name	T423
Test name
Test status
Simulation time	473401132 ps
CPU time	11.76 seconds
Started	Apr 20 04:07:37 PM PDT 24
Finished	Apr 20 04:07:49 PM PDT 24
Peak memory	214340 kb
Host	smart-4b06344a-4ca8-4a15-80dd-39dc650eb37f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1425424452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.1425424452
Directory	/workspace/27.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.1477721005
Short name	T135
Test name
Test status
Simulation time	1930956232 ps
CPU time	14.12 seconds
Started	Apr 20 04:10:06 PM PDT 24
Finished	Apr 20 04:10:20 PM PDT 24
Peak memory	213792 kb
Host	smart-163b8869-4494-45bd-b4df-b36fdfd71f40
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477721005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er r.1477721005
Directory	/workspace/15.keymgr_tl_intg_err/latest

Test location	/workspace/coverage/default/41.keymgr_custom_cm.3754860378
Short name	T60
Test name
Test status
Simulation time	243177642 ps
CPU time	5.81 seconds
Started	Apr 20 04:08:51 PM PDT 24
Finished	Apr 20 04:08:57 PM PDT 24
Peak memory	220328 kb
Host	smart-3f2d5f0a-ea7d-4bce-8bd9-dce80dd666a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3754860378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.3754860378
Directory	/workspace/41.keymgr_custom_cm/latest

Test location	/workspace/coverage/cover_reg_top/13.keymgr_tl_errors.801055850
Short name	T476
Test name
Test status
Simulation time	44662903 ps
CPU time	2.46 seconds
Started	Apr 20 04:10:10 PM PDT 24
Finished	Apr 20 04:10:13 PM PDT 24
Peak memory	213832 kb
Host	smart-a557b58e-d2d8-48af-b55d-d562877e96a9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801055850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.801055850
Directory	/workspace/13.keymgr_tl_errors/latest

Test location	/workspace/coverage/default/6.keymgr_cfg_regwen.1239245914
Short name	T247
Test name
Test status
Simulation time	650571119 ps
CPU time	8.35 seconds
Started	Apr 20 04:05:16 PM PDT 24
Finished	Apr 20 04:05:25 PM PDT 24
Peak memory	214264 kb
Host	smart-89ceee46-5c95-43af-8298-58ea568cd028
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1239245914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.1239245914
Directory	/workspace/6.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/9.keymgr_custom_cm.2720568945
Short name	T41
Test name
Test status
Simulation time	134238610 ps
CPU time	2.87 seconds
Started	Apr 20 04:05:49 PM PDT 24
Finished	Apr 20 04:05:52 PM PDT 24
Peak memory	220536 kb
Host	smart-e8192066-1c8e-4ed1-b09e-2642cf947817
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2720568945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.2720568945
Directory	/workspace/9.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/22.keymgr_hwsw_invalid_input.537551573
Short name	T27
Test name
Test status
Simulation time	346951485 ps
CPU time	8.39 seconds
Started	Apr 20 04:07:07 PM PDT 24
Finished	Apr 20 04:07:15 PM PDT 24
Peak memory	219180 kb
Host	smart-0d4506d1-a0a6-4d41-b8a7-5583e4616525
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=537551573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.537551573
Directory	/workspace/22.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.2331259629
Short name	T117
Test name
Test status
Simulation time	424692751 ps
CPU time	6.46 seconds
Started	Apr 20 04:09:42 PM PDT 24
Finished	Apr 20 04:09:48 PM PDT 24
Peak memory	214012 kb
Host	smart-97ac1b0c-2ac5-4107-af24-727663c2475a
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331259629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado w_reg_errors.2331259629
Directory	/workspace/1.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/default/2.keymgr_cfg_regwen.2419503992
Short name	T400
Test name
Test status
Simulation time	1133943166 ps
CPU time	15.03 seconds
Started	Apr 20 04:04:39 PM PDT 24
Finished	Apr 20 04:04:54 PM PDT 24
Peak memory	214984 kb
Host	smart-e89b5a9e-cb7d-4588-9a94-42d132685b37
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2419503992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.2419503992
Directory	/workspace/2.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/24.keymgr_hwsw_invalid_input.23481844
Short name	T93
Test name
Test status
Simulation time	6543450281 ps
CPU time	72.43 seconds
Started	Apr 20 04:07:22 PM PDT 24
Finished	Apr 20 04:08:34 PM PDT 24
Peak memory	221672 kb
Host	smart-aa3fdbe9-faa3-42b7-9717-a4d2b8a4a9db
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=23481844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.23481844
Directory	/workspace/24.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/42.keymgr_stress_all.860146818
Short name	T65
Test name
Test status
Simulation time	9656150989 ps
CPU time	68.8 seconds
Started	Apr 20 04:08:59 PM PDT 24
Finished	Apr 20 04:10:08 PM PDT 24
Peak memory	222616 kb
Host	smart-b6e8acbc-c861-4bab-95d3-74771a157656
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860146818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.860146818
Directory	/workspace/42.keymgr_stress_all/latest

Test location	/workspace/coverage/default/46.keymgr_stress_all.3982955267
Short name	T72
Test name
Test status
Simulation time	769191044 ps
CPU time	38.49 seconds
Started	Apr 20 04:09:18 PM PDT 24
Finished	Apr 20 04:09:57 PM PDT 24
Peak memory	217196 kb
Host	smart-0cda5f2e-268d-4ffe-8f53-dee8b2557e7d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982955267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.3982955267
Directory	/workspace/46.keymgr_stress_all/latest

Test location	/workspace/coverage/default/4.keymgr_custom_cm.1972286936
Short name	T113
Test name
Test status
Simulation time	95288027 ps
CPU time	3.07 seconds
Started	Apr 20 04:05:03 PM PDT 24
Finished	Apr 20 04:05:06 PM PDT 24
Peak memory	217444 kb
Host	smart-70353df5-c664-4c3d-a8ed-f77db873b926
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1972286936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.1972286936
Directory	/workspace/4.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/26.keymgr_cfg_regwen.291914006
Short name	T321
Test name
Test status
Simulation time	6675131085 ps
CPU time	100.14 seconds
Started	Apr 20 04:07:34 PM PDT 24
Finished	Apr 20 04:09:15 PM PDT 24
Peak memory	219984 kb
Host	smart-59833d63-2f46-445c-b972-4b5251bcae0f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=291914006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.291914006
Directory	/workspace/26.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/18.keymgr_custom_cm.403696136
Short name	T34
Test name
Test status
Simulation time	93430147 ps
CPU time	3.11 seconds
Started	Apr 20 04:06:45 PM PDT 24
Finished	Apr 20 04:06:49 PM PDT 24
Peak memory	221452 kb
Host	smart-4ea27b33-5835-4d63-803f-c09c827fe8d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=403696136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.403696136
Directory	/workspace/18.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/1.keymgr_kmac_rsp_err.2018769889
Short name	T278
Test name
Test status
Simulation time	168846682 ps
CPU time	4.52 seconds
Started	Apr 20 04:04:30 PM PDT 24
Finished	Apr 20 04:04:35 PM PDT 24
Peak memory	222428 kb
Host	smart-f46e1ec6-4f2e-4dee-b5a9-d7c0415fecc1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2018769889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.2018769889
Directory	/workspace/1.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/28.keymgr_kmac_rsp_err.580665872
Short name	T94
Test name
Test status
Simulation time	119000894 ps
CPU time	4.6 seconds
Started	Apr 20 04:07:42 PM PDT 24
Finished	Apr 20 04:07:47 PM PDT 24
Peak memory	222440 kb
Host	smart-03673384-2cf1-4967-ba3c-7a3441048f2d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=580665872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.580665872
Directory	/workspace/28.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/10.keymgr_cfg_regwen.1230601310
Short name	T229
Test name
Test status
Simulation time	215188333 ps
CPU time	4.09 seconds
Started	Apr 20 04:05:47 PM PDT 24
Finished	Apr 20 04:05:51 PM PDT 24
Peak memory	215060 kb
Host	smart-f11fbe4e-1277-48e1-9578-cf590b36c456
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1230601310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.1230601310
Directory	/workspace/10.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/7.keymgr_stress_all.1287571044
Short name	T237
Test name
Test status
Simulation time	3019659645 ps
CPU time	34.87 seconds
Started	Apr 20 04:05:33 PM PDT 24
Finished	Apr 20 04:06:08 PM PDT 24
Peak memory	222560 kb
Host	smart-a9089cb7-e9f7-4eea-b2ce-ecc2b5b84b32
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287571044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.1287571044
Directory	/workspace/7.keymgr_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.2038917236
Short name	T136
Test name
Test status
Simulation time	1415007203 ps
CPU time	42.63 seconds
Started	Apr 20 04:09:54 PM PDT 24
Finished	Apr 20 04:10:37 PM PDT 24
Peak memory	212032 kb
Host	smart-e055e1ee-2fde-4467-a1e3-e7dcf549199d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038917236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err .2038917236
Directory	/workspace/6.keymgr_tl_intg_err/latest

Test location	/workspace/coverage/default/48.keymgr_hwsw_invalid_input.1892165967
Short name	T89
Test name
Test status
Simulation time	98236666 ps
CPU time	4.29 seconds
Started	Apr 20 04:09:27 PM PDT 24
Finished	Apr 20 04:09:32 PM PDT 24
Peak memory	214420 kb
Host	smart-2f4c0f24-9948-44ef-b124-b52ca15542fe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1892165967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.1892165967
Directory	/workspace/48.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/11.keymgr_cfg_regwen.1178358873
Short name	T341
Test name
Test status
Simulation time	1289341237 ps
CPU time	6.01 seconds
Started	Apr 20 04:05:56 PM PDT 24
Finished	Apr 20 04:06:02 PM PDT 24
Peak memory	214848 kb
Host	smart-b4d4b236-fc7c-46ae-954b-9a977ea03b3d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1178358873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.1178358873
Directory	/workspace/11.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/15.keymgr_alert_test.1445072525
Short name	T553
Test name
Test status
Simulation time	20994979 ps
CPU time	0.88 seconds
Started	Apr 20 04:06:33 PM PDT 24
Finished	Apr 20 04:06:35 PM PDT 24
Peak memory	205844 kb
Host	smart-b0fde12b-0157-40ed-a71c-6dcd027b77ad
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445072525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.1445072525
Directory	/workspace/15.keymgr_alert_test/latest

Test location	/workspace/coverage/default/30.keymgr_custom_cm.2871612017
Short name	T115
Test name
Test status
Simulation time	157262477 ps
CPU time	5.38 seconds
Started	Apr 20 04:07:59 PM PDT 24
Finished	Apr 20 04:08:05 PM PDT 24
Peak memory	218512 kb
Host	smart-fe3cc1ad-1ba7-4390-85bd-0ba588e1ebbd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2871612017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.2871612017
Directory	/workspace/30.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/0.keymgr_stress_all.1068627204
Short name	T304
Test name
Test status
Simulation time	3994766960 ps
CPU time	49.85 seconds
Started	Apr 20 04:04:23 PM PDT 24
Finished	Apr 20 04:05:13 PM PDT 24
Peak memory	215064 kb
Host	smart-11a907cf-63d6-4cbf-a93c-f42a27df12c4
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068627204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.1068627204
Directory	/workspace/0.keymgr_stress_all/latest

Test location	/workspace/coverage/default/10.keymgr_stress_all.2126029888
Short name	T211
Test name
Test status
Simulation time	3741873252 ps
CPU time	120.03 seconds
Started	Apr 20 04:05:52 PM PDT 24
Finished	Apr 20 04:07:53 PM PDT 24
Peak memory	216524 kb
Host	smart-ddcddad2-ecc3-478a-b189-0d22603d02a6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126029888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.2126029888
Directory	/workspace/10.keymgr_stress_all/latest

Test location	/workspace/coverage/default/13.keymgr_cfg_regwen.395342807
Short name	T122
Test name
Test status
Simulation time	203174949 ps
CPU time	3.77 seconds
Started	Apr 20 04:06:08 PM PDT 24
Finished	Apr 20 04:06:12 PM PDT 24
Peak memory	214460 kb
Host	smart-5d68ddb3-e28f-46e1-8557-92637dba963d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=395342807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.395342807
Directory	/workspace/13.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/26.keymgr_kmac_rsp_err.1450838625
Short name	T84
Test name
Test status
Simulation time	149037480 ps
CPU time	7.11 seconds
Started	Apr 20 04:07:31 PM PDT 24
Finished	Apr 20 04:07:39 PM PDT 24
Peak memory	222384 kb
Host	smart-0e05a07e-1401-46fa-9466-03d465251cda
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1450838625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.1450838625
Directory	/workspace/26.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/40.keymgr_stress_all.3975086499
Short name	T44
Test name
Test status
Simulation time	3643859715 ps
CPU time	35.65 seconds
Started	Apr 20 04:08:50 PM PDT 24
Finished	Apr 20 04:09:26 PM PDT 24
Peak memory	215368 kb
Host	smart-35a7cfe5-0f8b-4b64-88ef-87844536158e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975086499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.3975086499
Directory	/workspace/40.keymgr_stress_all/latest

Test location	/workspace/coverage/default/49.keymgr_cfg_regwen.1163799928
Short name	T373
Test name
Test status
Simulation time	994275161 ps
CPU time	8.71 seconds
Started	Apr 20 04:09:31 PM PDT 24
Finished	Apr 20 04:09:40 PM PDT 24
Peak memory	215044 kb
Host	smart-714b4622-32a5-45c7-a834-f4009e87736b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1163799928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.1163799928
Directory	/workspace/49.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/18.keymgr_kmac_rsp_err.3502009051
Short name	T95
Test name
Test status
Simulation time	214270049 ps
CPU time	5.49 seconds
Started	Apr 20 04:06:44 PM PDT 24
Finished	Apr 20 04:06:50 PM PDT 24
Peak memory	210820 kb
Host	smart-c709e06f-4596-4376-bced-93908f55955a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3502009051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.3502009051
Directory	/workspace/18.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.3618246586
Short name	T149
Test name
Test status
Simulation time	182093262 ps
CPU time	7.23 seconds
Started	Apr 20 04:10:03 PM PDT 24
Finished	Apr 20 04:10:11 PM PDT 24
Peak memory	208808 kb
Host	smart-115083b5-78a7-4f60-8e23-95bcd00215e4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618246586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er r.3618246586
Directory	/workspace/11.keymgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.1665103428
Short name	T153
Test name
Test status
Simulation time	406299589 ps
CPU time	13.4 seconds
Started	Apr 20 04:10:10 PM PDT 24
Finished	Apr 20 04:10:25 PM PDT 24
Peak memory	213908 kb
Host	smart-e9a708cd-91e0-4f49-bce8-968c0f746961
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665103428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er r.1665103428
Directory	/workspace/13.keymgr_tl_intg_err/latest

Test location	/workspace/coverage/default/12.keymgr_stress_all.440987823
Short name	T289
Test name
Test status
Simulation time	9753514282 ps
CPU time	69.81 seconds
Started	Apr 20 04:06:10 PM PDT 24
Finished	Apr 20 04:07:20 PM PDT 24
Peak memory	217100 kb
Host	smart-2ed1dd0e-525e-473f-951c-682b25f9fa93
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440987823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.440987823
Directory	/workspace/12.keymgr_stress_all/latest

Test location	/workspace/coverage/default/15.keymgr_cfg_regwen.546617280
Short name	T308
Test name
Test status
Simulation time	257869953 ps
CPU time	4.25 seconds
Started	Apr 20 04:06:20 PM PDT 24
Finished	Apr 20 04:06:24 PM PDT 24
Peak memory	215132 kb
Host	smart-0ab8a829-b2e3-45fb-8689-cbaee50af7f5
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=546617280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.546617280
Directory	/workspace/15.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/25.keymgr_stress_all.3485408035
Short name	T273
Test name
Test status
Simulation time	886863619 ps
CPU time	37.82 seconds
Started	Apr 20 04:07:30 PM PDT 24
Finished	Apr 20 04:08:08 PM PDT 24
Peak memory	215064 kb
Host	smart-1bb55c61-6ad1-48de-85de-bc84eda469bc
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485408035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.3485408035
Directory	/workspace/25.keymgr_stress_all/latest

Test location	/workspace/coverage/default/33.keymgr_cfg_regwen.2599368989
Short name	T265
Test name
Test status
Simulation time	537197599 ps
CPU time	4.55 seconds
Started	Apr 20 04:08:12 PM PDT 24
Finished	Apr 20 04:08:17 PM PDT 24
Peak memory	215608 kb
Host	smart-abc21bea-93b5-4d0d-8179-2b262aafd2eb
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2599368989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.2599368989
Directory	/workspace/33.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/35.keymgr_kmac_rsp_err.4033265821
Short name	T323
Test name
Test status
Simulation time	150401285 ps
CPU time	3.94 seconds
Started	Apr 20 04:08:22 PM PDT 24
Finished	Apr 20 04:08:26 PM PDT 24
Peak memory	211612 kb
Host	smart-9d6c4fee-8269-4669-9067-aa46c03cdd28
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4033265821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.4033265821
Directory	/workspace/35.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/36.keymgr_sideload_protect.3350757476
Short name	T36
Test name
Test status
Simulation time	45392981 ps
CPU time	2.34 seconds
Started	Apr 20 04:08:30 PM PDT 24
Finished	Apr 20 04:08:32 PM PDT 24
Peak memory	208836 kb
Host	smart-6d3eecf3-f39b-413f-b5e7-7e51801ef034
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3350757476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.3350757476
Directory	/workspace/36.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/43.keymgr_sideload_aes.2046037141
Short name	T335
Test name
Test status
Simulation time	139135962 ps
CPU time	2.67 seconds
Started	Apr 20 04:08:59 PM PDT 24
Finished	Apr 20 04:09:02 PM PDT 24
Peak memory	207216 kb
Host	smart-f02a14e5-4f4e-43ba-9ad5-1b61f94cbff4
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046037141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.2046037141
Directory	/workspace/43.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/12.keymgr_sync_async_fault_cross.1167699802
Short name	T157
Test name
Test status
Simulation time	196267392 ps
CPU time	3.18 seconds
Started	Apr 20 04:06:06 PM PDT 24
Finished	Apr 20 04:06:10 PM PDT 24
Peak memory	210180 kb
Host	smart-d774be31-47ab-4986-92db-8bfbb8490b58
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1167699802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.1167699802
Directory	/workspace/12.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/33.keymgr_sync_async_fault_cross.1571800069
Short name	T54
Test name
Test status
Simulation time	554349907 ps
CPU time	2.35 seconds
Started	Apr 20 04:08:13 PM PDT 24
Finished	Apr 20 04:08:16 PM PDT 24
Peak memory	210348 kb
Host	smart-26f990b6-ec1e-4a0a-b795-d6c93582c789
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1571800069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.1571800069
Directory	/workspace/33.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/0.keymgr_custom_cm.707911357
Short name	T116
Test name
Test status
Simulation time	79966591 ps
CPU time	4.18 seconds
Started	Apr 20 04:04:21 PM PDT 24
Finished	Apr 20 04:04:26 PM PDT 24
Peak memory	218104 kb
Host	smart-176dc7e0-8e9a-4e89-b618-3bf2b715f4f2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=707911357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.707911357
Directory	/workspace/0.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/26.keymgr_custom_cm.4205949944
Short name	T114
Test name
Test status
Simulation time	33939188 ps
CPU time	2.95 seconds
Started	Apr 20 04:07:37 PM PDT 24
Finished	Apr 20 04:07:40 PM PDT 24
Peak memory	222764 kb
Host	smart-9a26533b-384d-41ac-ba3f-c35140aef61e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4205949944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.4205949944
Directory	/workspace/26.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.3242573810
Short name	T881
Test name
Test status
Simulation time	359366603 ps
CPU time	3.48 seconds
Started	Apr 20 04:06:03 PM PDT 24
Finished	Apr 20 04:06:07 PM PDT 24
Peak memory	218416 kb
Host	smart-db1d6841-2a50-49ca-abb9-960b16bad256
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242573810 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.3242573810
Directory	/workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/13.keymgr_sideload_aes.1661596048
Short name	T640
Test name
Test status
Simulation time	448191146 ps
CPU time	2.72 seconds
Started	Apr 20 04:06:09 PM PDT 24
Finished	Apr 20 04:06:12 PM PDT 24
Peak memory	208536 kb
Host	smart-9cd109a7-0c6a-4d57-9e80-cd9ce527a68e
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661596048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.1661596048
Directory	/workspace/13.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/15.keymgr_stress_all.214299376
Short name	T1036
Test name
Test status
Simulation time	4747529502 ps
CPU time	50.03 seconds
Started	Apr 20 04:06:28 PM PDT 24
Finished	Apr 20 04:07:19 PM PDT 24
Peak memory	215832 kb
Host	smart-c246b958-de05-48ae-989f-fcd8611c1241
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214299376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.214299376
Directory	/workspace/15.keymgr_stress_all/latest

Test location	/workspace/coverage/default/16.keymgr_sw_invalid_input.2883958722
Short name	T182
Test name
Test status
Simulation time	8181008452 ps
CPU time	14.55 seconds
Started	Apr 20 04:06:29 PM PDT 24
Finished	Apr 20 04:06:44 PM PDT 24
Peak memory	209228 kb
Host	smart-4a2c9465-31ca-49b1-a8d7-b9108c3cc564
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2883958722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.2883958722
Directory	/workspace/16.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/17.keymgr_hwsw_invalid_input.2580366766
Short name	T88
Test name
Test status
Simulation time	815140375 ps
CPU time	5.53 seconds
Started	Apr 20 04:06:38 PM PDT 24
Finished	Apr 20 04:06:44 PM PDT 24
Peak memory	220496 kb
Host	smart-64578228-cf9a-4871-858f-b9b21e08a5d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2580366766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.2580366766
Directory	/workspace/17.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/2.keymgr_stress_all.697145423
Short name	T315
Test name
Test status
Simulation time	1983882742 ps
CPU time	53.25 seconds
Started	Apr 20 04:04:41 PM PDT 24
Finished	Apr 20 04:05:35 PM PDT 24
Peak memory	215308 kb
Host	smart-50c37000-e56c-4bd7-9fd9-dd333dda1a15
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697145423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.697145423
Directory	/workspace/2.keymgr_stress_all/latest

Test location	/workspace/coverage/default/30.keymgr_kmac_rsp_err.3588912005
Short name	T16
Test name
Test status
Simulation time	138770399 ps
CPU time	3.22 seconds
Started	Apr 20 04:07:59 PM PDT 24
Finished	Apr 20 04:08:03 PM PDT 24
Peak memory	210264 kb
Host	smart-85c2b62f-54cf-44e3-b5fb-98ba5d6f548a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3588912005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.3588912005
Directory	/workspace/30.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/32.keymgr_sideload_otbn.382315148
Short name	T301
Test name
Test status
Simulation time	258009493 ps
CPU time	5.08 seconds
Started	Apr 20 04:08:05 PM PDT 24
Finished	Apr 20 04:08:10 PM PDT 24
Peak memory	208888 kb
Host	smart-b2800e9b-2bd3-4b79-b53a-59fcdb2fd2fe
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382315148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.382315148
Directory	/workspace/32.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/43.keymgr_lc_disable.2789812774
Short name	T64
Test name
Test status
Simulation time	6277094130 ps
CPU time	35.86 seconds
Started	Apr 20 04:09:04 PM PDT 24
Finished	Apr 20 04:09:40 PM PDT 24
Peak memory	214456 kb
Host	smart-487825bc-76c9-4f99-919b-60ccb96548c6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2789812774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.2789812774
Directory	/workspace/43.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/49.keymgr_hwsw_invalid_input.255931715
Short name	T1058
Test name
Test status
Simulation time	332150471 ps
CPU time	9.61 seconds
Started	Apr 20 04:09:33 PM PDT 24
Finished	Apr 20 04:09:43 PM PDT 24
Peak memory	208296 kb
Host	smart-479fbc58-fed8-4a52-b68b-84ec552fbe5e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=255931715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.255931715
Directory	/workspace/49.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.4054377373
Short name	T154
Test name
Test status
Simulation time	669272918 ps
CPU time	9.95 seconds
Started	Apr 20 04:10:00 PM PDT 24
Finished	Apr 20 04:10:10 PM PDT 24
Peak memory	209352 kb
Host	smart-420c57e1-5e8b-4ddc-896a-1ca4e086d007
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054377373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er r.4054377373
Directory	/workspace/10.keymgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.3993236426
Short name	T151
Test name
Test status
Simulation time	204980979 ps
CPU time	4.41 seconds
Started	Apr 20 04:10:17 PM PDT 24
Finished	Apr 20 04:10:22 PM PDT 24
Peak memory	209280 kb
Host	smart-f8340d1e-3f2e-472a-b504-2da05cd6b0f9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993236426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er r.3993236426
Directory	/workspace/14.keymgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.545623025
Short name	T152
Test name
Test status
Simulation time	659756599 ps
CPU time	9.08 seconds
Started	Apr 20 04:10:12 PM PDT 24
Finished	Apr 20 04:10:22 PM PDT 24
Peak memory	209320 kb
Host	smart-04463c86-43ef-4889-9da1-1e533eb65723
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545623025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_err .545623025
Directory	/workspace/18.keymgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.1973973897
Short name	T158
Test name
Test status
Simulation time	66545903 ps
CPU time	3.84 seconds
Started	Apr 20 04:09:59 PM PDT 24
Finished	Apr 20 04:10:03 PM PDT 24
Peak memory	213856 kb
Host	smart-4c8b95a6-0c69-491a-9fa6-1df16a809648
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973973897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err .1973973897
Directory	/workspace/8.keymgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.668990128
Short name	T150
Test name
Test status
Simulation time	4873841528 ps
CPU time	31.54 seconds
Started	Apr 20 04:09:57 PM PDT 24
Finished	Apr 20 04:10:29 PM PDT 24
Peak memory	222088 kb
Host	smart-6720975b-00be-470b-92dc-712618e3a79e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668990128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err. 668990128
Directory	/workspace/9.keymgr_tl_intg_err/latest

Test location	/workspace/coverage/default/2.keymgr_sync_async_fault_cross.3236719143
Short name	T156
Test name
Test status
Simulation time	262979787 ps
CPU time	6.24 seconds
Started	Apr 20 04:04:43 PM PDT 24
Finished	Apr 20 04:04:49 PM PDT 24
Peak memory	210324 kb
Host	smart-4b5e8f80-1f68-4937-846b-4a2de6ba8f89
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3236719143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.3236719143
Directory	/workspace/2.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/0.keymgr_kmac_rsp_err.703950928
Short name	T292
Test name
Test status
Simulation time	211086390 ps
CPU time	4.77 seconds
Started	Apr 20 04:04:20 PM PDT 24
Finished	Apr 20 04:04:25 PM PDT 24
Peak memory	210800 kb
Host	smart-0a5ee95d-03ec-42b0-8a85-a4fa27bd3921
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=703950928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.703950928
Directory	/workspace/0.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/1.keymgr_sideload_otbn.3222613099
Short name	T376
Test name
Test status
Simulation time	201430696 ps
CPU time	5.89 seconds
Started	Apr 20 04:04:26 PM PDT 24
Finished	Apr 20 04:04:32 PM PDT 24
Peak memory	208540 kb
Host	smart-42ce5038-e517-448a-964b-a68e84130196
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222613099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.3222613099
Directory	/workspace/1.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/11.keymgr_stress_all.566479842
Short name	T216
Test name
Test status
Simulation time	2900804893 ps
CPU time	91.81 seconds
Started	Apr 20 04:05:57 PM PDT 24
Finished	Apr 20 04:07:30 PM PDT 24
Peak memory	216520 kb
Host	smart-2a2a82c1-b2a2-4236-8423-9fd6e8e5f74d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566479842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.566479842
Directory	/workspace/11.keymgr_stress_all/latest

Test location	/workspace/coverage/default/12.keymgr_kmac_rsp_err.407321115
Short name	T337
Test name
Test status
Simulation time	872356022 ps
CPU time	7.68 seconds
Started	Apr 20 04:06:06 PM PDT 24
Finished	Apr 20 04:06:14 PM PDT 24
Peak memory	222476 kb
Host	smart-968f726e-6d0a-4881-9ebf-a1c1786c2edb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=407321115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.407321115
Directory	/workspace/12.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/15.keymgr_kmac_rsp_err.3457436940
Short name	T960
Test name
Test status
Simulation time	139536386 ps
CPU time	3.01 seconds
Started	Apr 20 04:06:24 PM PDT 24
Finished	Apr 20 04:06:27 PM PDT 24
Peak memory	214340 kb
Host	smart-c27f65fd-0655-4d53-8b74-1c9815999f25
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3457436940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.3457436940
Directory	/workspace/15.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/15.keymgr_sideload_aes.3836271785
Short name	T320
Test name
Test status
Simulation time	261156389 ps
CPU time	3.21 seconds
Started	Apr 20 04:06:20 PM PDT 24
Finished	Apr 20 04:06:24 PM PDT 24
Peak memory	206808 kb
Host	smart-46031528-3207-4cd7-a7a2-74410d637b0b
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836271785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.3836271785
Directory	/workspace/15.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/16.keymgr_cfg_regwen.3904033173
Short name	T414
Test name
Test status
Simulation time	5794408623 ps
CPU time	80.05 seconds
Started	Apr 20 04:06:31 PM PDT 24
Finished	Apr 20 04:07:52 PM PDT 24
Peak memory	216008 kb
Host	smart-011cbf44-d205-4e36-a3e5-c1c9483c47d8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3904033173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.3904033173
Directory	/workspace/16.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/17.keymgr_cfg_regwen.1336669671
Short name	T416
Test name
Test status
Simulation time	70856022 ps
CPU time	3.03 seconds
Started	Apr 20 04:06:37 PM PDT 24
Finished	Apr 20 04:06:40 PM PDT 24
Peak memory	215056 kb
Host	smart-444a265b-0203-4061-b8cd-2f806e200158
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1336669671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.1336669671
Directory	/workspace/17.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/19.keymgr_cfg_regwen.1296691780
Short name	T418
Test name
Test status
Simulation time	47932171 ps
CPU time	3.3 seconds
Started	Apr 20 04:06:46 PM PDT 24
Finished	Apr 20 04:06:49 PM PDT 24
Peak memory	214264 kb
Host	smart-1c28ebac-b124-41d9-b151-861a16a49b46
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1296691780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.1296691780
Directory	/workspace/19.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/2.keymgr_kmac_rsp_err.4157015914
Short name	T326
Test name
Test status
Simulation time	612714731 ps
CPU time	18.5 seconds
Started	Apr 20 04:04:43 PM PDT 24
Finished	Apr 20 04:05:02 PM PDT 24
Peak memory	216108 kb
Host	smart-327833af-2fd3-4747-94fa-335ea3741344
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4157015914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.4157015914
Directory	/workspace/2.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/2.keymgr_lc_disable.1060618036
Short name	T213
Test name
Test status
Simulation time	1676185302 ps
CPU time	4.22 seconds
Started	Apr 20 04:04:46 PM PDT 24
Finished	Apr 20 04:04:50 PM PDT 24
Peak memory	219844 kb
Host	smart-978b3a31-78e8-4a09-bcb0-08b2c47e6a18
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1060618036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.1060618036
Directory	/workspace/2.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.2590437994
Short name	T217
Test name
Test status
Simulation time	702391330 ps
CPU time	9.99 seconds
Started	Apr 20 04:06:59 PM PDT 24
Finished	Apr 20 04:07:09 PM PDT 24
Peak memory	222620 kb
Host	smart-aee9faa0-a2c7-4fd1-b1fe-26f70f354eeb
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590437994 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.2590437994
Directory	/workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/27.keymgr_hwsw_invalid_input.968116732
Short name	T283
Test name
Test status
Simulation time	1562224589 ps
CPU time	8.05 seconds
Started	Apr 20 04:07:36 PM PDT 24
Finished	Apr 20 04:07:44 PM PDT 24
Peak memory	214280 kb
Host	smart-ff7ae032-d4f9-4b36-b820-4dc6749b2855
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=968116732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.968116732
Directory	/workspace/27.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/27.keymgr_kmac_rsp_err.1940920226
Short name	T279
Test name
Test status
Simulation time	310039944 ps
CPU time	10.27 seconds
Started	Apr 20 04:07:37 PM PDT 24
Finished	Apr 20 04:07:48 PM PDT 24
Peak memory	215168 kb
Host	smart-3b0397ca-606b-42b7-a584-931384674aea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1940920226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.1940920226
Directory	/workspace/27.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/28.keymgr_stress_all.3953711197
Short name	T70
Test name
Test status
Simulation time	1473456075 ps
CPU time	14.63 seconds
Started	Apr 20 04:07:42 PM PDT 24
Finished	Apr 20 04:07:57 PM PDT 24
Peak memory	215788 kb
Host	smart-b74210c5-c16e-4cdf-9821-dffdcfcc23fc
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953711197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.3953711197
Directory	/workspace/28.keymgr_stress_all/latest

Test location	/workspace/coverage/default/3.keymgr_custom_cm.1259742660
Short name	T209
Test name
Test status
Simulation time	97827204 ps
CPU time	4.5 seconds
Started	Apr 20 04:04:56 PM PDT 24
Finished	Apr 20 04:05:01 PM PDT 24
Peak memory	209932 kb
Host	smart-154c5f11-f4d8-474f-8b5b-16c46efab358
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1259742660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.1259742660
Directory	/workspace/3.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/30.keymgr_stress_all.3753702609
Short name	T62
Test name
Test status
Simulation time	79505144 ps
CPU time	3.64 seconds
Started	Apr 20 04:07:58 PM PDT 24
Finished	Apr 20 04:08:02 PM PDT 24
Peak memory	220260 kb
Host	smart-24cd85bb-793f-43cb-998d-2d52f3c4032b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753702609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.3753702609
Directory	/workspace/30.keymgr_stress_all/latest

Test location	/workspace/coverage/default/32.keymgr_cfg_regwen.2875882952
Short name	T222
Test name
Test status
Simulation time	184611286 ps
CPU time	2.32 seconds
Started	Apr 20 04:08:05 PM PDT 24
Finished	Apr 20 04:08:07 PM PDT 24
Peak memory	214232 kb
Host	smart-d16a0dac-e4a7-4576-a925-408672c3073b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2875882952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.2875882952
Directory	/workspace/32.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/32.keymgr_hwsw_invalid_input.1760253817
Short name	T382
Test name
Test status
Simulation time	100672049 ps
CPU time	4.19 seconds
Started	Apr 20 04:08:05 PM PDT 24
Finished	Apr 20 04:08:10 PM PDT 24
Peak memory	209200 kb
Host	smart-9852c9b7-6b70-44b0-86af-1e10f50a5c3f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1760253817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.1760253817
Directory	/workspace/32.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/37.keymgr_cfg_regwen.3101061357
Short name	T297
Test name
Test status
Simulation time	266393580 ps
CPU time	7.78 seconds
Started	Apr 20 04:08:33 PM PDT 24
Finished	Apr 20 04:08:41 PM PDT 24
Peak memory	215212 kb
Host	smart-0833389a-2b41-49c0-9d51-393322c19d73
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3101061357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.3101061357
Directory	/workspace/37.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.2671437020
Short name	T218
Test name
Test status
Simulation time	456666229 ps
CPU time	11.88 seconds
Started	Apr 20 04:09:06 PM PDT 24
Finished	Apr 20 04:09:18 PM PDT 24
Peak memory	223316 kb
Host	smart-d92dea7b-b2d3-4381-887f-346757382f02
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671437020 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.2671437020
Directory	/workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/44.keymgr_lc_disable.3562548303
Short name	T365
Test name
Test status
Simulation time	70602749 ps
CPU time	3.52 seconds
Started	Apr 20 04:09:08 PM PDT 24
Finished	Apr 20 04:09:12 PM PDT 24
Peak memory	219984 kb
Host	smart-633f229d-7eb4-40ff-a600-56e76bc093a4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3562548303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.3562548303
Directory	/workspace/44.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/45.keymgr_hwsw_invalid_input.4008569618
Short name	T92
Test name
Test status
Simulation time	39961148 ps
CPU time	2.95 seconds
Started	Apr 20 04:09:19 PM PDT 24
Finished	Apr 20 04:09:23 PM PDT 24
Peak memory	208924 kb
Host	smart-9caa0a6a-11f3-4ed6-8a9f-05cbe96e32fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4008569618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.4008569618
Directory	/workspace/45.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/47.keymgr_random.1017360042
Short name	T369
Test name
Test status
Simulation time	1494294486 ps
CPU time	5.81 seconds
Started	Apr 20 04:09:25 PM PDT 24
Finished	Apr 20 04:09:32 PM PDT 24
Peak memory	207420 kb
Host	smart-7a8d783a-0306-4185-895c-c3b68415b6f4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1017360042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.1017360042
Directory	/workspace/47.keymgr_random/latest

Test location	/workspace/coverage/default/0.keymgr_sec_cm.233557002
Short name	T13
Test name
Test status
Simulation time	2750160246 ps
CPU time	43.45 seconds
Started	Apr 20 04:04:25 PM PDT 24
Finished	Apr 20 04:05:09 PM PDT 24
Peak memory	236204 kb
Host	smart-b1bee64c-95c5-4b2f-a0f1-993928324455
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233557002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.233557002
Directory	/workspace/0.keymgr_sec_cm/latest

Test location	/workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.3367781770
Short name	T475
Test name
Test status
Simulation time	840105457 ps
CPU time	15.34 seconds
Started	Apr 20 04:09:34 PM PDT 24
Finished	Apr 20 04:09:50 PM PDT 24
Peak memory	205508 kb
Host	smart-5baf958d-142f-4fee-a96d-c375e06d32e2
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367781770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.3 367781770
Directory	/workspace/0.keymgr_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.3494894100
Short name	T521
Test name
Test status
Simulation time	49161109 ps
CPU time	1.31 seconds
Started	Apr 20 04:09:34 PM PDT 24
Finished	Apr 20 04:09:36 PM PDT 24
Peak memory	205568 kb
Host	smart-31e7b006-e19b-4824-bae0-2c01f8ea17d1
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494894100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.3 494894100
Directory	/workspace/0.keymgr_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.4182362328
Short name	T439
Test name
Test status
Simulation time	36904277 ps
CPU time	1.04 seconds
Started	Apr 20 04:09:42 PM PDT 24
Finished	Apr 20 04:09:43 PM PDT 24
Peak memory	205704 kb
Host	smart-0c77666a-5daf-4573-a30f-c1db302ee74c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182362328 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.4182362328
Directory	/workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.keymgr_csr_rw.4204247146
Short name	T485
Test name
Test status
Simulation time	19078896 ps
CPU time	1.23 seconds
Started	Apr 20 04:09:33 PM PDT 24
Finished	Apr 20 04:09:35 PM PDT 24
Peak memory	205560 kb
Host	smart-a9b14078-8920-43a0-a0c8-7b5776f83b16
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204247146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.4204247146
Directory	/workspace/0.keymgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.keymgr_intr_test.3153994203
Short name	T504
Test name
Test status
Simulation time	11520390 ps
CPU time	0.79 seconds
Started	Apr 20 04:09:33 PM PDT 24
Finished	Apr 20 04:09:35 PM PDT 24
Peak memory	205512 kb
Host	smart-33c71fbd-5e51-44cd-a62c-f6707a453d36
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153994203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.3153994203
Directory	/workspace/0.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.3948964208
Short name	T530
Test name
Test status
Simulation time	47332034 ps
CPU time	2.35 seconds
Started	Apr 20 04:09:42 PM PDT 24
Finished	Apr 20 04:09:44 PM PDT 24
Peak memory	205692 kb
Host	smart-73ec6b29-b6b7-4b90-bc32-79c847a4e0cd
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948964208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa me_csr_outstanding.3948964208
Directory	/workspace/0.keymgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.865756293
Short name	T518
Test name
Test status
Simulation time	1456704589 ps
CPU time	9.34 seconds
Started	Apr 20 04:09:34 PM PDT 24
Finished	Apr 20 04:09:44 PM PDT 24
Peak memory	214108 kb
Host	smart-81d22571-9e86-4151-a3c0-313d654866d2
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865756293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow _reg_errors.865756293
Directory	/workspace/0.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.2260395108
Short name	T145
Test name
Test status
Simulation time	197599409 ps
CPU time	5.12 seconds
Started	Apr 20 04:09:33 PM PDT 24
Finished	Apr 20 04:09:39 PM PDT 24
Peak memory	214128 kb
Host	smart-202a903d-d737-4a2a-be90-2b63360644d3
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260395108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0. keymgr_shadow_reg_errors_with_csr_rw.2260395108
Directory	/workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.keymgr_tl_errors.1920240219
Short name	T120
Test name
Test status
Simulation time	448411384 ps
CPU time	3.17 seconds
Started	Apr 20 04:09:33 PM PDT 24
Finished	Apr 20 04:09:37 PM PDT 24
Peak memory	222056 kb
Host	smart-5a97be7b-00c2-416f-9f92-253d0d80c77a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920240219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.1920240219
Directory	/workspace/0.keymgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.1425501186
Short name	T133
Test name
Test status
Simulation time	254357175 ps
CPU time	8.02 seconds
Started	Apr 20 04:09:32 PM PDT 24
Finished	Apr 20 04:09:41 PM PDT 24
Peak memory	217756 kb
Host	smart-6c2f116b-8b88-4ae8-9076-28bd86e37b8d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425501186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err .1425501186
Directory	/workspace/0.keymgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.1041855857
Short name	T433
Test name
Test status
Simulation time	1884670260 ps
CPU time	10.43 seconds
Started	Apr 20 04:09:41 PM PDT 24
Finished	Apr 20 04:09:52 PM PDT 24
Peak memory	205436 kb
Host	smart-cfb469c7-d2e2-40c2-9b56-8783b918c011
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041855857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.1 041855857
Directory	/workspace/1.keymgr_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.335111228
Short name	T540
Test name
Test status
Simulation time	884439309 ps
CPU time	15.74 seconds
Started	Apr 20 04:09:37 PM PDT 24
Finished	Apr 20 04:09:53 PM PDT 24
Peak memory	205572 kb
Host	smart-9370aa13-d591-4581-91ab-e928a7f6bdd4
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335111228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.335111228
Directory	/workspace/1.keymgr_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.1439058235
Short name	T473
Test name
Test status
Simulation time	60822867 ps
CPU time	1.09 seconds
Started	Apr 20 04:09:43 PM PDT 24
Finished	Apr 20 04:09:44 PM PDT 24
Peak memory	205584 kb
Host	smart-21d74072-7014-4fd8-82ce-40abd946af4a
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439058235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.1 439058235
Directory	/workspace/1.keymgr_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.586760158
Short name	T525
Test name
Test status
Simulation time	48519184 ps
CPU time	1.37 seconds
Started	Apr 20 04:09:41 PM PDT 24
Finished	Apr 20 04:09:42 PM PDT 24
Peak memory	214004 kb
Host	smart-946154d7-4527-4ce0-8f0d-9c4b330bf21f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586760158 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.586760158
Directory	/workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.keymgr_csr_rw.3230307002
Short name	T176
Test name
Test status
Simulation time	17822628 ps
CPU time	1.01 seconds
Started	Apr 20 04:09:37 PM PDT 24
Finished	Apr 20 04:09:38 PM PDT 24
Peak memory	205480 kb
Host	smart-5e91f6da-234f-4d47-b48f-2421ed167bb8
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230307002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.3230307002
Directory	/workspace/1.keymgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.keymgr_intr_test.2956537895
Short name	T181
Test name
Test status
Simulation time	26711094 ps
CPU time	0.73 seconds
Started	Apr 20 04:09:36 PM PDT 24
Finished	Apr 20 04:09:37 PM PDT 24
Peak memory	205476 kb
Host	smart-92639ee3-035c-41b8-89a5-77e2b3216561
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956537895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.2956537895
Directory	/workspace/1.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.753202691
Short name	T538
Test name
Test status
Simulation time	225510838 ps
CPU time	10.91 seconds
Started	Apr 20 04:09:35 PM PDT 24
Finished	Apr 20 04:09:47 PM PDT 24
Peak memory	213980 kb
Host	smart-5c057626-5a21-4ba6-bc3d-2cc30402fe00
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753202691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST _SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.k eymgr_shadow_reg_errors_with_csr_rw.753202691
Directory	/workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.keymgr_tl_errors.833553882
Short name	T465
Test name
Test status
Simulation time	26865456 ps
CPU time	1.72 seconds
Started	Apr 20 04:09:35 PM PDT 24
Finished	Apr 20 04:09:38 PM PDT 24
Peak memory	217092 kb
Host	smart-a36a84d1-1cfe-4441-97ad-43a79d92351d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833553882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.833553882
Directory	/workspace/1.keymgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.2454196272
Short name	T163
Test name
Test status
Simulation time	294190700 ps
CPU time	3.74 seconds
Started	Apr 20 04:09:38 PM PDT 24
Finished	Apr 20 04:09:42 PM PDT 24
Peak memory	213932 kb
Host	smart-641db895-8feb-40cc-a021-a2a1aecfa7ab
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454196272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err .2454196272
Directory	/workspace/1.keymgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.183694105
Short name	T445
Test name
Test status
Simulation time	28128741 ps
CPU time	1.74 seconds
Started	Apr 20 04:09:59 PM PDT 24
Finished	Apr 20 04:10:02 PM PDT 24
Peak memory	213964 kb
Host	smart-b8f3a0b1-9951-4c35-b3bb-66a130c570f5
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183694105 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.183694105
Directory	/workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.keymgr_csr_rw.2647470612
Short name	T450
Test name
Test status
Simulation time	64224036 ps
CPU time	1.22 seconds
Started	Apr 20 04:09:59 PM PDT 24
Finished	Apr 20 04:10:01 PM PDT 24
Peak memory	205560 kb
Host	smart-d539ed8c-7feb-4084-901c-29b70de4a883
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647470612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.2647470612
Directory	/workspace/10.keymgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.keymgr_intr_test.2633360994
Short name	T430
Test name
Test status
Simulation time	8803408 ps
CPU time	0.78 seconds
Started	Apr 20 04:09:59 PM PDT 24
Finished	Apr 20 04:10:01 PM PDT 24
Peak memory	205412 kb
Host	smart-294cf389-cbf3-4f89-aed4-7e65d295e715
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633360994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.2633360994
Directory	/workspace/10.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.825330191
Short name	T544
Test name
Test status
Simulation time	44418519 ps
CPU time	1.62 seconds
Started	Apr 20 04:10:00 PM PDT 24
Finished	Apr 20 04:10:03 PM PDT 24
Peak memory	205704 kb
Host	smart-c133ee57-16f5-4add-ac31-4e6760233841
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825330191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_sa me_csr_outstanding.825330191
Directory	/workspace/10.keymgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.371947008
Short name	T462
Test name
Test status
Simulation time	184374986 ps
CPU time	2.02 seconds
Started	Apr 20 04:09:59 PM PDT 24
Finished	Apr 20 04:10:01 PM PDT 24
Peak memory	222184 kb
Host	smart-a3fbf2fe-3490-4de1-97d2-0b9483cdb239
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371947008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shado w_reg_errors.371947008
Directory	/workspace/10.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.keymgr_tl_errors.3752968634
Short name	T488
Test name
Test status
Simulation time	29918337 ps
CPU time	2.2 seconds
Started	Apr 20 04:10:00 PM PDT 24
Finished	Apr 20 04:10:02 PM PDT 24
Peak memory	213988 kb
Host	smart-02b91192-69c0-4957-aecd-d6adeecf6430
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752968634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.3752968634
Directory	/workspace/10.keymgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.460492437
Short name	T541
Test name
Test status
Simulation time	32709661 ps
CPU time	1.35 seconds
Started	Apr 20 04:10:02 PM PDT 24
Finished	Apr 20 04:10:04 PM PDT 24
Peak memory	213896 kb
Host	smart-782e2a9a-d15c-4355-9921-12cab5e648f7
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460492437 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.460492437
Directory	/workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.keymgr_csr_rw.2915014351
Short name	T144
Test name
Test status
Simulation time	54900594 ps
CPU time	1.21 seconds
Started	Apr 20 04:10:06 PM PDT 24
Finished	Apr 20 04:10:08 PM PDT 24
Peak memory	205548 kb
Host	smart-90dca923-7368-45a1-886c-39fcb3850400
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915014351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.2915014351
Directory	/workspace/11.keymgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.keymgr_intr_test.2247709032
Short name	T534
Test name
Test status
Simulation time	11346527 ps
CPU time	0.86 seconds
Started	Apr 20 04:10:03 PM PDT 24
Finished	Apr 20 04:10:04 PM PDT 24
Peak memory	205528 kb
Host	smart-a8a54627-0d70-45b3-a705-73655b4d87b2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247709032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.2247709032
Directory	/workspace/11.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.3103985592
Short name	T146
Test name
Test status
Simulation time	99484581 ps
CPU time	1.74 seconds
Started	Apr 20 04:10:05 PM PDT 24
Finished	Apr 20 04:10:07 PM PDT 24
Peak memory	205728 kb
Host	smart-e7f5f11e-196f-4407-982c-76c55093faea
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103985592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s ame_csr_outstanding.3103985592
Directory	/workspace/11.keymgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.1830573052
Short name	T175
Test name
Test status
Simulation time	371703332 ps
CPU time	8.24 seconds
Started	Apr 20 04:09:59 PM PDT 24
Finished	Apr 20 04:10:08 PM PDT 24
Peak memory	213904 kb
Host	smart-98f96e8d-72ae-4e7d-b31f-f6750bd9d6b5
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830573052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad ow_reg_errors.1830573052
Directory	/workspace/11.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.3932145345
Short name	T543
Test name
Test status
Simulation time	1603048293 ps
CPU time	15.19 seconds
Started	Apr 20 04:09:58 PM PDT 24
Finished	Apr 20 04:10:14 PM PDT 24
Peak memory	220228 kb
Host	smart-331b35f9-ddea-4f5f-9432-47c15e519054
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932145345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11 .keymgr_shadow_reg_errors_with_csr_rw.3932145345
Directory	/workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.keymgr_tl_errors.2176643801
Short name	T510
Test name
Test status
Simulation time	289226452 ps
CPU time	2.79 seconds
Started	Apr 20 04:10:02 PM PDT 24
Finished	Apr 20 04:10:05 PM PDT 24
Peak memory	215928 kb
Host	smart-360d64cd-b408-4868-90ae-de35db868d05
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176643801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.2176643801
Directory	/workspace/11.keymgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.2707116170
Short name	T444
Test name
Test status
Simulation time	19082591 ps
CPU time	1.63 seconds
Started	Apr 20 04:10:03 PM PDT 24
Finished	Apr 20 04:10:05 PM PDT 24
Peak memory	213976 kb
Host	smart-d7cda86d-11a3-4642-b0b1-80eb3e195dd6
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707116170 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.2707116170
Directory	/workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.keymgr_csr_rw.3148018300
Short name	T173
Test name
Test status
Simulation time	22601530 ps
CPU time	0.99 seconds
Started	Apr 20 04:10:04 PM PDT 24
Finished	Apr 20 04:10:05 PM PDT 24
Peak memory	205520 kb
Host	smart-6a117d7f-91cf-4ddb-86e8-130b448e84ee
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148018300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.3148018300
Directory	/workspace/12.keymgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.keymgr_intr_test.923786250
Short name	T468
Test name
Test status
Simulation time	9912013 ps
CPU time	0.87 seconds
Started	Apr 20 04:10:09 PM PDT 24
Finished	Apr 20 04:10:10 PM PDT 24
Peak memory	205440 kb
Host	smart-2f7d532a-7b42-4e7a-bc4c-882820dfae35
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923786250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.923786250
Directory	/workspace/12.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.1730000554
Short name	T446
Test name
Test status
Simulation time	91153959 ps
CPU time	2.14 seconds
Started	Apr 20 04:10:04 PM PDT 24
Finished	Apr 20 04:10:06 PM PDT 24
Peak memory	205572 kb
Host	smart-8e1d93d2-265c-4729-bd45-995ef36671bc
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730000554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s ame_csr_outstanding.1730000554
Directory	/workspace/12.keymgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.998415469
Short name	T434
Test name
Test status
Simulation time	100887660 ps
CPU time	2.62 seconds
Started	Apr 20 04:10:04 PM PDT 24
Finished	Apr 20 04:10:08 PM PDT 24
Peak memory	218864 kb
Host	smart-1372a1a6-3886-4a64-a2df-0c3c2aedfc30
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998415469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shado w_reg_errors.998415469
Directory	/workspace/12.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.168099797
Short name	T118
Test name
Test status
Simulation time	118146092 ps
CPU time	4.25 seconds
Started	Apr 20 04:10:07 PM PDT 24
Finished	Apr 20 04:10:12 PM PDT 24
Peak memory	214132 kb
Host	smart-9da40c2e-188a-4378-9f01-f514916d94e1
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168099797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST _SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12. keymgr_shadow_reg_errors_with_csr_rw.168099797
Directory	/workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.keymgr_tl_errors.711123184
Short name	T495
Test name
Test status
Simulation time	564372826 ps
CPU time	2.41 seconds
Started	Apr 20 04:10:01 PM PDT 24
Finished	Apr 20 04:10:05 PM PDT 24
Peak memory	213888 kb
Host	smart-767657f5-4664-4f57-8694-d2515e5dfed2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711123184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.711123184
Directory	/workspace/12.keymgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.2137397249
Short name	T164
Test name
Test status
Simulation time	21801045 ps
CPU time	1.37 seconds
Started	Apr 20 04:10:05 PM PDT 24
Finished	Apr 20 04:10:07 PM PDT 24
Peak memory	213932 kb
Host	smart-43eb4baa-4ea2-48c1-a380-6254d0f7d1c3
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137397249 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.2137397249
Directory	/workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.keymgr_intr_test.233130308
Short name	T547
Test name
Test status
Simulation time	8266615 ps
CPU time	0.7 seconds
Started	Apr 20 04:10:00 PM PDT 24
Finished	Apr 20 04:10:01 PM PDT 24
Peak memory	205488 kb
Host	smart-b9b736d8-ef17-45c1-9343-36c7dd986519
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233130308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.233130308
Directory	/workspace/13.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.525920834
Short name	T174
Test name
Test status
Simulation time	249067448 ps
CPU time	2.92 seconds
Started	Apr 20 04:10:01 PM PDT 24
Finished	Apr 20 04:10:05 PM PDT 24
Peak memory	214096 kb
Host	smart-2dade5dd-d01c-438d-8502-cb331ab8bd76
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525920834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shado w_reg_errors.525920834
Directory	/workspace/13.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3856174754
Short name	T497
Test name
Test status
Simulation time	552239405 ps
CPU time	17.53 seconds
Started	Apr 20 04:10:10 PM PDT 24
Finished	Apr 20 04:10:27 PM PDT 24
Peak memory	213980 kb
Host	smart-e89c774a-196a-4daa-9ed7-fdf086beb3da
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856174754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13 .keymgr_shadow_reg_errors_with_csr_rw.3856174754
Directory	/workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.3875317702
Short name	T459
Test name
Test status
Simulation time	126338132 ps
CPU time	1.51 seconds
Started	Apr 20 04:10:07 PM PDT 24
Finished	Apr 20 04:10:09 PM PDT 24
Peak memory	214012 kb
Host	smart-6c8ede04-f916-4270-90c3-c1941de8dbf0
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875317702 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.3875317702
Directory	/workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.keymgr_intr_test.4185691250
Short name	T457
Test name
Test status
Simulation time	28768021 ps
CPU time	0.7 seconds
Started	Apr 20 04:10:06 PM PDT 24
Finished	Apr 20 04:10:07 PM PDT 24
Peak memory	205520 kb
Host	smart-73391310-501f-4e78-a876-28f63e737363
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185691250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.4185691250
Directory	/workspace/14.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.384045521
Short name	T147
Test name
Test status
Simulation time	37337168 ps
CPU time	2.05 seconds
Started	Apr 20 04:10:08 PM PDT 24
Finished	Apr 20 04:10:11 PM PDT 24
Peak memory	205640 kb
Host	smart-8a486588-4ea6-4f85-83cb-352589f898b1
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384045521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_sa me_csr_outstanding.384045521
Directory	/workspace/14.keymgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.575962252
Short name	T436
Test name
Test status
Simulation time	520329992 ps
CPU time	3.26 seconds
Started	Apr 20 04:10:07 PM PDT 24
Finished	Apr 20 04:10:11 PM PDT 24
Peak memory	214072 kb
Host	smart-44fce034-4a4d-4af9-89f7-7a28ff93f3aa
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575962252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shado w_reg_errors.575962252
Directory	/workspace/14.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.701320701
Short name	T471
Test name
Test status
Simulation time	657460345 ps
CPU time	5.17 seconds
Started	Apr 20 04:10:05 PM PDT 24
Finished	Apr 20 04:10:10 PM PDT 24
Peak memory	214008 kb
Host	smart-da7388f0-779d-4dcb-878c-00f44aa6eb32
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701320701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST _SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14. keymgr_shadow_reg_errors_with_csr_rw.701320701
Directory	/workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.keymgr_tl_errors.2592215939
Short name	T532
Test name
Test status
Simulation time	139607791 ps
CPU time	1.62 seconds
Started	Apr 20 04:10:06 PM PDT 24
Finished	Apr 20 04:10:08 PM PDT 24
Peak memory	213904 kb
Host	smart-95972bc8-dee8-4e7d-add3-e8affa0456cb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592215939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.2592215939
Directory	/workspace/14.keymgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.4120449482
Short name	T494
Test name
Test status
Simulation time	50724629 ps
CPU time	1.29 seconds
Started	Apr 20 04:10:17 PM PDT 24
Finished	Apr 20 04:10:19 PM PDT 24
Peak memory	213924 kb
Host	smart-16f0de50-ceb5-49fb-b8b3-0dddf2554f08
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120449482 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.4120449482
Directory	/workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.keymgr_csr_rw.3411519252
Short name	T140
Test name
Test status
Simulation time	43210498 ps
CPU time	1.13 seconds
Started	Apr 20 04:10:17 PM PDT 24
Finished	Apr 20 04:10:18 PM PDT 24
Peak memory	205568 kb
Host	smart-4cff2658-fafa-43fb-9a3c-8bbc55cb7b27
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411519252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.3411519252
Directory	/workspace/15.keymgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.keymgr_intr_test.132123275
Short name	T529
Test name
Test status
Simulation time	44711320 ps
CPU time	0.81 seconds
Started	Apr 20 04:10:06 PM PDT 24
Finished	Apr 20 04:10:07 PM PDT 24
Peak memory	205416 kb
Host	smart-07ae3e27-8fa1-4d20-885c-7f6b86acb2e2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132123275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.132123275
Directory	/workspace/15.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.1704495577
Short name	T486
Test name
Test status
Simulation time	313843172 ps
CPU time	3.84 seconds
Started	Apr 20 04:10:06 PM PDT 24
Finished	Apr 20 04:10:10 PM PDT 24
Peak memory	214096 kb
Host	smart-1a9e7918-6df2-445f-a246-bf674cb1ae7a
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704495577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad ow_reg_errors.1704495577
Directory	/workspace/15.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.3409044019
Short name	T493
Test name
Test status
Simulation time	601266456 ps
CPU time	4.58 seconds
Started	Apr 20 04:10:17 PM PDT 24
Finished	Apr 20 04:10:22 PM PDT 24
Peak memory	213968 kb
Host	smart-c63086c1-dcda-4129-bede-03dba151c977
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409044019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15 .keymgr_shadow_reg_errors_with_csr_rw.3409044019
Directory	/workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.keymgr_tl_errors.2910149089
Short name	T128
Test name
Test status
Simulation time	604621861 ps
CPU time	5.39 seconds
Started	Apr 20 04:10:07 PM PDT 24
Finished	Apr 20 04:10:13 PM PDT 24
Peak memory	213504 kb
Host	smart-69f47328-08de-4380-afc5-061bc375b087
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910149089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.2910149089
Directory	/workspace/15.keymgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.986075738
Short name	T477
Test name
Test status
Simulation time	17015567 ps
CPU time	1.02 seconds
Started	Apr 20 04:10:11 PM PDT 24
Finished	Apr 20 04:10:13 PM PDT 24
Peak memory	205620 kb
Host	smart-5fffba83-b799-458a-a286-d22f855c87cb
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986075738 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.986075738
Directory	/workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.keymgr_csr_rw.2146139619
Short name	T143
Test name
Test status
Simulation time	58474801 ps
CPU time	0.99 seconds
Started	Apr 20 04:10:09 PM PDT 24
Finished	Apr 20 04:10:10 PM PDT 24
Peak memory	205524 kb
Host	smart-5ce54323-8e2f-4840-893e-63bf0577e439
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146139619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.2146139619
Directory	/workspace/16.keymgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.keymgr_intr_test.1997986081
Short name	T178
Test name
Test status
Simulation time	16295985 ps
CPU time	0.74 seconds
Started	Apr 20 04:10:13 PM PDT 24
Finished	Apr 20 04:10:15 PM PDT 24
Peak memory	205496 kb
Host	smart-a3c01b32-52b4-469c-93cb-77f232915c7d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997986081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.1997986081
Directory	/workspace/16.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.2048991494
Short name	T516
Test name
Test status
Simulation time	78165374 ps
CPU time	1.53 seconds
Started	Apr 20 04:10:14 PM PDT 24
Finished	Apr 20 04:10:16 PM PDT 24
Peak memory	205644 kb
Host	smart-82dede91-2a56-4395-93e0-144303ab7596
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048991494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s ame_csr_outstanding.2048991494
Directory	/workspace/16.keymgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.2526904065
Short name	T463
Test name
Test status
Simulation time	204174644 ps
CPU time	2.77 seconds
Started	Apr 20 04:10:08 PM PDT 24
Finished	Apr 20 04:10:12 PM PDT 24
Peak memory	222288 kb
Host	smart-13df119a-e7a4-40fa-9a00-0c6dfb5051ba
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526904065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad ow_reg_errors.2526904065
Directory	/workspace/16.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.keymgr_tl_errors.2326768125
Short name	T490
Test name
Test status
Simulation time	49909831 ps
CPU time	3.17 seconds
Started	Apr 20 04:10:10 PM PDT 24
Finished	Apr 20 04:10:14 PM PDT 24
Peak memory	213972 kb
Host	smart-8a2dde53-4c41-4dd8-a142-037d89a57c3c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326768125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.2326768125
Directory	/workspace/16.keymgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.793042739
Short name	T542
Test name
Test status
Simulation time	86011363 ps
CPU time	1.72 seconds
Started	Apr 20 04:10:13 PM PDT 24
Finished	Apr 20 04:10:16 PM PDT 24
Peak memory	213836 kb
Host	smart-f6bb330c-b37b-4412-8b8c-38664e838872
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793042739 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.793042739
Directory	/workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.keymgr_csr_rw.3254105521
Short name	T442
Test name
Test status
Simulation time	23866782 ps
CPU time	0.89 seconds
Started	Apr 20 04:10:18 PM PDT 24
Finished	Apr 20 04:10:19 PM PDT 24
Peak memory	205464 kb
Host	smart-70df7067-1b2a-4274-ab80-24663c8a5c4d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254105521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.3254105521
Directory	/workspace/17.keymgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.keymgr_intr_test.2048402241
Short name	T480
Test name
Test status
Simulation time	37650129 ps
CPU time	0.69 seconds
Started	Apr 20 04:10:13 PM PDT 24
Finished	Apr 20 04:10:15 PM PDT 24
Peak memory	205488 kb
Host	smart-d1355d69-de61-4d6b-b6c0-278a7af739c9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048402241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.2048402241
Directory	/workspace/17.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.994824671
Short name	T531
Test name
Test status
Simulation time	159949490 ps
CPU time	2.49 seconds
Started	Apr 20 04:10:10 PM PDT 24
Finished	Apr 20 04:10:13 PM PDT 24
Peak memory	213996 kb
Host	smart-158d639d-90d4-42e8-8d6d-23e94c12a4e6
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994824671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shado w_reg_errors.994824671
Directory	/workspace/17.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.keymgr_tl_errors.11393121
Short name	T134
Test name
Test status
Simulation time	41782501 ps
CPU time	2.88 seconds
Started	Apr 20 04:10:09 PM PDT 24
Finished	Apr 20 04:10:12 PM PDT 24
Peak memory	216884 kb
Host	smart-06c9175c-3aee-42b9-bfdb-5dc1555a57da
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11393121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.11393121
Directory	/workspace/17.keymgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.1227768402
Short name	T537
Test name
Test status
Simulation time	26930889 ps
CPU time	1.17 seconds
Started	Apr 20 04:10:13 PM PDT 24
Finished	Apr 20 04:10:14 PM PDT 24
Peak memory	205684 kb
Host	smart-2047049c-477f-4462-aef1-a944c37a8b9b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227768402 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.1227768402
Directory	/workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.keymgr_csr_rw.3658399902
Short name	T441
Test name
Test status
Simulation time	59743125 ps
CPU time	1.08 seconds
Started	Apr 20 04:10:13 PM PDT 24
Finished	Apr 20 04:10:15 PM PDT 24
Peak memory	205476 kb
Host	smart-4b2776b8-8ccf-415a-a977-53a5129a5dbf
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658399902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.3658399902
Directory	/workspace/18.keymgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.keymgr_intr_test.946742160
Short name	T428
Test name
Test status
Simulation time	10127657 ps
CPU time	0.82 seconds
Started	Apr 20 04:10:14 PM PDT 24
Finished	Apr 20 04:10:16 PM PDT 24
Peak memory	205524 kb
Host	smart-f24a6d34-f7a7-4f71-977e-ebddec79aaa4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946742160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.946742160
Directory	/workspace/18.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.3656771580
Short name	T500
Test name
Test status
Simulation time	120755574 ps
CPU time	3.63 seconds
Started	Apr 20 04:10:14 PM PDT 24
Finished	Apr 20 04:10:19 PM PDT 24
Peak memory	214092 kb
Host	smart-e5a30857-6af4-445a-8043-c14b1ec4fb46
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656771580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad ow_reg_errors.3656771580
Directory	/workspace/18.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.keymgr_tl_errors.3271719575
Short name	T129
Test name
Test status
Simulation time	62749114 ps
CPU time	1.91 seconds
Started	Apr 20 04:10:15 PM PDT 24
Finished	Apr 20 04:10:17 PM PDT 24
Peak memory	213892 kb
Host	smart-55fbfe34-8709-423e-9559-fb17503274f0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271719575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.3271719575
Directory	/workspace/18.keymgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.1051930182
Short name	T172
Test name
Test status
Simulation time	103403709 ps
CPU time	0.93 seconds
Started	Apr 20 04:10:17 PM PDT 24
Finished	Apr 20 04:10:18 PM PDT 24
Peak memory	205616 kb
Host	smart-a878e3eb-498c-45a9-bd8b-5565ec2bee05
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051930182 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.1051930182
Directory	/workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.keymgr_csr_rw.1650384352
Short name	T511
Test name
Test status
Simulation time	26104436 ps
CPU time	0.98 seconds
Started	Apr 20 04:10:22 PM PDT 24
Finished	Apr 20 04:10:23 PM PDT 24
Peak memory	205504 kb
Host	smart-c977ddd4-d559-4d73-9ab1-a0e4aef5a25d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650384352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.1650384352
Directory	/workspace/19.keymgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.keymgr_intr_test.2945358516
Short name	T458
Test name
Test status
Simulation time	74710733 ps
CPU time	0.73 seconds
Started	Apr 20 04:10:16 PM PDT 24
Finished	Apr 20 04:10:17 PM PDT 24
Peak memory	205512 kb
Host	smart-063a1bae-e029-4bda-8908-8cea79602400
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945358516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.2945358516
Directory	/workspace/19.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3853892835
Short name	T487
Test name
Test status
Simulation time	1421857088 ps
CPU time	7 seconds
Started	Apr 20 04:10:15 PM PDT 24
Finished	Apr 20 04:10:22 PM PDT 24
Peak memory	214076 kb
Host	smart-150b8d7c-71a3-44b1-abb3-b75dde0d7059
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853892835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad ow_reg_errors.3853892835
Directory	/workspace/19.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.keymgr_tl_errors.501604628
Short name	T127
Test name
Test status
Simulation time	34091672 ps
CPU time	2.26 seconds
Started	Apr 20 04:10:17 PM PDT 24
Finished	Apr 20 04:10:19 PM PDT 24
Peak memory	213996 kb
Host	smart-2faf0302-1231-45ad-9861-1c25236d217b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501604628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.501604628
Directory	/workspace/19.keymgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.2880180460
Short name	T453
Test name
Test status
Simulation time	458975581 ps
CPU time	8.41 seconds
Started	Apr 20 04:09:41 PM PDT 24
Finished	Apr 20 04:09:50 PM PDT 24
Peak memory	205612 kb
Host	smart-89d20296-caf0-436d-a569-cc3166a9041e
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880180460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.2 880180460
Directory	/workspace/2.keymgr_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.1761968462
Short name	T167
Test name
Test status
Simulation time	91448928 ps
CPU time	1.17 seconds
Started	Apr 20 04:09:38 PM PDT 24
Finished	Apr 20 04:09:39 PM PDT 24
Peak memory	205540 kb
Host	smart-fcf54fab-691f-47bd-bf92-3accfd79bbd0
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761968462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.1 761968462
Directory	/workspace/2.keymgr_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.3612175910
Short name	T437
Test name
Test status
Simulation time	23582859 ps
CPU time	1.17 seconds
Started	Apr 20 04:09:40 PM PDT 24
Finished	Apr 20 04:09:41 PM PDT 24
Peak memory	205700 kb
Host	smart-0c2e31dd-5664-4729-a63b-cdb0a577613c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612175910 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.3612175910
Directory	/workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.keymgr_csr_rw.4219251129
Short name	T464
Test name
Test status
Simulation time	75041706 ps
CPU time	1.33 seconds
Started	Apr 20 04:09:40 PM PDT 24
Finished	Apr 20 04:09:42 PM PDT 24
Peak memory	205672 kb
Host	smart-b4c2d082-a49d-41c4-9bd4-0fef298904ac
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219251129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.4219251129
Directory	/workspace/2.keymgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.keymgr_intr_test.2188867421
Short name	T141
Test name
Test status
Simulation time	87695240 ps
CPU time	0.77 seconds
Started	Apr 20 04:09:41 PM PDT 24
Finished	Apr 20 04:09:42 PM PDT 24
Peak memory	205520 kb
Host	smart-bc0643b1-5c1f-4ee8-bf59-dcb4a5ac22eb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188867421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.2188867421
Directory	/workspace/2.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.2561027644
Short name	T519
Test name
Test status
Simulation time	56015866 ps
CPU time	1.57 seconds
Started	Apr 20 04:09:41 PM PDT 24
Finished	Apr 20 04:09:43 PM PDT 24
Peak memory	205640 kb
Host	smart-21269eef-23f4-4627-909b-5ffeebd43726
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561027644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa me_csr_outstanding.2561027644
Directory	/workspace/2.keymgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.2755930117
Short name	T452
Test name
Test status
Simulation time	252517551 ps
CPU time	4.12 seconds
Started	Apr 20 04:09:40 PM PDT 24
Finished	Apr 20 04:09:44 PM PDT 24
Peak memory	214204 kb
Host	smart-f3480f51-8209-427a-841c-8566a039a390
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755930117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado w_reg_errors.2755930117
Directory	/workspace/2.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.1634230724
Short name	T451
Test name
Test status
Simulation time	776572227 ps
CPU time	9.84 seconds
Started	Apr 20 04:09:42 PM PDT 24
Finished	Apr 20 04:09:52 PM PDT 24
Peak memory	220028 kb
Host	smart-1609ed40-9367-445c-983f-aadb41e888c7
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634230724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2. keymgr_shadow_reg_errors_with_csr_rw.1634230724
Directory	/workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.keymgr_tl_errors.1255499642
Short name	T130
Test name
Test status
Simulation time	33520834 ps
CPU time	1.87 seconds
Started	Apr 20 04:09:41 PM PDT 24
Finished	Apr 20 04:09:44 PM PDT 24
Peak memory	213812 kb
Host	smart-dbe02ace-215c-41ba-a1e0-212b4668a6c2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255499642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.1255499642
Directory	/workspace/2.keymgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.3324064803
Short name	T383
Test name
Test status
Simulation time	436125231 ps
CPU time	10.42 seconds
Started	Apr 20 04:09:41 PM PDT 24
Finished	Apr 20 04:09:52 PM PDT 24
Peak memory	213872 kb
Host	smart-4f7f45a0-9eb0-4388-b0c3-5f5ed6a1d051
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324064803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err .3324064803
Directory	/workspace/2.keymgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/20.keymgr_intr_test.3966763170
Short name	T432
Test name
Test status
Simulation time	10788420 ps
CPU time	0.79 seconds
Started	Apr 20 04:10:17 PM PDT 24
Finished	Apr 20 04:10:19 PM PDT 24
Peak memory	205476 kb
Host	smart-07074431-4896-4b1c-8a0c-c5d4d85281d6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966763170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.3966763170
Directory	/workspace/20.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.keymgr_intr_test.860594601
Short name	T491
Test name
Test status
Simulation time	43149707 ps
CPU time	0.81 seconds
Started	Apr 20 04:10:16 PM PDT 24
Finished	Apr 20 04:10:18 PM PDT 24
Peak memory	205512 kb
Host	smart-a9b79593-43c3-4942-8ee2-2ddc933f9121
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860594601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.860594601
Directory	/workspace/21.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.keymgr_intr_test.3019683077
Short name	T513
Test name
Test status
Simulation time	18416939 ps
CPU time	0.83 seconds
Started	Apr 20 04:10:16 PM PDT 24
Finished	Apr 20 04:10:17 PM PDT 24
Peak memory	205488 kb
Host	smart-4fc3bae9-8c00-4e83-ac2f-a53169a5e488
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019683077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.3019683077
Directory	/workspace/22.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.keymgr_intr_test.742749863
Short name	T443
Test name
Test status
Simulation time	8656690 ps
CPU time	0.81 seconds
Started	Apr 20 04:10:16 PM PDT 24
Finished	Apr 20 04:10:17 PM PDT 24
Peak memory	205532 kb
Host	smart-d40131f3-b8fb-4481-bc8e-9c0089a67311
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742749863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.742749863
Directory	/workspace/23.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.keymgr_intr_test.927260419
Short name	T474
Test name
Test status
Simulation time	59039988 ps
CPU time	0.85 seconds
Started	Apr 20 04:10:16 PM PDT 24
Finished	Apr 20 04:10:18 PM PDT 24
Peak memory	205492 kb
Host	smart-0249ab4b-3601-4ef0-a0e9-8e6bb858eb89
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927260419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.927260419
Directory	/workspace/24.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.keymgr_intr_test.1377244881
Short name	T478
Test name
Test status
Simulation time	13014356 ps
CPU time	0.74 seconds
Started	Apr 20 04:10:16 PM PDT 24
Finished	Apr 20 04:10:17 PM PDT 24
Peak memory	205524 kb
Host	smart-08b4c1aa-69c8-4ca5-9283-e2ab773d6dfd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377244881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.1377244881
Directory	/workspace/25.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.keymgr_intr_test.2012386680
Short name	T503
Test name
Test status
Simulation time	29773978 ps
CPU time	0.69 seconds
Started	Apr 20 04:10:18 PM PDT 24
Finished	Apr 20 04:10:19 PM PDT 24
Peak memory	205516 kb
Host	smart-9000ccbe-b451-460f-94ab-25dcabdb2b0b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012386680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.2012386680
Directory	/workspace/26.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.keymgr_intr_test.937285455
Short name	T548
Test name
Test status
Simulation time	9489907 ps
CPU time	0.72 seconds
Started	Apr 20 04:10:17 PM PDT 24
Finished	Apr 20 04:10:19 PM PDT 24
Peak memory	205476 kb
Host	smart-52b55dab-e6bc-48ba-b09f-9af6269006d7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937285455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.937285455
Directory	/workspace/27.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.keymgr_intr_test.2681056238
Short name	T461
Test name
Test status
Simulation time	14244413 ps
CPU time	0.75 seconds
Started	Apr 20 04:10:17 PM PDT 24
Finished	Apr 20 04:10:18 PM PDT 24
Peak memory	205412 kb
Host	smart-b49c0fb5-0c86-4ba0-abbd-b23a8ea6ec0a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681056238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.2681056238
Directory	/workspace/28.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.keymgr_intr_test.3038744226
Short name	T506
Test name
Test status
Simulation time	42891847 ps
CPU time	0.75 seconds
Started	Apr 20 04:10:13 PM PDT 24
Finished	Apr 20 04:10:15 PM PDT 24
Peak memory	205424 kb
Host	smart-176c3e73-52a2-49e0-ae35-e3ccd80616ef
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038744226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.3038744226
Directory	/workspace/29.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.1539768345
Short name	T148
Test name
Test status
Simulation time	366480628 ps
CPU time	9.77 seconds
Started	Apr 20 04:09:44 PM PDT 24
Finished	Apr 20 04:09:54 PM PDT 24
Peak memory	205596 kb
Host	smart-9d445cd7-e8e7-4758-a7fe-bef5b99ed557
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539768345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.1 539768345
Directory	/workspace/3.keymgr_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.1585975314
Short name	T550
Test name
Test status
Simulation time	43947147 ps
CPU time	1.03 seconds
Started	Apr 20 04:09:44 PM PDT 24
Finished	Apr 20 04:09:45 PM PDT 24
Peak memory	205580 kb
Host	smart-e289e95a-1b01-4dd6-922a-9067f0b7a69f
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585975314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.1 585975314
Directory	/workspace/3.keymgr_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2219581428
Short name	T177
Test name
Test status
Simulation time	37780921 ps
CPU time	1.25 seconds
Started	Apr 20 04:09:46 PM PDT 24
Finished	Apr 20 04:09:48 PM PDT 24
Peak memory	205720 kb
Host	smart-7bd3fd63-6cee-4a6d-8d8e-f390d0884641
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219581428 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.2219581428
Directory	/workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.keymgr_csr_rw.1652344528
Short name	T524
Test name
Test status
Simulation time	28639506 ps
CPU time	0.92 seconds
Started	Apr 20 04:09:45 PM PDT 24
Finished	Apr 20 04:09:46 PM PDT 24
Peak memory	205480 kb
Host	smart-72932836-1dcd-42c8-8078-fc34fa80d0b3
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652344528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.1652344528
Directory	/workspace/3.keymgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.keymgr_intr_test.656708689
Short name	T515
Test name
Test status
Simulation time	27010198 ps
CPU time	0.71 seconds
Started	Apr 20 04:09:42 PM PDT 24
Finished	Apr 20 04:09:43 PM PDT 24
Peak memory	205564 kb
Host	smart-926622e5-3273-4d33-9b9e-4dbfa2e1a321
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656708689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.656708689
Directory	/workspace/3.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.3225102471
Short name	T447
Test name
Test status
Simulation time	202076746 ps
CPU time	2.01 seconds
Started	Apr 20 04:09:43 PM PDT 24
Finished	Apr 20 04:09:45 PM PDT 24
Peak memory	205628 kb
Host	smart-c34cb485-1a6e-43c5-a816-10956f268575
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225102471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa me_csr_outstanding.3225102471
Directory	/workspace/3.keymgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.1995357974
Short name	T171
Test name
Test status
Simulation time	918010965 ps
CPU time	4.57 seconds
Started	Apr 20 04:09:40 PM PDT 24
Finished	Apr 20 04:09:45 PM PDT 24
Peak memory	214092 kb
Host	smart-8d7ffde6-27a9-4cbc-895c-31206cd9a1b7
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995357974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado w_reg_errors.1995357974
Directory	/workspace/3.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.keymgr_tl_errors.2556967453
Short name	T170
Test name
Test status
Simulation time	271519715 ps
CPU time	3.4 seconds
Started	Apr 20 04:09:43 PM PDT 24
Finished	Apr 20 04:09:47 PM PDT 24
Peak memory	213912 kb
Host	smart-cc6e52c3-cbf1-4918-88f5-4fd370ee65b0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556967453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.2556967453
Directory	/workspace/3.keymgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.2674458800
Short name	T126
Test name
Test status
Simulation time	116728966 ps
CPU time	4.77 seconds
Started	Apr 20 04:09:43 PM PDT 24
Finished	Apr 20 04:09:49 PM PDT 24
Peak memory	213908 kb
Host	smart-0bbec3eb-cfb4-41b8-a565-5edfcb4e3d8b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674458800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err .2674458800
Directory	/workspace/3.keymgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.keymgr_intr_test.3089844675
Short name	T142
Test name
Test status
Simulation time	27239735 ps
CPU time	0.8 seconds
Started	Apr 20 04:10:18 PM PDT 24
Finished	Apr 20 04:10:19 PM PDT 24
Peak memory	205404 kb
Host	smart-ac1c4716-3588-487c-b944-b9cf7d3021fb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089844675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.3089844675
Directory	/workspace/30.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.keymgr_intr_test.1835371064
Short name	T180
Test name
Test status
Simulation time	49257584 ps
CPU time	0.9 seconds
Started	Apr 20 04:10:19 PM PDT 24
Finished	Apr 20 04:10:20 PM PDT 24
Peak memory	205524 kb
Host	smart-736390ee-bc59-4443-ada7-d91ba5d984cf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835371064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.1835371064
Directory	/workspace/31.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.keymgr_intr_test.1573483530
Short name	T509
Test name
Test status
Simulation time	19288743 ps
CPU time	0.76 seconds
Started	Apr 20 04:10:20 PM PDT 24
Finished	Apr 20 04:10:21 PM PDT 24
Peak memory	205532 kb
Host	smart-e1b98432-4285-4b99-9513-283112c339f5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573483530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.1573483530
Directory	/workspace/32.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.keymgr_intr_test.1995682631
Short name	T448
Test name
Test status
Simulation time	14586414 ps
CPU time	0.72 seconds
Started	Apr 20 04:10:20 PM PDT 24
Finished	Apr 20 04:10:21 PM PDT 24
Peak memory	205524 kb
Host	smart-0ec3eef6-c203-45f3-9bde-c216d45c58b5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995682631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.1995682631
Directory	/workspace/33.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.keymgr_intr_test.24269414
Short name	T533
Test name
Test status
Simulation time	21591652 ps
CPU time	0.75 seconds
Started	Apr 20 04:10:20 PM PDT 24
Finished	Apr 20 04:10:21 PM PDT 24
Peak memory	205564 kb
Host	smart-d0cff6a1-611d-49ff-92ad-a5360aa22e48
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24269414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.24269414
Directory	/workspace/34.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.keymgr_intr_test.1315829828
Short name	T384
Test name
Test status
Simulation time	14623409 ps
CPU time	0.72 seconds
Started	Apr 20 04:10:20 PM PDT 24
Finished	Apr 20 04:10:21 PM PDT 24
Peak memory	205504 kb
Host	smart-61b4a239-d175-45a6-98fa-1d67a1a9c6cb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315829828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.1315829828
Directory	/workspace/35.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.keymgr_intr_test.542663362
Short name	T539
Test name
Test status
Simulation time	37189453 ps
CPU time	0.73 seconds
Started	Apr 20 04:10:19 PM PDT 24
Finished	Apr 20 04:10:20 PM PDT 24
Peak memory	205516 kb
Host	smart-581de613-cc9d-4d7a-825c-4bcc3f34cc10
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542663362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.542663362
Directory	/workspace/36.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.keymgr_intr_test.3171934979
Short name	T496
Test name
Test status
Simulation time	115343758 ps
CPU time	0.83 seconds
Started	Apr 20 04:10:30 PM PDT 24
Finished	Apr 20 04:10:32 PM PDT 24
Peak memory	205496 kb
Host	smart-d227ac38-2da9-4b9e-b4b8-d0619947f1cd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171934979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.3171934979
Directory	/workspace/37.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.keymgr_intr_test.2540568583
Short name	T438
Test name
Test status
Simulation time	16072604 ps
CPU time	0.75 seconds
Started	Apr 20 04:10:20 PM PDT 24
Finished	Apr 20 04:10:21 PM PDT 24
Peak memory	205520 kb
Host	smart-852e11e5-9593-42a6-9601-a942d0a894f6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540568583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.2540568583
Directory	/workspace/38.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.keymgr_intr_test.2254776809
Short name	T431
Test name
Test status
Simulation time	10218073 ps
CPU time	0.84 seconds
Started	Apr 20 04:10:19 PM PDT 24
Finished	Apr 20 04:10:20 PM PDT 24
Peak memory	205512 kb
Host	smart-5f92f4c5-54e5-4a9c-a235-0fb65bc540b7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254776809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.2254776809
Directory	/workspace/39.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.714315914
Short name	T460
Test name
Test status
Simulation time	535305840 ps
CPU time	9.07 seconds
Started	Apr 20 04:09:48 PM PDT 24
Finished	Apr 20 04:09:57 PM PDT 24
Peak memory	205592 kb
Host	smart-b9d73cee-6f06-452d-97ee-dd75ef16afd7
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714315914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.714315914
Directory	/workspace/4.keymgr_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.2034523057
Short name	T455
Test name
Test status
Simulation time	264473400 ps
CPU time	12.25 seconds
Started	Apr 20 04:09:46 PM PDT 24
Finished	Apr 20 04:09:58 PM PDT 24
Peak memory	205548 kb
Host	smart-65e613a2-e1c0-46c4-bf3a-54ea8d48caff
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034523057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.2 034523057
Directory	/workspace/4.keymgr_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.2304236136
Short name	T484
Test name
Test status
Simulation time	73097677 ps
CPU time	1.17 seconds
Started	Apr 20 04:09:47 PM PDT 24
Finished	Apr 20 04:09:49 PM PDT 24
Peak memory	205576 kb
Host	smart-e016e88f-b9a3-428e-ae27-7dc2fb543304
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304236136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.2 304236136
Directory	/workspace/4.keymgr_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.2779530425
Short name	T165
Test name
Test status
Simulation time	23318402 ps
CPU time	1.6 seconds
Started	Apr 20 04:09:52 PM PDT 24
Finished	Apr 20 04:09:54 PM PDT 24
Peak memory	217596 kb
Host	smart-c7692f03-7132-4d18-9d3a-272cc155c867
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779530425 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.2779530425
Directory	/workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.keymgr_intr_test.190058472
Short name	T528
Test name
Test status
Simulation time	20973204 ps
CPU time	0.87 seconds
Started	Apr 20 04:09:46 PM PDT 24
Finished	Apr 20 04:09:47 PM PDT 24
Peak memory	205524 kb
Host	smart-541648d3-8ebc-4666-b17f-fb7f0a654652
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190058472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.190058472
Directory	/workspace/4.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.523545280
Short name	T545
Test name
Test status
Simulation time	85605143 ps
CPU time	1.54 seconds
Started	Apr 20 04:09:51 PM PDT 24
Finished	Apr 20 04:09:54 PM PDT 24
Peak memory	205716 kb
Host	smart-65119ca7-425b-4857-b242-1bf5108bf647
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523545280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sam e_csr_outstanding.523545280
Directory	/workspace/4.keymgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.2152652220
Short name	T123
Test name
Test status
Simulation time	114846983 ps
CPU time	3.64 seconds
Started	Apr 20 04:09:48 PM PDT 24
Finished	Apr 20 04:09:52 PM PDT 24
Peak memory	214076 kb
Host	smart-483413da-8651-4030-87cf-27a792ffec61
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152652220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado w_reg_errors.2152652220
Directory	/workspace/4.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.3178612481
Short name	T125
Test name
Test status
Simulation time	488171381 ps
CPU time	10.47 seconds
Started	Apr 20 04:09:46 PM PDT 24
Finished	Apr 20 04:09:57 PM PDT 24
Peak memory	222212 kb
Host	smart-6db6fb59-60e7-49c5-b356-18d95934e281
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178612481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4. keymgr_shadow_reg_errors_with_csr_rw.3178612481
Directory	/workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.keymgr_tl_errors.3577525918
Short name	T466
Test name
Test status
Simulation time	147207232 ps
CPU time	2.83 seconds
Started	Apr 20 04:09:46 PM PDT 24
Finished	Apr 20 04:09:49 PM PDT 24
Peak memory	213908 kb
Host	smart-83343093-6191-47a8-bae1-a41001c1ad64
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577525918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.3577525918
Directory	/workspace/4.keymgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/40.keymgr_intr_test.2154186526
Short name	T429
Test name
Test status
Simulation time	27578247 ps
CPU time	0.82 seconds
Started	Apr 20 04:10:20 PM PDT 24
Finished	Apr 20 04:10:21 PM PDT 24
Peak memory	205532 kb
Host	smart-65bd9b43-c2fb-4f3e-861f-7c28e7b09ecc
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154186526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.2154186526
Directory	/workspace/40.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.keymgr_intr_test.28054683
Short name	T482
Test name
Test status
Simulation time	9963875 ps
CPU time	0.8 seconds
Started	Apr 20 04:10:19 PM PDT 24
Finished	Apr 20 04:10:20 PM PDT 24
Peak memory	205520 kb
Host	smart-15b8925c-ca79-49f2-a1f6-20c3672a91d6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28054683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.28054683
Directory	/workspace/41.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.keymgr_intr_test.1769987489
Short name	T179
Test name
Test status
Simulation time	23106260 ps
CPU time	0.75 seconds
Started	Apr 20 04:10:20 PM PDT 24
Finished	Apr 20 04:10:21 PM PDT 24
Peak memory	205532 kb
Host	smart-a0bb4162-755d-4a02-88f1-bc43e35a0d15
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769987489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.1769987489
Directory	/workspace/42.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.keymgr_intr_test.1729856275
Short name	T454
Test name
Test status
Simulation time	10705273 ps
CPU time	0.78 seconds
Started	Apr 20 04:10:21 PM PDT 24
Finished	Apr 20 04:10:22 PM PDT 24
Peak memory	205536 kb
Host	smart-a0ab8d2e-da49-4b6c-8432-74d69e157a88
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729856275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.1729856275
Directory	/workspace/43.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.keymgr_intr_test.3404234771
Short name	T522
Test name
Test status
Simulation time	25656528 ps
CPU time	0.77 seconds
Started	Apr 20 04:10:29 PM PDT 24
Finished	Apr 20 04:10:30 PM PDT 24
Peak memory	205532 kb
Host	smart-7b0e37a6-e1c5-4f1b-a54a-90a530e5539b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404234771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.3404234771
Directory	/workspace/44.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.keymgr_intr_test.2940839565
Short name	T514
Test name
Test status
Simulation time	9202788 ps
CPU time	0.75 seconds
Started	Apr 20 04:10:29 PM PDT 24
Finished	Apr 20 04:10:30 PM PDT 24
Peak memory	205428 kb
Host	smart-1b7d9b7f-eb02-4cc6-bc5a-d08ce4d380a3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940839565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.2940839565
Directory	/workspace/45.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.keymgr_intr_test.202111522
Short name	T470
Test name
Test status
Simulation time	14982168 ps
CPU time	0.7 seconds
Started	Apr 20 04:10:32 PM PDT 24
Finished	Apr 20 04:10:34 PM PDT 24
Peak memory	205528 kb
Host	smart-cff3a092-8165-4a0c-a612-9a4e43f5b4eb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202111522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.202111522
Directory	/workspace/46.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.keymgr_intr_test.2959416816
Short name	T507
Test name
Test status
Simulation time	51352360 ps
CPU time	0.91 seconds
Started	Apr 20 04:10:31 PM PDT 24
Finished	Apr 20 04:10:33 PM PDT 24
Peak memory	205452 kb
Host	smart-b7de4e22-1701-44e8-9767-b14cad65fa0c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959416816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.2959416816
Directory	/workspace/47.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.keymgr_intr_test.1529732921
Short name	T502
Test name
Test status
Simulation time	38839275 ps
CPU time	0.74 seconds
Started	Apr 20 04:10:32 PM PDT 24
Finished	Apr 20 04:10:34 PM PDT 24
Peak memory	205528 kb
Host	smart-9a97102e-d01c-46bc-9d01-8658b8614229
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529732921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.1529732921
Directory	/workspace/48.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.keymgr_intr_test.2828547600
Short name	T536
Test name
Test status
Simulation time	88535318 ps
CPU time	0.72 seconds
Started	Apr 20 04:10:36 PM PDT 24
Finished	Apr 20 04:10:38 PM PDT 24
Peak memory	205420 kb
Host	smart-72bd92a3-fe77-4965-86d5-b10f852fa0a3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828547600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.2828547600
Directory	/workspace/49.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3326751032
Short name	T551
Test name
Test status
Simulation time	128276861 ps
CPU time	1.32 seconds
Started	Apr 20 04:09:51 PM PDT 24
Finished	Apr 20 04:09:54 PM PDT 24
Peak memory	214004 kb
Host	smart-afc984ff-a2a3-451f-ae66-b681838903fd
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326751032 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.3326751032
Directory	/workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.keymgr_csr_rw.617105537
Short name	T440
Test name
Test status
Simulation time	28961349 ps
CPU time	1.17 seconds
Started	Apr 20 04:09:49 PM PDT 24
Finished	Apr 20 04:09:51 PM PDT 24
Peak memory	205568 kb
Host	smart-6dce8c87-74ac-4724-9c17-d058a6015c26
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617105537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.617105537
Directory	/workspace/5.keymgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.keymgr_intr_test.3464831862
Short name	T512
Test name
Test status
Simulation time	34613898 ps
CPU time	0.82 seconds
Started	Apr 20 04:09:50 PM PDT 24
Finished	Apr 20 04:09:53 PM PDT 24
Peak memory	205332 kb
Host	smart-af025e11-67af-4b4f-9c62-0292cec172bd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464831862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.3464831862
Directory	/workspace/5.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.1195773406
Short name	T520
Test name
Test status
Simulation time	352074666 ps
CPU time	5.96 seconds
Started	Apr 20 04:09:49 PM PDT 24
Finished	Apr 20 04:09:56 PM PDT 24
Peak memory	214112 kb
Host	smart-4ae94e95-7000-454e-b1fb-d23c68ab7059
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195773406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado w_reg_errors.1195773406
Directory	/workspace/5.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.2623922308
Short name	T124
Test name
Test status
Simulation time	232324626 ps
CPU time	8.01 seconds
Started	Apr 20 04:09:52 PM PDT 24
Finished	Apr 20 04:10:01 PM PDT 24
Peak memory	213960 kb
Host	smart-3846e2cd-21ea-4c75-b3b2-445f23f82312
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623922308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5. keymgr_shadow_reg_errors_with_csr_rw.2623922308
Directory	/workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.keymgr_tl_errors.1868930655
Short name	T508
Test name
Test status
Simulation time	26566035 ps
CPU time	2.01 seconds
Started	Apr 20 04:09:51 PM PDT 24
Finished	Apr 20 04:09:55 PM PDT 24
Peak memory	216484 kb
Host	smart-40761dcf-602f-4ead-916a-c64758293694
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868930655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.1868930655
Directory	/workspace/5.keymgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.3967758742
Short name	T162
Test name
Test status
Simulation time	207193989 ps
CPU time	5.68 seconds
Started	Apr 20 04:09:50 PM PDT 24
Finished	Apr 20 04:09:58 PM PDT 24
Peak memory	208796 kb
Host	smart-ca674fd9-4304-4a11-99c5-ae002d8c8af6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967758742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err .3967758742
Directory	/workspace/5.keymgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.1670532516
Short name	T166
Test name
Test status
Simulation time	46369040 ps
CPU time	1.81 seconds
Started	Apr 20 04:09:57 PM PDT 24
Finished	Apr 20 04:09:59 PM PDT 24
Peak memory	213884 kb
Host	smart-b39ef7ed-e30e-4ec4-a095-67e4e37f5709
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670532516 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.1670532516
Directory	/workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.keymgr_csr_rw.364399905
Short name	T499
Test name
Test status
Simulation time	40481770 ps
CPU time	1.18 seconds
Started	Apr 20 04:09:54 PM PDT 24
Finished	Apr 20 04:09:55 PM PDT 24
Peak memory	205608 kb
Host	smart-21b16966-21cd-4617-b83b-c1036a88966b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364399905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.364399905
Directory	/workspace/6.keymgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.keymgr_intr_test.1254944052
Short name	T469
Test name
Test status
Simulation time	13800859 ps
CPU time	0.84 seconds
Started	Apr 20 04:09:54 PM PDT 24
Finished	Apr 20 04:09:55 PM PDT 24
Peak memory	205572 kb
Host	smart-fd6bc59a-cf56-4bc2-99df-251c883d3d7c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254944052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.1254944052
Directory	/workspace/6.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.2498358615
Short name	T523
Test name
Test status
Simulation time	88077287 ps
CPU time	2.46 seconds
Started	Apr 20 04:09:51 PM PDT 24
Finished	Apr 20 04:09:55 PM PDT 24
Peak memory	205532 kb
Host	smart-ac1bb113-39dd-4b03-a5e2-c4d0d5926ca7
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498358615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa me_csr_outstanding.2498358615
Directory	/workspace/6.keymgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.2145238088
Short name	T498
Test name
Test status
Simulation time	416286002 ps
CPU time	5.14 seconds
Started	Apr 20 04:09:51 PM PDT 24
Finished	Apr 20 04:09:58 PM PDT 24
Peak memory	214104 kb
Host	smart-36ba46ad-746c-4f18-9342-376815c9bab8
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145238088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado w_reg_errors.2145238088
Directory	/workspace/6.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.4006129333
Short name	T527
Test name
Test status
Simulation time	631187201 ps
CPU time	9.34 seconds
Started	Apr 20 04:09:53 PM PDT 24
Finished	Apr 20 04:10:03 PM PDT 24
Peak memory	213728 kb
Host	smart-704a0326-488c-47fa-be51-0faca35866c4
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006129333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6. keymgr_shadow_reg_errors_with_csr_rw.4006129333
Directory	/workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.keymgr_tl_errors.3076753176
Short name	T483
Test name
Test status
Simulation time	30451285 ps
CPU time	2.04 seconds
Started	Apr 20 04:09:53 PM PDT 24
Finished	Apr 20 04:09:56 PM PDT 24
Peak memory	214000 kb
Host	smart-0887d083-db2a-4280-a179-8a0a0ef6eae5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076753176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.3076753176
Directory	/workspace/6.keymgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.1394970003
Short name	T489
Test name
Test status
Simulation time	30010193 ps
CPU time	2.19 seconds
Started	Apr 20 04:09:58 PM PDT 24
Finished	Apr 20 04:10:01 PM PDT 24
Peak memory	213920 kb
Host	smart-205d45d6-3ed2-424f-b5b3-2330ac24e114
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394970003 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.1394970003
Directory	/workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.keymgr_csr_rw.3217228512
Short name	T481
Test name
Test status
Simulation time	11282930 ps
CPU time	1.15 seconds
Started	Apr 20 04:09:57 PM PDT 24
Finished	Apr 20 04:09:58 PM PDT 24
Peak memory	205652 kb
Host	smart-5ff86d32-d4f9-488b-a71b-ca4bf1ad021f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217228512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.3217228512
Directory	/workspace/7.keymgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.keymgr_intr_test.2907842248
Short name	T535
Test name
Test status
Simulation time	22006650 ps
CPU time	0.69 seconds
Started	Apr 20 04:09:55 PM PDT 24
Finished	Apr 20 04:09:56 PM PDT 24
Peak memory	205432 kb
Host	smart-aff23e57-b3ae-4927-bdce-d9308ae107a1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907842248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.2907842248
Directory	/workspace/7.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.3438223446
Short name	T456
Test name
Test status
Simulation time	9181475770 ps
CPU time	86.47 seconds
Started	Apr 20 04:09:55 PM PDT 24
Finished	Apr 20 04:11:21 PM PDT 24
Peak memory	231180 kb
Host	smart-0ff5924d-07c6-4e06-a0d0-003183bae9cb
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438223446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado w_reg_errors.3438223446
Directory	/workspace/7.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.687486659
Short name	T549
Test name
Test status
Simulation time	283057265 ps
CPU time	11.65 seconds
Started	Apr 20 04:09:51 PM PDT 24
Finished	Apr 20 04:10:04 PM PDT 24
Peak memory	220848 kb
Host	smart-e8bf5eb6-f07f-43e8-b356-975895dcbe3d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687486659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST _SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.k eymgr_shadow_reg_errors_with_csr_rw.687486659
Directory	/workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.keymgr_tl_errors.449336713
Short name	T546
Test name
Test status
Simulation time	141265536 ps
CPU time	2.17 seconds
Started	Apr 20 04:09:54 PM PDT 24
Finished	Apr 20 04:09:57 PM PDT 24
Peak memory	213980 kb
Host	smart-599084e0-a2ed-4ce2-a2ee-2373a7d1f7f9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449336713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.449336713
Directory	/workspace/7.keymgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.1221369151
Short name	T168
Test name
Test status
Simulation time	40141825 ps
CPU time	1.24 seconds
Started	Apr 20 04:09:56 PM PDT 24
Finished	Apr 20 04:09:57 PM PDT 24
Peak memory	205648 kb
Host	smart-aaf3e8fe-f99f-441e-8929-aefe99fc58fa
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221369151 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.1221369151
Directory	/workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.keymgr_csr_rw.1141357595
Short name	T501
Test name
Test status
Simulation time	49579406 ps
CPU time	0.95 seconds
Started	Apr 20 04:09:58 PM PDT 24
Finished	Apr 20 04:09:59 PM PDT 24
Peak memory	205512 kb
Host	smart-c90b7baf-83dc-4f81-a2fe-cb558ca9dfcd
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141357595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.1141357595
Directory	/workspace/8.keymgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.keymgr_intr_test.442862795
Short name	T435
Test name
Test status
Simulation time	7615090 ps
CPU time	0.77 seconds
Started	Apr 20 04:09:56 PM PDT 24
Finished	Apr 20 04:09:57 PM PDT 24
Peak memory	205528 kb
Host	smart-b52b6c4f-0deb-462a-a5f1-2f17c2191350
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442862795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.442862795
Directory	/workspace/8.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.2440598167
Short name	T467
Test name
Test status
Simulation time	57774010 ps
CPU time	2.39 seconds
Started	Apr 20 04:09:56 PM PDT 24
Finished	Apr 20 04:09:59 PM PDT 24
Peak memory	205628 kb
Host	smart-66f8e6b5-937f-4944-ac36-44651e9491a7
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440598167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa me_csr_outstanding.2440598167
Directory	/workspace/8.keymgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.1622496196
Short name	T169
Test name
Test status
Simulation time	96689956 ps
CPU time	3.11 seconds
Started	Apr 20 04:09:59 PM PDT 24
Finished	Apr 20 04:10:03 PM PDT 24
Peak memory	214072 kb
Host	smart-68119b03-e8f5-49ad-8255-d8b2f0817bb1
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622496196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado w_reg_errors.1622496196
Directory	/workspace/8.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.656358573
Short name	T492
Test name
Test status
Simulation time	962734214 ps
CPU time	15.85 seconds
Started	Apr 20 04:10:03 PM PDT 24
Finished	Apr 20 04:10:19 PM PDT 24
Peak memory	214032 kb
Host	smart-eefc67e0-68a3-44ff-b5d2-123705e1c748
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656358573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST _SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.k eymgr_shadow_reg_errors_with_csr_rw.656358573
Directory	/workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.keymgr_tl_errors.3778876936
Short name	T526
Test name
Test status
Simulation time	28162470 ps
CPU time	1.89 seconds
Started	Apr 20 04:09:55 PM PDT 24
Finished	Apr 20 04:09:57 PM PDT 24
Peak memory	215224 kb
Host	smart-afad7842-7b1a-4116-9c66-62ff555e3bcd
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778876936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.3778876936
Directory	/workspace/8.keymgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.2443065401
Short name	T449
Test name
Test status
Simulation time	71541790 ps
CPU time	1.11 seconds
Started	Apr 20 04:10:07 PM PDT 24
Finished	Apr 20 04:10:08 PM PDT 24
Peak memory	205652 kb
Host	smart-5a5ff9c1-b781-44e8-8487-c516b5fb966a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443065401 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.2443065401
Directory	/workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.keymgr_intr_test.1817403866
Short name	T517
Test name
Test status
Simulation time	23378505 ps
CPU time	0.75 seconds
Started	Apr 20 04:09:58 PM PDT 24
Finished	Apr 20 04:09:59 PM PDT 24
Peak memory	205500 kb
Host	smart-5a0c1d89-8ed0-4f0a-a72b-a3485ad0c7ae
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817403866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.1817403866
Directory	/workspace/9.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.2378246431
Short name	T505
Test name
Test status
Simulation time	21447726 ps
CPU time	1.43 seconds
Started	Apr 20 04:10:02 PM PDT 24
Finished	Apr 20 04:10:04 PM PDT 24
Peak memory	205600 kb
Host	smart-1f800d67-ec34-4bf8-b433-b99c0510c3c7
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378246431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa me_csr_outstanding.2378246431
Directory	/workspace/9.keymgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.2268398392
Short name	T119
Test name
Test status
Simulation time	263064696 ps
CPU time	6.07 seconds
Started	Apr 20 04:09:56 PM PDT 24
Finished	Apr 20 04:10:03 PM PDT 24
Peak memory	214104 kb
Host	smart-14235f28-e183-41eb-b8fb-0dea43928153
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268398392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado w_reg_errors.2268398392
Directory	/workspace/9.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.2150499121
Short name	T472
Test name
Test status
Simulation time	172568449 ps
CPU time	4.91 seconds
Started	Apr 20 04:10:03 PM PDT 24
Finished	Apr 20 04:10:08 PM PDT 24
Peak memory	213944 kb
Host	smart-1dcf081e-153a-48e7-adbb-f700db30d9d7
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150499121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9. keymgr_shadow_reg_errors_with_csr_rw.2150499121
Directory	/workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.keymgr_tl_errors.2253844229
Short name	T479
Test name
Test status
Simulation time	68177730 ps
CPU time	2.17 seconds
Started	Apr 20 04:09:57 PM PDT 24
Finished	Apr 20 04:09:59 PM PDT 24
Peak memory	213944 kb
Host	smart-0a6df116-da58-4837-aed2-d1e3c0736c2c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253844229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.2253844229
Directory	/workspace/9.keymgr_tl_errors/latest

Test location	/workspace/coverage/default/0.keymgr_alert_test.3343731153
Short name	T706
Test name
Test status
Simulation time	12684627 ps
CPU time	0.82 seconds
Started	Apr 20 04:04:24 PM PDT 24
Finished	Apr 20 04:04:25 PM PDT 24
Peak memory	205864 kb
Host	smart-31f31e92-4368-404b-86e3-887572be2708
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343731153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.3343731153
Directory	/workspace/0.keymgr_alert_test/latest

Test location	/workspace/coverage/default/0.keymgr_cfg_regwen.2235628454
Short name	T309
Test name
Test status
Simulation time	71163379 ps
CPU time	4.43 seconds
Started	Apr 20 04:04:18 PM PDT 24
Finished	Apr 20 04:04:22 PM PDT 24
Peak memory	214428 kb
Host	smart-19b8acc9-1eab-4c8f-a0d4-fb82d19e8d54
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2235628454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.2235628454
Directory	/workspace/0.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/0.keymgr_direct_to_disabled.1363409932
Short name	T588
Test name
Test status
Simulation time	60030256 ps
CPU time	3.15 seconds
Started	Apr 20 04:04:21 PM PDT 24
Finished	Apr 20 04:04:25 PM PDT 24
Peak memory	214408 kb
Host	smart-08fdace5-90f5-405a-b8f0-de818e6be528
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1363409932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.1363409932
Directory	/workspace/0.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/0.keymgr_hwsw_invalid_input.4140318232
Short name	T87
Test name
Test status
Simulation time	237565414 ps
CPU time	4.35 seconds
Started	Apr 20 04:04:22 PM PDT 24
Finished	Apr 20 04:04:27 PM PDT 24
Peak memory	209348 kb
Host	smart-bebe3218-e111-4564-93af-db59968451fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4140318232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.4140318232
Directory	/workspace/0.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/0.keymgr_lc_disable.2588196765
Short name	T691
Test name
Test status
Simulation time	192089101 ps
CPU time	1.92 seconds
Started	Apr 20 04:04:21 PM PDT 24
Finished	Apr 20 04:04:24 PM PDT 24
Peak memory	206132 kb
Host	smart-27af33f8-adef-48e9-9f82-45527cfbaa7d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2588196765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.2588196765
Directory	/workspace/0.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/0.keymgr_random.3991030507
Short name	T310
Test name
Test status
Simulation time	109044609 ps
CPU time	4.08 seconds
Started	Apr 20 04:04:14 PM PDT 24
Finished	Apr 20 04:04:18 PM PDT 24
Peak memory	208148 kb
Host	smart-ec010f30-2f86-4a24-8c18-4aa2adada4ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3991030507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.3991030507
Directory	/workspace/0.keymgr_random/latest

Test location	/workspace/coverage/default/0.keymgr_sideload.3747952576
Short name	T602
Test name
Test status
Simulation time	872641307 ps
CPU time	3.22 seconds
Started	Apr 20 04:04:14 PM PDT 24
Finished	Apr 20 04:04:17 PM PDT 24
Peak memory	206772 kb
Host	smart-b0378dec-c26d-43bb-ab31-1146f9c4d408
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3747952576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.3747952576
Directory	/workspace/0.keymgr_sideload/latest

Test location	/workspace/coverage/default/0.keymgr_sideload_aes.2691595964
Short name	T390
Test name
Test status
Simulation time	22822899 ps
CPU time	1.88 seconds
Started	Apr 20 04:04:13 PM PDT 24
Finished	Apr 20 04:04:16 PM PDT 24
Peak memory	206828 kb
Host	smart-a8ef881d-d712-4fcb-987d-7fae4fc17c72
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691595964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.2691595964
Directory	/workspace/0.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/0.keymgr_sideload_kmac.859352448
Short name	T660
Test name
Test status
Simulation time	257536976 ps
CPU time	3.28 seconds
Started	Apr 20 04:04:14 PM PDT 24
Finished	Apr 20 04:04:18 PM PDT 24
Peak memory	208804 kb
Host	smart-f21d6767-627c-4400-938b-38d0cc8663a9
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859352448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.859352448
Directory	/workspace/0.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/0.keymgr_sideload_otbn.224726565
Short name	T652
Test name
Test status
Simulation time	863048930 ps
CPU time	6.88 seconds
Started	Apr 20 04:04:15 PM PDT 24
Finished	Apr 20 04:04:22 PM PDT 24
Peak memory	208464 kb
Host	smart-612cb08b-bd96-4afc-8eac-7a58771b77f8
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224726565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.224726565
Directory	/workspace/0.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/0.keymgr_sideload_protect.895515652
Short name	T806
Test name
Test status
Simulation time	497915478 ps
CPU time	14.39 seconds
Started	Apr 20 04:04:20 PM PDT 24
Finished	Apr 20 04:04:35 PM PDT 24
Peak memory	209892 kb
Host	smart-d52e5d9a-1297-4490-a88d-b3c49983bd7d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=895515652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.895515652
Directory	/workspace/0.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/0.keymgr_smoke.2534786832
Short name	T779
Test name
Test status
Simulation time	751183159 ps
CPU time	5.1 seconds
Started	Apr 20 04:04:13 PM PDT 24
Finished	Apr 20 04:04:19 PM PDT 24
Peak memory	208672 kb
Host	smart-b4133c9d-aa05-4aa6-ac13-8c022abf7093
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2534786832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.2534786832
Directory	/workspace/0.keymgr_smoke/latest

Test location	/workspace/coverage/default/0.keymgr_sw_invalid_input.3996485900
Short name	T1011
Test name
Test status
Simulation time	343552482 ps
CPU time	4.67 seconds
Started	Apr 20 04:04:17 PM PDT 24
Finished	Apr 20 04:04:22 PM PDT 24
Peak memory	214292 kb
Host	smart-d78584ce-2090-450b-8ef3-d1164d8fd919
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3996485900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.3996485900
Directory	/workspace/0.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/0.keymgr_sync_async_fault_cross.804188362
Short name	T39
Test name
Test status
Simulation time	160299883 ps
CPU time	1.46 seconds
Started	Apr 20 04:04:22 PM PDT 24
Finished	Apr 20 04:04:24 PM PDT 24
Peak memory	209712 kb
Host	smart-5463fcf0-d80a-40d9-a2da-f321524893d3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=804188362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.804188362
Directory	/workspace/0.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/1.keymgr_alert_test.4053605684
Short name	T968
Test name
Test status
Simulation time	31000798 ps
CPU time	0.86 seconds
Started	Apr 20 04:04:38 PM PDT 24
Finished	Apr 20 04:04:39 PM PDT 24
Peak memory	205808 kb
Host	smart-fd5f2b6f-a619-4873-870e-802ed6b2184c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053605684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.4053605684
Directory	/workspace/1.keymgr_alert_test/latest

Test location	/workspace/coverage/default/1.keymgr_cfg_regwen.1204170666
Short name	T399
Test name
Test status
Simulation time	891256068 ps
CPU time	12.61 seconds
Started	Apr 20 04:04:28 PM PDT 24
Finished	Apr 20 04:04:41 PM PDT 24
Peak memory	214888 kb
Host	smart-6a5815f4-f6c0-4b1b-a87a-4689bf1aef4c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1204170666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.1204170666
Directory	/workspace/1.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/1.keymgr_custom_cm.3158414746
Short name	T849
Test name
Test status
Simulation time	425911581 ps
CPU time	2.11 seconds
Started	Apr 20 04:04:30 PM PDT 24
Finished	Apr 20 04:04:33 PM PDT 24
Peak memory	209920 kb
Host	smart-777976a8-2bff-4aa0-bf1f-2157e48911a5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3158414746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.3158414746
Directory	/workspace/1.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/1.keymgr_direct_to_disabled.4016527044
Short name	T771
Test name
Test status
Simulation time	159509157 ps
CPU time	6.73 seconds
Started	Apr 20 04:04:27 PM PDT 24
Finished	Apr 20 04:04:34 PM PDT 24
Peak memory	210372 kb
Host	smart-59535cc5-74ad-4485-a4f7-8a21dc173c68
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4016527044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.4016527044
Directory	/workspace/1.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/1.keymgr_hwsw_invalid_input.4094784401
Short name	T727
Test name
Test status
Simulation time	1116886547 ps
CPU time	35.79 seconds
Started	Apr 20 04:04:28 PM PDT 24
Finished	Apr 20 04:05:05 PM PDT 24
Peak memory	221972 kb
Host	smart-550176b7-0b49-4e1c-b049-a49b8a787c95
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4094784401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.4094784401
Directory	/workspace/1.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/1.keymgr_lc_disable.3580221798
Short name	T852
Test name
Test status
Simulation time	438195247 ps
CPU time	5.07 seconds
Started	Apr 20 04:04:28 PM PDT 24
Finished	Apr 20 04:04:33 PM PDT 24
Peak memory	222464 kb
Host	smart-070243c4-3d4a-4819-bd1f-2c7c691c86b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3580221798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.3580221798
Directory	/workspace/1.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/1.keymgr_random.1993839670
Short name	T724
Test name
Test status
Simulation time	196415091 ps
CPU time	6.21 seconds
Started	Apr 20 04:04:28 PM PDT 24
Finished	Apr 20 04:04:34 PM PDT 24
Peak memory	214224 kb
Host	smart-df003a6c-4db3-45d8-b336-9fcf4f97a122
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1993839670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.1993839670
Directory	/workspace/1.keymgr_random/latest

Test location	/workspace/coverage/default/1.keymgr_sideload.3802545942
Short name	T1046
Test name
Test status
Simulation time	459071102 ps
CPU time	3.17 seconds
Started	Apr 20 04:04:27 PM PDT 24
Finished	Apr 20 04:04:31 PM PDT 24
Peak memory	208656 kb
Host	smart-10247806-0001-4e53-bf24-7c518bd98b88
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3802545942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.3802545942
Directory	/workspace/1.keymgr_sideload/latest

Test location	/workspace/coverage/default/1.keymgr_sideload_aes.2430967219
Short name	T262
Test name
Test status
Simulation time	163391030 ps
CPU time	2.13 seconds
Started	Apr 20 04:04:25 PM PDT 24
Finished	Apr 20 04:04:27 PM PDT 24
Peak memory	206784 kb
Host	smart-ebd9d003-beb8-472f-90bc-5f340d6e234c
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430967219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.2430967219
Directory	/workspace/1.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/1.keymgr_sideload_kmac.2853302480
Short name	T725
Test name
Test status
Simulation time	795459142 ps
CPU time	19.81 seconds
Started	Apr 20 04:04:24 PM PDT 24
Finished	Apr 20 04:04:44 PM PDT 24
Peak memory	208012 kb
Host	smart-fcc6c466-1527-4132-ae36-47c0988d450b
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853302480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.2853302480
Directory	/workspace/1.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/1.keymgr_sideload_protect.4292055270
Short name	T1061
Test name
Test status
Simulation time	180152823 ps
CPU time	3.84 seconds
Started	Apr 20 04:04:31 PM PDT 24
Finished	Apr 20 04:04:35 PM PDT 24
Peak memory	208944 kb
Host	smart-94c7f462-5dbd-46f1-96bb-19657a1177a8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4292055270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.4292055270
Directory	/workspace/1.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/1.keymgr_smoke.283022900
Short name	T1
Test name
Test status
Simulation time	1201673141 ps
CPU time	7.98 seconds
Started	Apr 20 04:04:24 PM PDT 24
Finished	Apr 20 04:04:32 PM PDT 24
Peak memory	208716 kb
Host	smart-62c81aa6-60c9-4c46-8617-54af599ab3d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=283022900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.283022900
Directory	/workspace/1.keymgr_smoke/latest

Test location	/workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.2301186083
Short name	T614
Test name
Test status
Simulation time	123115707 ps
CPU time	6.67 seconds
Started	Apr 20 04:04:35 PM PDT 24
Finished	Apr 20 04:04:42 PM PDT 24
Peak memory	222720 kb
Host	smart-78514a75-56f1-42d5-a4dc-12c74802033b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301186083 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.2301186083
Directory	/workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/1.keymgr_sw_invalid_input.3184660979
Short name	T137
Test name
Test status
Simulation time	348462606 ps
CPU time	7.82 seconds
Started	Apr 20 04:04:27 PM PDT 24
Finished	Apr 20 04:04:35 PM PDT 24
Peak memory	208472 kb
Host	smart-b20fbc81-2e94-43a4-af9e-6797ee44945b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3184660979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.3184660979
Directory	/workspace/1.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/1.keymgr_sync_async_fault_cross.982252194
Short name	T952
Test name
Test status
Simulation time	63195819 ps
CPU time	2.84 seconds
Started	Apr 20 04:04:30 PM PDT 24
Finished	Apr 20 04:04:34 PM PDT 24
Peak memory	210140 kb
Host	smart-c93e2035-7bdc-4841-bf55-54e4b9018ee8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=982252194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.982252194
Directory	/workspace/1.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/10.keymgr_alert_test.3111086887
Short name	T601
Test name
Test status
Simulation time	112783929 ps
CPU time	0.91 seconds
Started	Apr 20 04:05:53 PM PDT 24
Finished	Apr 20 04:05:54 PM PDT 24
Peak memory	205896 kb
Host	smart-1d125608-5f5b-4153-9a10-c5902d3301c3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111086887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.3111086887
Directory	/workspace/10.keymgr_alert_test/latest

Test location	/workspace/coverage/default/10.keymgr_custom_cm.2120442560
Short name	T1026
Test name
Test status
Simulation time	805327489 ps
CPU time	15.03 seconds
Started	Apr 20 04:05:49 PM PDT 24
Finished	Apr 20 04:06:04 PM PDT 24
Peak memory	209428 kb
Host	smart-eb501a99-b8a4-4563-a22b-9760a448f475
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2120442560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.2120442560
Directory	/workspace/10.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/10.keymgr_direct_to_disabled.2000360379
Short name	T837
Test name
Test status
Simulation time	181544882 ps
CPU time	3.97 seconds
Started	Apr 20 04:05:45 PM PDT 24
Finished	Apr 20 04:05:49 PM PDT 24
Peak memory	214252 kb
Host	smart-b1229d42-a51a-48aa-972a-c8ebf08f13d3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2000360379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.2000360379
Directory	/workspace/10.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/10.keymgr_hwsw_invalid_input.3806237006
Short name	T1040
Test name
Test status
Simulation time	290808127 ps
CPU time	3.46 seconds
Started	Apr 20 04:05:50 PM PDT 24
Finished	Apr 20 04:05:54 PM PDT 24
Peak memory	208704 kb
Host	smart-62caca0d-c778-488f-b628-535059a7c902
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3806237006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.3806237006
Directory	/workspace/10.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/10.keymgr_kmac_rsp_err.3735071879
Short name	T85
Test name
Test status
Simulation time	451054307 ps
CPU time	5.54 seconds
Started	Apr 20 04:05:49 PM PDT 24
Finished	Apr 20 04:05:55 PM PDT 24
Peak memory	222444 kb
Host	smart-1cc54287-78eb-4b61-9565-8bcd7ab302f7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3735071879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.3735071879
Directory	/workspace/10.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/10.keymgr_random.166645712
Short name	T870
Test name
Test status
Simulation time	168550352 ps
CPU time	7.21 seconds
Started	Apr 20 04:05:48 PM PDT 24
Finished	Apr 20 04:05:55 PM PDT 24
Peak memory	218360 kb
Host	smart-1e542f40-f6f1-4df9-bf1d-31e1881c736b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=166645712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.166645712
Directory	/workspace/10.keymgr_random/latest

Test location	/workspace/coverage/default/10.keymgr_sideload.99718726
Short name	T710
Test name
Test status
Simulation time	39978138 ps
CPU time	2.78 seconds
Started	Apr 20 04:05:46 PM PDT 24
Finished	Apr 20 04:05:49 PM PDT 24
Peak memory	208400 kb
Host	smart-a57acd16-5075-4484-ab88-8774439a0b97
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=99718726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.99718726
Directory	/workspace/10.keymgr_sideload/latest

Test location	/workspace/coverage/default/10.keymgr_sideload_aes.3053484056
Short name	T654
Test name
Test status
Simulation time	212520226 ps
CPU time	6.32 seconds
Started	Apr 20 04:05:46 PM PDT 24
Finished	Apr 20 04:05:52 PM PDT 24
Peak memory	208452 kb
Host	smart-d2e42eb5-e5cf-481f-9a63-d8da7c8a4351
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053484056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.3053484056
Directory	/workspace/10.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/10.keymgr_sideload_kmac.30017039
Short name	T865
Test name
Test status
Simulation time	1990739683 ps
CPU time	49.04 seconds
Started	Apr 20 04:05:46 PM PDT 24
Finished	Apr 20 04:06:36 PM PDT 24
Peak memory	208556 kb
Host	smart-6578d222-294c-49b1-8ceb-aed457bc77ce
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30017039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.30017039
Directory	/workspace/10.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/10.keymgr_sideload_otbn.2026681811
Short name	T715
Test name
Test status
Simulation time	1310436608 ps
CPU time	5.42 seconds
Started	Apr 20 04:05:47 PM PDT 24
Finished	Apr 20 04:05:52 PM PDT 24
Peak memory	206864 kb
Host	smart-8d2cc12f-65b1-4f9f-9cd3-8be71110f92f
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026681811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.2026681811
Directory	/workspace/10.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/10.keymgr_sideload_protect.2879359919
Short name	T700
Test name
Test status
Simulation time	72944153 ps
CPU time	2.14 seconds
Started	Apr 20 04:05:50 PM PDT 24
Finished	Apr 20 04:05:53 PM PDT 24
Peak memory	218196 kb
Host	smart-234b224a-f670-4abf-898d-dc068b71cf92
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2879359919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.2879359919
Directory	/workspace/10.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/10.keymgr_smoke.117193070
Short name	T997
Test name
Test status
Simulation time	156444737 ps
CPU time	2.82 seconds
Started	Apr 20 04:05:47 PM PDT 24
Finished	Apr 20 04:05:50 PM PDT 24
Peak memory	208772 kb
Host	smart-cd522b58-dd13-4a84-a0a0-3db6bb56a09b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=117193070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.117193070
Directory	/workspace/10.keymgr_smoke/latest

Test location	/workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.2913726072
Short name	T206
Test name
Test status
Simulation time	446725406 ps
CPU time	5.62 seconds
Started	Apr 20 04:05:54 PM PDT 24
Finished	Apr 20 04:06:00 PM PDT 24
Peak memory	219500 kb
Host	smart-ea6645f1-41ae-4cfc-9e4f-50494f48011c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913726072 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.2913726072
Directory	/workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/10.keymgr_sw_invalid_input.754566173
Short name	T964
Test name
Test status
Simulation time	815220617 ps
CPU time	6.39 seconds
Started	Apr 20 04:05:45 PM PDT 24
Finished	Apr 20 04:05:52 PM PDT 24
Peak memory	207848 kb
Host	smart-877f14c8-f38e-41a6-a4ff-5167e0b8e006
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=754566173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.754566173
Directory	/workspace/10.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/10.keymgr_sync_async_fault_cross.3307095556
Short name	T880
Test name
Test status
Simulation time	526889500 ps
CPU time	3.86 seconds
Started	Apr 20 04:05:50 PM PDT 24
Finished	Apr 20 04:05:54 PM PDT 24
Peak memory	210432 kb
Host	smart-dd5121e3-26e1-4aac-b874-ef8a04b70ae6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3307095556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.3307095556
Directory	/workspace/10.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/11.keymgr_alert_test.3887477926
Short name	T920
Test name
Test status
Simulation time	60748257 ps
CPU time	0.84 seconds
Started	Apr 20 04:05:59 PM PDT 24
Finished	Apr 20 04:06:00 PM PDT 24
Peak memory	205816 kb
Host	smart-c8b832f0-b2c1-4ba0-a1cb-7fa9aeb7fd0d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887477926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.3887477926
Directory	/workspace/11.keymgr_alert_test/latest

Test location	/workspace/coverage/default/11.keymgr_custom_cm.514806951
Short name	T800
Test name
Test status
Simulation time	153341514 ps
CPU time	5.58 seconds
Started	Apr 20 04:05:56 PM PDT 24
Finished	Apr 20 04:06:02 PM PDT 24
Peak memory	222776 kb
Host	smart-6ba97428-d19a-49ad-a554-d2596cdc3edc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=514806951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.514806951
Directory	/workspace/11.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/11.keymgr_direct_to_disabled.2762637776
Short name	T75
Test name
Test status
Simulation time	565198648 ps
CPU time	3.18 seconds
Started	Apr 20 04:05:56 PM PDT 24
Finished	Apr 20 04:06:00 PM PDT 24
Peak memory	210064 kb
Host	smart-f8bcc3b5-fcd1-43e3-b5a4-6df30e1af451
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2762637776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.2762637776
Directory	/workspace/11.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/11.keymgr_hwsw_invalid_input.552788561
Short name	T775
Test name
Test status
Simulation time	62440564 ps
CPU time	3.83 seconds
Started	Apr 20 04:05:56 PM PDT 24
Finished	Apr 20 04:06:00 PM PDT 24
Peak memory	214348 kb
Host	smart-d06ff5be-e0d7-44e8-9ff5-78e34aee5380
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=552788561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.552788561
Directory	/workspace/11.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/11.keymgr_kmac_rsp_err.1493467993
Short name	T1045
Test name
Test status
Simulation time	3068834397 ps
CPU time	7.63 seconds
Started	Apr 20 04:05:57 PM PDT 24
Finished	Apr 20 04:06:05 PM PDT 24
Peak memory	210588 kb
Host	smart-f541efc8-7780-47a3-a72a-3a70c1f69653
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1493467993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.1493467993
Directory	/workspace/11.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/11.keymgr_lc_disable.835984356
Short name	T763
Test name
Test status
Simulation time	50313971 ps
CPU time	2.67 seconds
Started	Apr 20 04:05:57 PM PDT 24
Finished	Apr 20 04:06:00 PM PDT 24
Peak memory	214260 kb
Host	smart-decbee19-7871-4a7c-99f1-ad21e3d0010e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=835984356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.835984356
Directory	/workspace/11.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/11.keymgr_random.3672289769
Short name	T104
Test name
Test status
Simulation time	650799889 ps
CPU time	9.9 seconds
Started	Apr 20 04:05:55 PM PDT 24
Finished	Apr 20 04:06:05 PM PDT 24
Peak memory	210128 kb
Host	smart-979a4d82-ed6b-4882-a325-76dbcbecab7c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3672289769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.3672289769
Directory	/workspace/11.keymgr_random/latest

Test location	/workspace/coverage/default/11.keymgr_sideload.928685958
Short name	T190
Test name
Test status
Simulation time	74989235 ps
CPU time	2.6 seconds
Started	Apr 20 04:05:52 PM PDT 24
Finished	Apr 20 04:05:54 PM PDT 24
Peak memory	208548 kb
Host	smart-ff6c86eb-4168-4931-9101-d8d248fec70a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=928685958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.928685958
Directory	/workspace/11.keymgr_sideload/latest

Test location	/workspace/coverage/default/11.keymgr_sideload_aes.689096588
Short name	T823
Test name
Test status
Simulation time	67597530 ps
CPU time	3.58 seconds
Started	Apr 20 04:05:52 PM PDT 24
Finished	Apr 20 04:05:56 PM PDT 24
Peak memory	208636 kb
Host	smart-39a0760a-2ac1-4ae5-9c63-d96ad2e6160b
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689096588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.689096588
Directory	/workspace/11.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/11.keymgr_sideload_kmac.2164124594
Short name	T910
Test name
Test status
Simulation time	187500555 ps
CPU time	2.77 seconds
Started	Apr 20 04:05:53 PM PDT 24
Finished	Apr 20 04:05:56 PM PDT 24
Peak memory	207492 kb
Host	smart-76c8ce41-7bdf-4598-86c9-9c8c396103df
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164124594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.2164124594
Directory	/workspace/11.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/11.keymgr_sideload_otbn.943126170
Short name	T621
Test name
Test status
Simulation time	41119089 ps
CPU time	2.37 seconds
Started	Apr 20 04:05:55 PM PDT 24
Finished	Apr 20 04:05:58 PM PDT 24
Peak memory	207972 kb
Host	smart-06eeb3ef-6304-40ff-82b6-164175eed6ce
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943126170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.943126170
Directory	/workspace/11.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/11.keymgr_sideload_protect.3186727778
Short name	T703
Test name
Test status
Simulation time	19897160 ps
CPU time	1.6 seconds
Started	Apr 20 04:05:58 PM PDT 24
Finished	Apr 20 04:05:59 PM PDT 24
Peak memory	215304 kb
Host	smart-8da3ccdd-f299-454c-ab59-9f4039540368
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3186727778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.3186727778
Directory	/workspace/11.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/11.keymgr_smoke.3603887493
Short name	T552
Test name
Test status
Simulation time	45482928 ps
CPU time	2.81 seconds
Started	Apr 20 04:05:52 PM PDT 24
Finished	Apr 20 04:05:55 PM PDT 24
Peak memory	208596 kb
Host	smart-59d2424e-a355-4fab-a71e-0a01a7a01cd6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3603887493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.3603887493
Directory	/workspace/11.keymgr_smoke/latest

Test location	/workspace/coverage/default/11.keymgr_sw_invalid_input.4149768111
Short name	T972
Test name
Test status
Simulation time	119903531 ps
CPU time	5.18 seconds
Started	Apr 20 04:05:57 PM PDT 24
Finished	Apr 20 04:06:03 PM PDT 24
Peak memory	214372 kb
Host	smart-a47187fa-36b5-416b-9a2d-468e8ae0d710
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4149768111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.4149768111
Directory	/workspace/11.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/11.keymgr_sync_async_fault_cross.3273061858
Short name	T159
Test name
Test status
Simulation time	83109221 ps
CPU time	1.79 seconds
Started	Apr 20 04:05:57 PM PDT 24
Finished	Apr 20 04:05:59 PM PDT 24
Peak memory	210240 kb
Host	smart-8c75998e-2465-4915-b407-fc1b408563ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3273061858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.3273061858
Directory	/workspace/11.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/12.keymgr_alert_test.146197938
Short name	T709
Test name
Test status
Simulation time	42714991 ps
CPU time	0.75 seconds
Started	Apr 20 04:06:07 PM PDT 24
Finished	Apr 20 04:06:08 PM PDT 24
Peak memory	205864 kb
Host	smart-daf51a9d-cf28-4302-a398-19595926509e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146197938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.146197938
Directory	/workspace/12.keymgr_alert_test/latest

Test location	/workspace/coverage/default/12.keymgr_cfg_regwen.205219689
Short name	T898
Test name
Test status
Simulation time	643425866 ps
CPU time	8.42 seconds
Started	Apr 20 04:06:04 PM PDT 24
Finished	Apr 20 04:06:13 PM PDT 24
Peak memory	214248 kb
Host	smart-822c6f3f-7c52-4f40-a36c-2993b28ff0e9
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=205219689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.205219689
Directory	/workspace/12.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/12.keymgr_custom_cm.2417548086
Short name	T1018
Test name
Test status
Simulation time	151128017 ps
CPU time	4.71 seconds
Started	Apr 20 04:06:08 PM PDT 24
Finished	Apr 20 04:06:13 PM PDT 24
Peak memory	216324 kb
Host	smart-ddc51dd1-10ce-4c1c-a851-20a5940b2e77
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2417548086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.2417548086
Directory	/workspace/12.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/12.keymgr_direct_to_disabled.2307453813
Short name	T69
Test name
Test status
Simulation time	127032704 ps
CPU time	3.27 seconds
Started	Apr 20 04:06:03 PM PDT 24
Finished	Apr 20 04:06:07 PM PDT 24
Peak memory	214408 kb
Host	smart-1909eed1-8960-47f9-98d0-f63df707d1b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2307453813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.2307453813
Directory	/workspace/12.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/12.keymgr_hwsw_invalid_input.797948739
Short name	T1019
Test name
Test status
Simulation time	381885923 ps
CPU time	7.59 seconds
Started	Apr 20 04:06:05 PM PDT 24
Finished	Apr 20 04:06:13 PM PDT 24
Peak memory	214328 kb
Host	smart-5ee14c08-3d81-4229-b9d8-6ca85ce51871
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=797948739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.797948739
Directory	/workspace/12.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/12.keymgr_lc_disable.2142892633
Short name	T895
Test name
Test status
Simulation time	87092701 ps
CPU time	4.16 seconds
Started	Apr 20 04:06:05 PM PDT 24
Finished	Apr 20 04:06:09 PM PDT 24
Peak memory	209488 kb
Host	smart-f68ad3c3-7c4c-4b76-a1e8-013ec33597c7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2142892633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.2142892633
Directory	/workspace/12.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/12.keymgr_random.3371680112
Short name	T1060
Test name
Test status
Simulation time	108389036 ps
CPU time	3.81 seconds
Started	Apr 20 04:06:02 PM PDT 24
Finished	Apr 20 04:06:06 PM PDT 24
Peak memory	208112 kb
Host	smart-0579dc84-19a9-4c43-bd09-8aeff16ff3f2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3371680112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.3371680112
Directory	/workspace/12.keymgr_random/latest

Test location	/workspace/coverage/default/12.keymgr_sideload.2687460023
Short name	T760
Test name
Test status
Simulation time	394088375 ps
CPU time	3.88 seconds
Started	Apr 20 04:05:58 PM PDT 24
Finished	Apr 20 04:06:02 PM PDT 24
Peak memory	208716 kb
Host	smart-60ac8f1e-cddc-4e77-afde-e28b5bcf507a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2687460023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.2687460023
Directory	/workspace/12.keymgr_sideload/latest

Test location	/workspace/coverage/default/12.keymgr_sideload_aes.3723517149
Short name	T586
Test name
Test status
Simulation time	26850855 ps
CPU time	2.12 seconds
Started	Apr 20 04:06:02 PM PDT 24
Finished	Apr 20 04:06:04 PM PDT 24
Peak memory	208620 kb
Host	smart-71ac1ba0-4d82-4304-b9b1-15ce3d0583d5
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723517149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.3723517149
Directory	/workspace/12.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/12.keymgr_sideload_kmac.3545161029
Short name	T647
Test name
Test status
Simulation time	590555573 ps
CPU time	5.5 seconds
Started	Apr 20 04:06:05 PM PDT 24
Finished	Apr 20 04:06:11 PM PDT 24
Peak memory	208768 kb
Host	smart-4b0bddf6-d0f8-418f-a413-3a2b42e391e7
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545161029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.3545161029
Directory	/workspace/12.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/12.keymgr_sideload_otbn.3288662482
Short name	T876
Test name
Test status
Simulation time	44651651 ps
CPU time	2.68 seconds
Started	Apr 20 04:06:02 PM PDT 24
Finished	Apr 20 04:06:05 PM PDT 24
Peak memory	208284 kb
Host	smart-0a243724-7eb5-49c4-b0e5-fc059c83da96
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288662482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.3288662482
Directory	/workspace/12.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/12.keymgr_sideload_protect.3673011889
Short name	T620
Test name
Test status
Simulation time	1255896237 ps
CPU time	28.79 seconds
Started	Apr 20 04:06:07 PM PDT 24
Finished	Apr 20 04:06:36 PM PDT 24
Peak memory	219232 kb
Host	smart-f84108b7-a0b8-45ea-be30-b424acb013dd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3673011889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.3673011889
Directory	/workspace/12.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/12.keymgr_smoke.4033337902
Short name	T1024
Test name
Test status
Simulation time	231055614 ps
CPU time	3.84 seconds
Started	Apr 20 04:05:59 PM PDT 24
Finished	Apr 20 04:06:03 PM PDT 24
Peak memory	206680 kb
Host	smart-4b41bca8-c748-4095-87ac-0570f586665b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4033337902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.4033337902
Directory	/workspace/12.keymgr_smoke/latest

Test location	/workspace/coverage/default/12.keymgr_sw_invalid_input.991651594
Short name	T622
Test name
Test status
Simulation time	10631303948 ps
CPU time	66.51 seconds
Started	Apr 20 04:06:07 PM PDT 24
Finished	Apr 20 04:07:14 PM PDT 24
Peak memory	221288 kb
Host	smart-12d80c3e-c326-47aa-8568-7272688ca961
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=991651594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.991651594
Directory	/workspace/12.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/13.keymgr_alert_test.578267175
Short name	T954
Test name
Test status
Simulation time	63690432 ps
CPU time	0.74 seconds
Started	Apr 20 04:06:14 PM PDT 24
Finished	Apr 20 04:06:15 PM PDT 24
Peak memory	205876 kb
Host	smart-883d5737-b1af-4349-8664-f08109c08327
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578267175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.578267175
Directory	/workspace/13.keymgr_alert_test/latest

Test location	/workspace/coverage/default/13.keymgr_custom_cm.593305390
Short name	T813
Test name
Test status
Simulation time	161509570 ps
CPU time	1.66 seconds
Started	Apr 20 04:06:16 PM PDT 24
Finished	Apr 20 04:06:18 PM PDT 24
Peak memory	217116 kb
Host	smart-593259cf-1b0c-47ed-9296-31698c670fcb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=593305390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.593305390
Directory	/workspace/13.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/13.keymgr_direct_to_disabled.592841664
Short name	T51
Test name
Test status
Simulation time	39411003 ps
CPU time	2.2 seconds
Started	Apr 20 04:06:10 PM PDT 24
Finished	Apr 20 04:06:12 PM PDT 24
Peak memory	209932 kb
Host	smart-7d70a926-cfd7-46aa-bd97-dd99798daac7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=592841664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.592841664
Directory	/workspace/13.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/13.keymgr_hwsw_invalid_input.1424655258
Short name	T331
Test name
Test status
Simulation time	307117076 ps
CPU time	9.11 seconds
Started	Apr 20 04:06:16 PM PDT 24
Finished	Apr 20 04:06:26 PM PDT 24
Peak memory	221120 kb
Host	smart-32609c24-ecc1-4092-81f2-0a0d649dc116
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1424655258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.1424655258
Directory	/workspace/13.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/13.keymgr_kmac_rsp_err.442748122
Short name	T188
Test name
Test status
Simulation time	139801860 ps
CPU time	6.16 seconds
Started	Apr 20 04:06:09 PM PDT 24
Finished	Apr 20 04:06:16 PM PDT 24
Peak memory	214304 kb
Host	smart-1880beea-1a39-433a-b61a-b1993b1324ec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=442748122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.442748122
Directory	/workspace/13.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/13.keymgr_lc_disable.1065959055
Short name	T674
Test name
Test status
Simulation time	57700975 ps
CPU time	2.74 seconds
Started	Apr 20 04:06:16 PM PDT 24
Finished	Apr 20 04:06:19 PM PDT 24
Peak memory	209296 kb
Host	smart-5a0e8005-802d-498b-b049-ea75376b589d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1065959055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.1065959055
Directory	/workspace/13.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/13.keymgr_random.1320689327
Short name	T923
Test name
Test status
Simulation time	901523766 ps
CPU time	10.66 seconds
Started	Apr 20 04:06:10 PM PDT 24
Finished	Apr 20 04:06:21 PM PDT 24
Peak memory	208188 kb
Host	smart-c948af61-1e82-4dd8-badd-7e95bcd9726f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1320689327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.1320689327
Directory	/workspace/13.keymgr_random/latest

Test location	/workspace/coverage/default/13.keymgr_sideload.4182484206
Short name	T641
Test name
Test status
Simulation time	68533120 ps
CPU time	3.35 seconds
Started	Apr 20 04:06:11 PM PDT 24
Finished	Apr 20 04:06:14 PM PDT 24
Peak memory	207964 kb
Host	smart-30d2099b-55aa-4d29-8e23-2b0840800b27
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4182484206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.4182484206
Directory	/workspace/13.keymgr_sideload/latest

Test location	/workspace/coverage/default/13.keymgr_sideload_kmac.2365312457
Short name	T15
Test name
Test status
Simulation time	107093746 ps
CPU time	4.4 seconds
Started	Apr 20 04:06:16 PM PDT 24
Finished	Apr 20 04:06:21 PM PDT 24
Peak memory	209008 kb
Host	smart-288d226f-b70e-4a4f-a8dc-08d4c7d05acd
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365312457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.2365312457
Directory	/workspace/13.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/13.keymgr_sideload_otbn.3053725704
Short name	T650
Test name
Test status
Simulation time	58484610 ps
CPU time	3.2 seconds
Started	Apr 20 04:06:11 PM PDT 24
Finished	Apr 20 04:06:14 PM PDT 24
Peak memory	206928 kb
Host	smart-d9e36ef0-6453-4581-ba9b-f796c2b7e41e
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053725704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.3053725704
Directory	/workspace/13.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/13.keymgr_sideload_protect.4112589363
Short name	T975
Test name
Test status
Simulation time	1465800609 ps
CPU time	6.34 seconds
Started	Apr 20 04:06:13 PM PDT 24
Finished	Apr 20 04:06:19 PM PDT 24
Peak memory	209708 kb
Host	smart-5fa99759-a0a4-443f-b050-3fef4160a8fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4112589363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.4112589363
Directory	/workspace/13.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/13.keymgr_smoke.894608333
Short name	T426
Test name
Test status
Simulation time	870997144 ps
CPU time	27.64 seconds
Started	Apr 20 04:06:07 PM PDT 24
Finished	Apr 20 04:06:35 PM PDT 24
Peak memory	208188 kb
Host	smart-82da9a63-91b0-4573-94fc-c61de53a18bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=894608333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.894608333
Directory	/workspace/13.keymgr_smoke/latest

Test location	/workspace/coverage/default/13.keymgr_stress_all.3288593368
Short name	T1005
Test name
Test status
Simulation time	2676845618 ps
CPU time	30.19 seconds
Started	Apr 20 04:06:13 PM PDT 24
Finished	Apr 20 04:06:43 PM PDT 24
Peak memory	222152 kb
Host	smart-3e79105f-9090-4d4c-be4f-fec230243000
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288593368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.3288593368
Directory	/workspace/13.keymgr_stress_all/latest

Test location	/workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.1500299872
Short name	T886
Test name
Test status
Simulation time	211195933 ps
CPU time	2.77 seconds
Started	Apr 20 04:06:14 PM PDT 24
Finished	Apr 20 04:06:17 PM PDT 24
Peak memory	217892 kb
Host	smart-b2b5a502-2bd7-43d5-96bf-71d2fc2db63e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500299872 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.1500299872
Directory	/workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/13.keymgr_sw_invalid_input.2467234048
Short name	T983
Test name
Test status
Simulation time	45398430 ps
CPU time	3.12 seconds
Started	Apr 20 04:06:10 PM PDT 24
Finished	Apr 20 04:06:13 PM PDT 24
Peak memory	214308 kb
Host	smart-51e3e32a-51a6-4aa2-9c6d-a80a2775d8d4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2467234048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.2467234048
Directory	/workspace/13.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/13.keymgr_sync_async_fault_cross.570930225
Short name	T566
Test name
Test status
Simulation time	112172020 ps
CPU time	2.24 seconds
Started	Apr 20 04:06:16 PM PDT 24
Finished	Apr 20 04:06:19 PM PDT 24
Peak memory	214340 kb
Host	smart-3f482fba-9b9f-44c6-a7f5-6bac0d9e296b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=570930225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.570930225
Directory	/workspace/13.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/14.keymgr_alert_test.825894718
Short name	T1033
Test name
Test status
Simulation time	45322177 ps
CPU time	0.76 seconds
Started	Apr 20 04:06:16 PM PDT 24
Finished	Apr 20 04:06:17 PM PDT 24
Peak memory	205908 kb
Host	smart-c18297c0-f9d4-4b7e-89ca-ecc01bfdea26
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825894718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.825894718
Directory	/workspace/14.keymgr_alert_test/latest

Test location	/workspace/coverage/default/14.keymgr_cfg_regwen.3437788744
Short name	T424
Test name
Test status
Simulation time	717858893 ps
CPU time	12.73 seconds
Started	Apr 20 04:06:17 PM PDT 24
Finished	Apr 20 04:06:30 PM PDT 24
Peak memory	215288 kb
Host	smart-60c9e5a5-8968-48ca-9f74-aa1ad8fe49ca
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3437788744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.3437788744
Directory	/workspace/14.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/14.keymgr_custom_cm.3005055309
Short name	T21
Test name
Test status
Simulation time	2477086366 ps
CPU time	10.39 seconds
Started	Apr 20 04:06:18 PM PDT 24
Finished	Apr 20 04:06:29 PM PDT 24
Peak memory	222192 kb
Host	smart-502d385b-fc9d-4e0d-80dc-bac637afa793
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3005055309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.3005055309
Directory	/workspace/14.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/14.keymgr_direct_to_disabled.2040917172
Short name	T985
Test name
Test status
Simulation time	5011970994 ps
CPU time	18.09 seconds
Started	Apr 20 04:06:13 PM PDT 24
Finished	Apr 20 04:06:31 PM PDT 24
Peak memory	214428 kb
Host	smart-93b51bba-017b-445e-9e89-7427b23137bf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2040917172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.2040917172
Directory	/workspace/14.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/14.keymgr_hwsw_invalid_input.295308824
Short name	T1022
Test name
Test status
Simulation time	183094744 ps
CPU time	4.75 seconds
Started	Apr 20 04:06:18 PM PDT 24
Finished	Apr 20 04:06:23 PM PDT 24
Peak memory	214216 kb
Host	smart-1be477f6-27d1-46c8-8d82-48ea6a7f28ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=295308824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.295308824
Directory	/workspace/14.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/14.keymgr_kmac_rsp_err.2096172652
Short name	T1035
Test name
Test status
Simulation time	451167914 ps
CPU time	6.01 seconds
Started	Apr 20 04:06:17 PM PDT 24
Finished	Apr 20 04:06:23 PM PDT 24
Peak memory	214308 kb
Host	smart-76136ba6-5722-4eba-8a77-0d3d61afdb33
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2096172652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.2096172652
Directory	/workspace/14.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/14.keymgr_lc_disable.1904490970
Short name	T260
Test name
Test status
Simulation time	717090866 ps
CPU time	3.62 seconds
Started	Apr 20 04:06:18 PM PDT 24
Finished	Apr 20 04:06:22 PM PDT 24
Peak memory	220348 kb
Host	smart-c2451bff-b6ac-431a-a1c9-dd81fc934ee9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1904490970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.1904490970
Directory	/workspace/14.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/14.keymgr_random.4236901512
Short name	T860
Test name
Test status
Simulation time	152774050 ps
CPU time	6.74 seconds
Started	Apr 20 04:06:16 PM PDT 24
Finished	Apr 20 04:06:23 PM PDT 24
Peak memory	208532 kb
Host	smart-18ec5194-c1d6-4dec-af7c-f695ac61df6d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4236901512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.4236901512
Directory	/workspace/14.keymgr_random/latest

Test location	/workspace/coverage/default/14.keymgr_sideload.949535892
Short name	T287
Test name
Test status
Simulation time	86316824 ps
CPU time	4.39 seconds
Started	Apr 20 04:06:16 PM PDT 24
Finished	Apr 20 04:06:21 PM PDT 24
Peak memory	208788 kb
Host	smart-fb0bf9f6-a228-410f-9e6b-df15b2627900
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=949535892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.949535892
Directory	/workspace/14.keymgr_sideload/latest

Test location	/workspace/coverage/default/14.keymgr_sideload_aes.3172074821
Short name	T349
Test name
Test status
Simulation time	2065130242 ps
CPU time	4.72 seconds
Started	Apr 20 04:06:13 PM PDT 24
Finished	Apr 20 04:06:18 PM PDT 24
Peak memory	207904 kb
Host	smart-214e5035-cc35-480c-bd3f-a50ef9e23c48
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172074821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.3172074821
Directory	/workspace/14.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/14.keymgr_sideload_kmac.887781530
Short name	T698
Test name
Test status
Simulation time	926222176 ps
CPU time	7.29 seconds
Started	Apr 20 04:06:17 PM PDT 24
Finished	Apr 20 04:06:24 PM PDT 24
Peak memory	207984 kb
Host	smart-95aa8b36-904c-422e-8f74-e13fa441f1ab
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887781530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.887781530
Directory	/workspace/14.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/14.keymgr_sideload_otbn.383091060
Short name	T839
Test name
Test status
Simulation time	115459094 ps
CPU time	4.18 seconds
Started	Apr 20 04:06:17 PM PDT 24
Finished	Apr 20 04:06:21 PM PDT 24
Peak memory	208708 kb
Host	smart-9f4b395a-535a-4b53-9ca3-fd1be4caf886
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383091060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.383091060
Directory	/workspace/14.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/14.keymgr_sideload_protect.3365848200
Short name	T872
Test name
Test status
Simulation time	87097703 ps
CPU time	2.69 seconds
Started	Apr 20 04:06:16 PM PDT 24
Finished	Apr 20 04:06:19 PM PDT 24
Peak memory	208500 kb
Host	smart-04f0d307-fa0f-4aba-8438-33799314ae6c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3365848200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.3365848200
Directory	/workspace/14.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/14.keymgr_smoke.3173479963
Short name	T862
Test name
Test status
Simulation time	63885456 ps
CPU time	2.83 seconds
Started	Apr 20 04:06:21 PM PDT 24
Finished	Apr 20 04:06:24 PM PDT 24
Peak memory	206816 kb
Host	smart-b010c70c-1684-4e9b-8ce6-084452f333fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3173479963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.3173479963
Directory	/workspace/14.keymgr_smoke/latest

Test location	/workspace/coverage/default/14.keymgr_stress_all.1830066591
Short name	T243
Test name
Test status
Simulation time	1619609919 ps
CPU time	50.72 seconds
Started	Apr 20 04:06:19 PM PDT 24
Finished	Apr 20 04:07:10 PM PDT 24
Peak memory	219024 kb
Host	smart-44d3ed1e-497f-4d3e-8713-30a42d7a7162
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830066591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.1830066591
Directory	/workspace/14.keymgr_stress_all/latest

Test location	/workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.1269740946
Short name	T396
Test name
Test status
Simulation time	358417056 ps
CPU time	7.45 seconds
Started	Apr 20 04:06:18 PM PDT 24
Finished	Apr 20 04:06:26 PM PDT 24
Peak memory	220240 kb
Host	smart-a89b3d6d-b21a-4f77-89b9-3cedbe15e94d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269740946 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.1269740946
Directory	/workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/14.keymgr_sw_invalid_input.2700995138
Short name	T690
Test name
Test status
Simulation time	18561860755 ps
CPU time	67.88 seconds
Started	Apr 20 04:06:20 PM PDT 24
Finished	Apr 20 04:07:28 PM PDT 24
Peak memory	222536 kb
Host	smart-2dd3cc5c-e1f9-4af3-be7c-b50664e5e60f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2700995138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.2700995138
Directory	/workspace/14.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/14.keymgr_sync_async_fault_cross.1447668822
Short name	T686
Test name
Test status
Simulation time	62663544 ps
CPU time	1.92 seconds
Started	Apr 20 04:06:19 PM PDT 24
Finished	Apr 20 04:06:21 PM PDT 24
Peak memory	209768 kb
Host	smart-1ef862d2-188b-45f4-9bf3-6d47a2254189
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1447668822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.1447668822
Directory	/workspace/14.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/15.keymgr_custom_cm.1049181515
Short name	T204
Test name
Test status
Simulation time	118358319 ps
CPU time	2.45 seconds
Started	Apr 20 04:06:23 PM PDT 24
Finished	Apr 20 04:06:26 PM PDT 24
Peak memory	209528 kb
Host	smart-0e70868f-3a1c-4980-81d6-74fe46cc0516
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1049181515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.1049181515
Directory	/workspace/15.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/15.keymgr_direct_to_disabled.2637427275
Short name	T238
Test name
Test status
Simulation time	667033165 ps
CPU time	3.56 seconds
Started	Apr 20 04:06:21 PM PDT 24
Finished	Apr 20 04:06:25 PM PDT 24
Peak memory	207264 kb
Host	smart-7890f143-464c-4132-99ed-a3ea92f940f7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2637427275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.2637427275
Directory	/workspace/15.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/15.keymgr_hwsw_invalid_input.4259014227
Short name	T696
Test name
Test status
Simulation time	585529380 ps
CPU time	12.27 seconds
Started	Apr 20 04:06:21 PM PDT 24
Finished	Apr 20 04:06:34 PM PDT 24
Peak memory	209708 kb
Host	smart-15fff811-49dc-4266-83cb-378ad3e9f611
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4259014227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.4259014227
Directory	/workspace/15.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/15.keymgr_lc_disable.3586053595
Short name	T598
Test name
Test status
Simulation time	118375576 ps
CPU time	3.68 seconds
Started	Apr 20 04:06:20 PM PDT 24
Finished	Apr 20 04:06:24 PM PDT 24
Peak memory	214564 kb
Host	smart-d7fcbce6-b40c-4266-87cf-c63560edf760
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3586053595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.3586053595
Directory	/workspace/15.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/15.keymgr_random.3624729366
Short name	T836
Test name
Test status
Simulation time	200494281 ps
CPU time	7.89 seconds
Started	Apr 20 04:06:20 PM PDT 24
Finished	Apr 20 04:06:28 PM PDT 24
Peak memory	209276 kb
Host	smart-e8dc5026-8a6c-4b78-9300-3af0b42f42a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3624729366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.3624729366
Directory	/workspace/15.keymgr_random/latest

Test location	/workspace/coverage/default/15.keymgr_sideload.2336200892
Short name	T912
Test name
Test status
Simulation time	683916189 ps
CPU time	3.51 seconds
Started	Apr 20 04:06:19 PM PDT 24
Finished	Apr 20 04:06:23 PM PDT 24
Peak memory	208636 kb
Host	smart-bc64f687-81bb-4a7a-95c9-325ff5736688
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2336200892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.2336200892
Directory	/workspace/15.keymgr_sideload/latest

Test location	/workspace/coverage/default/15.keymgr_sideload_kmac.4255586909
Short name	T363
Test name
Test status
Simulation time	104433891 ps
CPU time	2.14 seconds
Started	Apr 20 04:06:19 PM PDT 24
Finished	Apr 20 04:06:22 PM PDT 24
Peak memory	208848 kb
Host	smart-8e30e2d4-32b7-4032-aedf-600b0749035f
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255586909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.4255586909
Directory	/workspace/15.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/15.keymgr_sideload_otbn.3277862967
Short name	T914
Test name
Test status
Simulation time	514703297 ps
CPU time	3.33 seconds
Started	Apr 20 04:06:22 PM PDT 24
Finished	Apr 20 04:06:25 PM PDT 24
Peak memory	208452 kb
Host	smart-3dda6b06-161d-4013-8eef-e0524fb87306
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277862967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.3277862967
Directory	/workspace/15.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/15.keymgr_sideload_protect.2668443943
Short name	T236
Test name
Test status
Simulation time	143679269 ps
CPU time	2.77 seconds
Started	Apr 20 04:06:24 PM PDT 24
Finished	Apr 20 04:06:27 PM PDT 24
Peak memory	210100 kb
Host	smart-1641ff95-e340-4334-946a-db5c8ee4ac0b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2668443943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.2668443943
Directory	/workspace/15.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/15.keymgr_smoke.1130141017
Short name	T832
Test name
Test status
Simulation time	493924244 ps
CPU time	3.44 seconds
Started	Apr 20 04:06:18 PM PDT 24
Finished	Apr 20 04:06:22 PM PDT 24
Peak memory	208036 kb
Host	smart-fd42cbff-279b-4860-bde7-cc25813ea555
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1130141017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.1130141017
Directory	/workspace/15.keymgr_smoke/latest

Test location	/workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.1402242788
Short name	T607
Test name
Test status
Simulation time	413378592 ps
CPU time	5.28 seconds
Started	Apr 20 04:06:23 PM PDT 24
Finished	Apr 20 04:06:29 PM PDT 24
Peak memory	222588 kb
Host	smart-50b12116-7f62-4024-9721-71f88171e02b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402242788 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.1402242788
Directory	/workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/15.keymgr_sw_invalid_input.3520819929
Short name	T868
Test name
Test status
Simulation time	555711976 ps
CPU time	6.09 seconds
Started	Apr 20 04:06:21 PM PDT 24
Finished	Apr 20 04:06:28 PM PDT 24
Peak memory	208996 kb
Host	smart-d20ed6b3-cf3f-4de9-b67c-a88411e83a8c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3520819929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.3520819929
Directory	/workspace/15.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/15.keymgr_sync_async_fault_cross.3469050641
Short name	T778
Test name
Test status
Simulation time	52633872 ps
CPU time	1.36 seconds
Started	Apr 20 04:06:24 PM PDT 24
Finished	Apr 20 04:06:26 PM PDT 24
Peak memory	209892 kb
Host	smart-68b8e3e7-47b5-47fa-b6ad-503cc1b05038
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3469050641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.3469050641
Directory	/workspace/15.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/16.keymgr_alert_test.2343468046
Short name	T617
Test name
Test status
Simulation time	39347718 ps
CPU time	0.93 seconds
Started	Apr 20 04:06:31 PM PDT 24
Finished	Apr 20 04:06:32 PM PDT 24
Peak memory	205864 kb
Host	smart-eea7652c-e0ed-47c8-8b62-56f297c35d2d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343468046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.2343468046
Directory	/workspace/16.keymgr_alert_test/latest

Test location	/workspace/coverage/default/16.keymgr_custom_cm.3815658976
Short name	T66
Test name
Test status
Simulation time	165243128 ps
CPU time	6.82 seconds
Started	Apr 20 04:06:30 PM PDT 24
Finished	Apr 20 04:06:37 PM PDT 24
Peak memory	222788 kb
Host	smart-ad52e99c-80e5-476b-8bdf-d9a380d66925
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3815658976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.3815658976
Directory	/workspace/16.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/16.keymgr_direct_to_disabled.2986990083
Short name	T900
Test name
Test status
Simulation time	156818038 ps
CPU time	2.06 seconds
Started	Apr 20 04:06:28 PM PDT 24
Finished	Apr 20 04:06:31 PM PDT 24
Peak memory	208220 kb
Host	smart-c588e0ab-d266-47dd-b355-00c3a19edbc2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2986990083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.2986990083
Directory	/workspace/16.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/16.keymgr_hwsw_invalid_input.2214264726
Short name	T91
Test name
Test status
Simulation time	162900549 ps
CPU time	5.77 seconds
Started	Apr 20 04:06:27 PM PDT 24
Finished	Apr 20 04:06:34 PM PDT 24
Peak memory	209360 kb
Host	smart-8fb16cf9-90f6-4ee0-a7db-36c1123af90d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2214264726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.2214264726
Directory	/workspace/16.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/16.keymgr_kmac_rsp_err.3559951635
Short name	T295
Test name
Test status
Simulation time	82130950 ps
CPU time	3.35 seconds
Started	Apr 20 04:06:30 PM PDT 24
Finished	Apr 20 04:06:34 PM PDT 24
Peak memory	222376 kb
Host	smart-ab5fdb26-32c7-4605-9764-b60996fddb00
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3559951635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.3559951635
Directory	/workspace/16.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/16.keymgr_lc_disable.2936894143
Short name	T587
Test name
Test status
Simulation time	105318405 ps
CPU time	3.65 seconds
Started	Apr 20 04:06:27 PM PDT 24
Finished	Apr 20 04:06:32 PM PDT 24
Peak memory	208920 kb
Host	smart-96f88782-f9a0-45f9-b9d4-75fd2c2aac1e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2936894143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.2936894143
Directory	/workspace/16.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/16.keymgr_random.2354392093
Short name	T412
Test name
Test status
Simulation time	420438893 ps
CPU time	5.47 seconds
Started	Apr 20 04:06:31 PM PDT 24
Finished	Apr 20 04:06:37 PM PDT 24
Peak memory	209264 kb
Host	smart-b840e0ad-2780-43cc-a2c9-050af33cecec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2354392093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.2354392093
Directory	/workspace/16.keymgr_random/latest

Test location	/workspace/coverage/default/16.keymgr_sideload.3831740173
Short name	T951
Test name
Test status
Simulation time	224343055 ps
CPU time	3.08 seconds
Started	Apr 20 04:06:28 PM PDT 24
Finished	Apr 20 04:06:31 PM PDT 24
Peak memory	206784 kb
Host	smart-20620fd0-5dc1-42f6-8a05-6d9a00f533ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3831740173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.3831740173
Directory	/workspace/16.keymgr_sideload/latest

Test location	/workspace/coverage/default/16.keymgr_sideload_aes.3595779822
Short name	T1063
Test name
Test status
Simulation time	482469269 ps
CPU time	7.38 seconds
Started	Apr 20 04:06:26 PM PDT 24
Finished	Apr 20 04:06:34 PM PDT 24
Peak memory	208820 kb
Host	smart-7f7d6c17-4b5a-4f3b-85ad-fc4e976adda2
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595779822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.3595779822
Directory	/workspace/16.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/16.keymgr_sideload_kmac.884138989
Short name	T945
Test name
Test status
Simulation time	59440624 ps
CPU time	2.98 seconds
Started	Apr 20 04:06:26 PM PDT 24
Finished	Apr 20 04:06:29 PM PDT 24
Peak memory	208264 kb
Host	smart-5dce3bf0-8c95-4866-b79a-45c93fa86bd3
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884138989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.884138989
Directory	/workspace/16.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/16.keymgr_sideload_otbn.3531283510
Short name	T605
Test name
Test status
Simulation time	81581713 ps
CPU time	2.56 seconds
Started	Apr 20 04:06:29 PM PDT 24
Finished	Apr 20 04:06:32 PM PDT 24
Peak memory	206888 kb
Host	smart-e113f50f-b467-4333-8f23-e71b4e62a348
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531283510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.3531283510
Directory	/workspace/16.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/16.keymgr_sideload_protect.1071647500
Short name	T757
Test name
Test status
Simulation time	151565526 ps
CPU time	5.57 seconds
Started	Apr 20 04:06:30 PM PDT 24
Finished	Apr 20 04:06:36 PM PDT 24
Peak memory	207140 kb
Host	smart-e6d17fbb-8dfc-4143-9e71-4b254daa3dd0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1071647500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.1071647500
Directory	/workspace/16.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/16.keymgr_smoke.4068170884
Short name	T929
Test name
Test status
Simulation time	124334678 ps
CPU time	2.31 seconds
Started	Apr 20 04:06:23 PM PDT 24
Finished	Apr 20 04:06:25 PM PDT 24
Peak memory	206840 kb
Host	smart-5d79b2c4-29f8-4372-bb3c-291a76a35f37
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4068170884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.4068170884
Directory	/workspace/16.keymgr_smoke/latest

Test location	/workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.634386400
Short name	T1043
Test name
Test status
Simulation time	211754467 ps
CPU time	7.74 seconds
Started	Apr 20 04:06:31 PM PDT 24
Finished	Apr 20 04:06:39 PM PDT 24
Peak memory	222668 kb
Host	smart-4de2eda9-83ec-46f1-8be5-02d6083b803a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634386400 -assert nopost proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.634386400
Directory	/workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/16.keymgr_sync_async_fault_cross.2096131320
Short name	T926
Test name
Test status
Simulation time	253201868 ps
CPU time	4.73 seconds
Started	Apr 20 04:06:31 PM PDT 24
Finished	Apr 20 04:06:36 PM PDT 24
Peak memory	210292 kb
Host	smart-d98a934e-17f7-4d71-9d81-6636476841de
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2096131320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.2096131320
Directory	/workspace/16.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/17.keymgr_alert_test.2098328699
Short name	T99
Test name
Test status
Simulation time	16229151 ps
CPU time	0.77 seconds
Started	Apr 20 04:06:41 PM PDT 24
Finished	Apr 20 04:06:42 PM PDT 24
Peak memory	205812 kb
Host	smart-3fc2d956-bc37-4726-be63-b4acd990a04e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098328699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.2098328699
Directory	/workspace/17.keymgr_alert_test/latest

Test location	/workspace/coverage/default/17.keymgr_custom_cm.694068643
Short name	T673
Test name
Test status
Simulation time	761603700 ps
CPU time	5.96 seconds
Started	Apr 20 04:06:36 PM PDT 24
Finished	Apr 20 04:06:42 PM PDT 24
Peak memory	218216 kb
Host	smart-8b322c44-d705-4bc6-ad67-6b4917772d76
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=694068643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.694068643
Directory	/workspace/17.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/17.keymgr_direct_to_disabled.3262413841
Short name	T919
Test name
Test status
Simulation time	400783430 ps
CPU time	3.46 seconds
Started	Apr 20 04:06:38 PM PDT 24
Finished	Apr 20 04:06:42 PM PDT 24
Peak memory	218196 kb
Host	smart-c6863472-9ec9-462b-bb82-1b5ca9d22335
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3262413841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.3262413841
Directory	/workspace/17.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/17.keymgr_kmac_rsp_err.1859706218
Short name	T885
Test name
Test status
Simulation time	2436982230 ps
CPU time	46.69 seconds
Started	Apr 20 04:06:37 PM PDT 24
Finished	Apr 20 04:07:24 PM PDT 24
Peak memory	222504 kb
Host	smart-53ba3ca7-8d9e-4feb-b832-7c7ef59f1dfc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1859706218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.1859706218
Directory	/workspace/17.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/17.keymgr_lc_disable.2666951380
Short name	T810
Test name
Test status
Simulation time	90789530 ps
CPU time	3.97 seconds
Started	Apr 20 04:06:36 PM PDT 24
Finished	Apr 20 04:06:41 PM PDT 24
Peak memory	219852 kb
Host	smart-d50427ea-befa-4e65-b5b6-3b0549366723
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2666951380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.2666951380
Directory	/workspace/17.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/17.keymgr_random.846533396
Short name	T740
Test name
Test status
Simulation time	2027374450 ps
CPU time	50.08 seconds
Started	Apr 20 04:06:37 PM PDT 24
Finished	Apr 20 04:07:27 PM PDT 24
Peak memory	218384 kb
Host	smart-61582679-de11-4401-a4eb-acf3c02aee41
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=846533396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.846533396
Directory	/workspace/17.keymgr_random/latest

Test location	/workspace/coverage/default/17.keymgr_sideload.2063908626
Short name	T711
Test name
Test status
Simulation time	7168598070 ps
CPU time	54.66 seconds
Started	Apr 20 04:06:29 PM PDT 24
Finished	Apr 20 04:07:24 PM PDT 24
Peak memory	208796 kb
Host	smart-12543035-b9bd-4705-bd97-1ccb86ec67ce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2063908626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.2063908626
Directory	/workspace/17.keymgr_sideload/latest

Test location	/workspace/coverage/default/17.keymgr_sideload_aes.3130029698
Short name	T666
Test name
Test status
Simulation time	93001352 ps
CPU time	4.06 seconds
Started	Apr 20 04:06:38 PM PDT 24
Finished	Apr 20 04:06:43 PM PDT 24
Peak memory	208668 kb
Host	smart-38eb0301-80c5-4ebf-8aee-fdbc8eb3668e
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130029698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.3130029698
Directory	/workspace/17.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/17.keymgr_sideload_kmac.2004696743
Short name	T111
Test name
Test status
Simulation time	360916828 ps
CPU time	7.89 seconds
Started	Apr 20 04:06:38 PM PDT 24
Finished	Apr 20 04:06:47 PM PDT 24
Peak memory	208632 kb
Host	smart-06d5f691-e9df-4252-a529-aea06e3a4328
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004696743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.2004696743
Directory	/workspace/17.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/17.keymgr_sideload_otbn.3707663765
Short name	T302
Test name
Test status
Simulation time	43838970 ps
CPU time	2.83 seconds
Started	Apr 20 04:06:38 PM PDT 24
Finished	Apr 20 04:06:41 PM PDT 24
Peak memory	209192 kb
Host	smart-66a9e63a-480b-47a8-88ac-97fbac27174d
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707663765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.3707663765
Directory	/workspace/17.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/17.keymgr_sideload_protect.368112094
Short name	T938
Test name
Test status
Simulation time	304601291 ps
CPU time	2.32 seconds
Started	Apr 20 04:06:38 PM PDT 24
Finished	Apr 20 04:06:40 PM PDT 24
Peak memory	218256 kb
Host	smart-12b4c25f-0479-44b5-aa2c-e24023172357
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=368112094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.368112094
Directory	/workspace/17.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/17.keymgr_smoke.2069145843
Short name	T392
Test name
Test status
Simulation time	100556735 ps
CPU time	2.88 seconds
Started	Apr 20 04:06:29 PM PDT 24
Finished	Apr 20 04:06:33 PM PDT 24
Peak memory	206796 kb
Host	smart-d58f3f9b-aa22-438e-8fc3-166896a399c7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2069145843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.2069145843
Directory	/workspace/17.keymgr_smoke/latest

Test location	/workspace/coverage/default/17.keymgr_stress_all.1500645692
Short name	T250
Test name
Test status
Simulation time	640979424 ps
CPU time	23.94 seconds
Started	Apr 20 04:06:38 PM PDT 24
Finished	Apr 20 04:07:02 PM PDT 24
Peak memory	215008 kb
Host	smart-f7ab6852-9137-4c7a-bf5b-7f9293f0d205
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500645692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.1500645692
Directory	/workspace/17.keymgr_stress_all/latest

Test location	/workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.290541288
Short name	T834
Test name
Test status
Simulation time	234426083 ps
CPU time	3.37 seconds
Started	Apr 20 04:06:41 PM PDT 24
Finished	Apr 20 04:06:45 PM PDT 24
Peak memory	217428 kb
Host	smart-58de085e-82dd-4a1c-bf44-c70582566a67
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290541288 -assert nopost proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.290541288
Directory	/workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/17.keymgr_sw_invalid_input.3926893508
Short name	T306
Test name
Test status
Simulation time	324335635 ps
CPU time	4.4 seconds
Started	Apr 20 04:06:39 PM PDT 24
Finished	Apr 20 04:06:44 PM PDT 24
Peak memory	206800 kb
Host	smart-3082c7cc-7e09-455b-bb2c-a3d93fd30855
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3926893508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.3926893508
Directory	/workspace/17.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/18.keymgr_alert_test.863762700
Short name	T612
Test name
Test status
Simulation time	56846107 ps
CPU time	0.86 seconds
Started	Apr 20 04:06:47 PM PDT 24
Finished	Apr 20 04:06:48 PM PDT 24
Peak memory	205848 kb
Host	smart-22ec85a7-3b1d-4683-9065-61ae0b063a1d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863762700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.863762700
Directory	/workspace/18.keymgr_alert_test/latest

Test location	/workspace/coverage/default/18.keymgr_cfg_regwen.2543085652
Short name	T993
Test name
Test status
Simulation time	113207934 ps
CPU time	4.58 seconds
Started	Apr 20 04:06:38 PM PDT 24
Finished	Apr 20 04:06:44 PM PDT 24
Peak memory	214252 kb
Host	smart-dbe0b206-2ea1-4492-a332-0c3d85a49a98
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2543085652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.2543085652
Directory	/workspace/18.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/18.keymgr_direct_to_disabled.2572682732
Short name	T901
Test name
Test status
Simulation time	50709633 ps
CPU time	1.53 seconds
Started	Apr 20 04:06:42 PM PDT 24
Finished	Apr 20 04:06:44 PM PDT 24
Peak memory	209052 kb
Host	smart-bf6cbf2d-ec42-4b93-8c37-c69aaba16471
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2572682732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.2572682732
Directory	/workspace/18.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/18.keymgr_hwsw_invalid_input.851461166
Short name	T838
Test name
Test status
Simulation time	40190775 ps
CPU time	2.77 seconds
Started	Apr 20 04:06:45 PM PDT 24
Finished	Apr 20 04:06:48 PM PDT 24
Peak memory	214276 kb
Host	smart-079ab607-e284-43a1-9706-867d29f39a1b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=851461166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.851461166
Directory	/workspace/18.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/18.keymgr_lc_disable.2459717221
Short name	T214
Test name
Test status
Simulation time	86629724 ps
CPU time	3.84 seconds
Started	Apr 20 04:06:43 PM PDT 24
Finished	Apr 20 04:06:47 PM PDT 24
Peak memory	220240 kb
Host	smart-615153bb-79f0-4444-8cfe-09e903d0acd5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2459717221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.2459717221
Directory	/workspace/18.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/18.keymgr_random.3979553517
Short name	T726
Test name
Test status
Simulation time	197526572 ps
CPU time	6.32 seconds
Started	Apr 20 04:06:40 PM PDT 24
Finished	Apr 20 04:06:46 PM PDT 24
Peak memory	218176 kb
Host	smart-430e88d4-f7ee-41ed-8d25-7e414deb3e66
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3979553517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.3979553517
Directory	/workspace/18.keymgr_random/latest

Test location	/workspace/coverage/default/18.keymgr_sideload.1007378861
Short name	T990
Test name
Test status
Simulation time	567291664 ps
CPU time	4.65 seconds
Started	Apr 20 04:06:41 PM PDT 24
Finished	Apr 20 04:06:45 PM PDT 24
Peak memory	208468 kb
Host	smart-3807c743-6118-46f2-ab9d-6d7370e01761
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1007378861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.1007378861
Directory	/workspace/18.keymgr_sideload/latest

Test location	/workspace/coverage/default/18.keymgr_sideload_aes.1421557578
Short name	T744
Test name
Test status
Simulation time	2051195275 ps
CPU time	18.02 seconds
Started	Apr 20 04:06:40 PM PDT 24
Finished	Apr 20 04:06:59 PM PDT 24
Peak memory	208340 kb
Host	smart-7e25b9bb-79bf-4bf7-85b2-48948e6076d5
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421557578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.1421557578
Directory	/workspace/18.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/18.keymgr_sideload_kmac.1761689663
Short name	T1010
Test name
Test status
Simulation time	149837513 ps
CPU time	4.45 seconds
Started	Apr 20 04:06:41 PM PDT 24
Finished	Apr 20 04:06:46 PM PDT 24
Peak memory	206936 kb
Host	smart-1ef247a8-02c1-460d-8fe1-d0ae44b27c3d
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761689663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.1761689663
Directory	/workspace/18.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/18.keymgr_sideload_otbn.1833679850
Short name	T246
Test name
Test status
Simulation time	24996840 ps
CPU time	1.89 seconds
Started	Apr 20 04:06:41 PM PDT 24
Finished	Apr 20 04:06:43 PM PDT 24
Peak memory	206820 kb
Host	smart-d6b977c7-48b6-49c5-b984-0b41ba3d79d3
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833679850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.1833679850
Directory	/workspace/18.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/18.keymgr_sideload_protect.19910924
Short name	T389
Test name
Test status
Simulation time	73414304 ps
CPU time	3.2 seconds
Started	Apr 20 04:06:43 PM PDT 24
Finished	Apr 20 04:06:46 PM PDT 24
Peak memory	208016 kb
Host	smart-56c36646-d147-4098-a18c-aa3db14bbb3b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=19910924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.19910924
Directory	/workspace/18.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/18.keymgr_smoke.1539513941
Short name	T766
Test name
Test status
Simulation time	184970391 ps
CPU time	2.63 seconds
Started	Apr 20 04:06:41 PM PDT 24
Finished	Apr 20 04:06:44 PM PDT 24
Peak memory	206744 kb
Host	smart-e99cd11e-8555-417f-bd84-65f43fe68f15
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1539513941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.1539513941
Directory	/workspace/18.keymgr_smoke/latest

Test location	/workspace/coverage/default/18.keymgr_stress_all.902758458
Short name	T1029
Test name
Test status
Simulation time	162142799 ps
CPU time	2.92 seconds
Started	Apr 20 04:06:45 PM PDT 24
Finished	Apr 20 04:06:48 PM PDT 24
Peak memory	207348 kb
Host	smart-fe1c57c3-4099-4cc1-8b48-b3799a04cd1f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902758458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.902758458
Directory	/workspace/18.keymgr_stress_all/latest

Test location	/workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.1071544511
Short name	T50
Test name
Test status
Simulation time	306680755 ps
CPU time	5.29 seconds
Started	Apr 20 04:06:43 PM PDT 24
Finished	Apr 20 04:06:48 PM PDT 24
Peak memory	222468 kb
Host	smart-6c346a4c-551d-4c93-ae54-013209ce7c80
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071544511 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.1071544511
Directory	/workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/18.keymgr_sw_invalid_input.1475038274
Short name	T636
Test name
Test status
Simulation time	91509079 ps
CPU time	4.36 seconds
Started	Apr 20 04:06:45 PM PDT 24
Finished	Apr 20 04:06:50 PM PDT 24
Peak memory	208872 kb
Host	smart-cfb5bb4f-a0d8-4d2d-86ff-b9a664233067
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1475038274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.1475038274
Directory	/workspace/18.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/18.keymgr_sync_async_fault_cross.717088878
Short name	T736
Test name
Test status
Simulation time	80322953 ps
CPU time	1.67 seconds
Started	Apr 20 04:06:43 PM PDT 24
Finished	Apr 20 04:06:45 PM PDT 24
Peak memory	210020 kb
Host	smart-2b11a60c-2b93-494c-99bf-74f3ea9184b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=717088878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.717088878
Directory	/workspace/18.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/19.keymgr_alert_test.218866684
Short name	T721
Test name
Test status
Simulation time	13041442 ps
CPU time	0.88 seconds
Started	Apr 20 04:06:49 PM PDT 24
Finished	Apr 20 04:06:50 PM PDT 24
Peak memory	205852 kb
Host	smart-8f96900c-38e3-457c-9068-d321c6cebf9c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218866684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.218866684
Directory	/workspace/19.keymgr_alert_test/latest

Test location	/workspace/coverage/default/19.keymgr_custom_cm.4161218158
Short name	T935
Test name
Test status
Simulation time	2031533188 ps
CPU time	15.75 seconds
Started	Apr 20 04:06:51 PM PDT 24
Finished	Apr 20 04:07:07 PM PDT 24
Peak memory	214596 kb
Host	smart-2fe28cbf-e058-468a-afa1-736ffa38d0b2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4161218158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.4161218158
Directory	/workspace/19.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/19.keymgr_direct_to_disabled.2557502645
Short name	T781
Test name
Test status
Simulation time	220184851 ps
CPU time	3.86 seconds
Started	Apr 20 04:06:52 PM PDT 24
Finished	Apr 20 04:06:56 PM PDT 24
Peak memory	209780 kb
Host	smart-0138cbe2-62d0-4400-879a-8a0e9e667d6c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2557502645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.2557502645
Directory	/workspace/19.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/19.keymgr_hwsw_invalid_input.1168349694
Short name	T86
Test name
Test status
Simulation time	105009952 ps
CPU time	4.49 seconds
Started	Apr 20 04:06:50 PM PDT 24
Finished	Apr 20 04:06:55 PM PDT 24
Peak memory	220392 kb
Host	smart-cf1602a3-a9fa-4467-b984-89bd2155f815
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1168349694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.1168349694
Directory	/workspace/19.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/19.keymgr_kmac_rsp_err.2027049618
Short name	T255
Test name
Test status
Simulation time	287999720 ps
CPU time	5.69 seconds
Started	Apr 20 04:06:51 PM PDT 24
Finished	Apr 20 04:06:57 PM PDT 24
Peak memory	214256 kb
Host	smart-f9dbba7e-dd62-46ff-8daa-7913974c90b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2027049618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.2027049618
Directory	/workspace/19.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/19.keymgr_lc_disable.3122055114
Short name	T592
Test name
Test status
Simulation time	94221982 ps
CPU time	3.24 seconds
Started	Apr 20 04:06:50 PM PDT 24
Finished	Apr 20 04:06:54 PM PDT 24
Peak memory	219156 kb
Host	smart-ac1ab7ee-223f-436f-a921-e39f1b8283fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3122055114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.3122055114
Directory	/workspace/19.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/19.keymgr_random.428006932
Short name	T632
Test name
Test status
Simulation time	50704341 ps
CPU time	2.96 seconds
Started	Apr 20 04:06:52 PM PDT 24
Finished	Apr 20 04:06:55 PM PDT 24
Peak memory	209708 kb
Host	smart-851183aa-fd48-4c39-896a-620de73b271b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=428006932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.428006932
Directory	/workspace/19.keymgr_random/latest

Test location	/workspace/coverage/default/19.keymgr_sideload.978342244
Short name	T941
Test name
Test status
Simulation time	206744570 ps
CPU time	6.99 seconds
Started	Apr 20 04:06:52 PM PDT 24
Finished	Apr 20 04:07:00 PM PDT 24
Peak memory	207984 kb
Host	smart-65fafe14-9703-4661-9c6d-0a2a962d8311
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=978342244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.978342244
Directory	/workspace/19.keymgr_sideload/latest

Test location	/workspace/coverage/default/19.keymgr_sideload_aes.225232765
Short name	T783
Test name
Test status
Simulation time	98826283 ps
CPU time	2.83 seconds
Started	Apr 20 04:06:47 PM PDT 24
Finished	Apr 20 04:06:50 PM PDT 24
Peak memory	206856 kb
Host	smart-322eabaa-2e42-471f-8b5c-71a7291173d8
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225232765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.225232765
Directory	/workspace/19.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/19.keymgr_sideload_kmac.714742728
Short name	T844
Test name
Test status
Simulation time	88667678 ps
CPU time	2 seconds
Started	Apr 20 04:06:48 PM PDT 24
Finished	Apr 20 04:06:50 PM PDT 24
Peak memory	206856 kb
Host	smart-fb9d015e-0bcc-4598-acf6-4ee2bdbd84aa
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714742728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.714742728
Directory	/workspace/19.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/19.keymgr_sideload_otbn.2305664433
Short name	T5
Test name
Test status
Simulation time	1037178877 ps
CPU time	10.97 seconds
Started	Apr 20 04:06:48 PM PDT 24
Finished	Apr 20 04:06:59 PM PDT 24
Peak memory	208744 kb
Host	smart-fa4f6b43-4273-4088-a34e-375a6a72a8aa
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305664433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.2305664433
Directory	/workspace/19.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/19.keymgr_sideload_protect.2615889042
Short name	T187
Test name
Test status
Simulation time	807361195 ps
CPU time	6.31 seconds
Started	Apr 20 04:06:50 PM PDT 24
Finished	Apr 20 04:06:57 PM PDT 24
Peak memory	209592 kb
Host	smart-8f37e555-1554-4676-b05e-57a812e4f032
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2615889042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.2615889042
Directory	/workspace/19.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/19.keymgr_smoke.715192626
Short name	T841
Test name
Test status
Simulation time	295893415 ps
CPU time	4.1 seconds
Started	Apr 20 04:06:47 PM PDT 24
Finished	Apr 20 04:06:52 PM PDT 24
Peak memory	208392 kb
Host	smart-d817c582-8519-4e0a-81a2-2ebffcbfe413
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=715192626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.715192626
Directory	/workspace/19.keymgr_smoke/latest

Test location	/workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.3230118315
Short name	T298
Test name
Test status
Simulation time	70256898 ps
CPU time	4.39 seconds
Started	Apr 20 04:06:55 PM PDT 24
Finished	Apr 20 04:07:00 PM PDT 24
Peak memory	219548 kb
Host	smart-babc8551-78ea-4487-bc1f-effd1ffb8f29
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230118315 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.3230118315
Directory	/workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/19.keymgr_sw_invalid_input.3409090995
Short name	T780
Test name
Test status
Simulation time	8280865547 ps
CPU time	60.64 seconds
Started	Apr 20 04:06:51 PM PDT 24
Finished	Apr 20 04:07:52 PM PDT 24
Peak memory	214376 kb
Host	smart-b916db72-2fd2-4450-b2d9-4b5a284364c9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3409090995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.3409090995
Directory	/workspace/19.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/19.keymgr_sync_async_fault_cross.2808067650
Short name	T644
Test name
Test status
Simulation time	1313804710 ps
CPU time	19.33 seconds
Started	Apr 20 04:06:49 PM PDT 24
Finished	Apr 20 04:07:08 PM PDT 24
Peak memory	210484 kb
Host	smart-d9039ab5-a427-4a1d-8087-d87bd6b1e9d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2808067650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.2808067650
Directory	/workspace/19.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/2.keymgr_alert_test.1211375479
Short name	T17
Test name
Test status
Simulation time	26768498 ps
CPU time	0.79 seconds
Started	Apr 20 04:04:46 PM PDT 24
Finished	Apr 20 04:04:47 PM PDT 24
Peak memory	205788 kb
Host	smart-48ff60ef-47c4-468d-b2af-d2df96f0ef51
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211375479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.1211375479
Directory	/workspace/2.keymgr_alert_test/latest

Test location	/workspace/coverage/default/2.keymgr_custom_cm.467566061
Short name	T31
Test name
Test status
Simulation time	152456106 ps
CPU time	3.82 seconds
Started	Apr 20 04:04:43 PM PDT 24
Finished	Apr 20 04:04:47 PM PDT 24
Peak memory	208804 kb
Host	smart-02bb2385-714e-4ea0-91d0-dbedd18dd745
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=467566061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.467566061
Directory	/workspace/2.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/2.keymgr_direct_to_disabled.2288997397
Short name	T53
Test name
Test status
Simulation time	113573106 ps
CPU time	2.09 seconds
Started	Apr 20 04:04:40 PM PDT 24
Finished	Apr 20 04:04:43 PM PDT 24
Peak memory	207580 kb
Host	smart-8c207e87-8ae4-4708-894b-e01bc717402e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2288997397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.2288997397
Directory	/workspace/2.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/2.keymgr_hwsw_invalid_input.2916710509
Short name	T96
Test name
Test status
Simulation time	36854546 ps
CPU time	2.76 seconds
Started	Apr 20 04:04:43 PM PDT 24
Finished	Apr 20 04:04:46 PM PDT 24
Peak memory	208596 kb
Host	smart-cf46be34-7bb0-45f9-ad6a-d4000dda054d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2916710509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.2916710509
Directory	/workspace/2.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/2.keymgr_random.2665109543
Short name	T78
Test name
Test status
Simulation time	2035329591 ps
CPU time	53.6 seconds
Started	Apr 20 04:04:40 PM PDT 24
Finished	Apr 20 04:05:34 PM PDT 24
Peak memory	210192 kb
Host	smart-b6e3742f-33c4-4b68-99f3-d2b4ccaff9f4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2665109543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.2665109543
Directory	/workspace/2.keymgr_random/latest

Test location	/workspace/coverage/default/2.keymgr_sec_cm.2464574020
Short name	T12
Test name
Test status
Simulation time	1137010030 ps
CPU time	18.39 seconds
Started	Apr 20 04:04:46 PM PDT 24
Finished	Apr 20 04:05:05 PM PDT 24
Peak memory	239856 kb
Host	smart-8e0cf9a5-35ac-43f0-84b7-772f1c31fe15
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464574020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.2464574020
Directory	/workspace/2.keymgr_sec_cm/latest

Test location	/workspace/coverage/default/2.keymgr_sideload.206978411
Short name	T1032
Test name
Test status
Simulation time	1047681204 ps
CPU time	8.62 seconds
Started	Apr 20 04:04:37 PM PDT 24
Finished	Apr 20 04:04:46 PM PDT 24
Peak memory	208632 kb
Host	smart-1d30d27a-7daf-410a-93eb-940a7117e0eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=206978411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.206978411
Directory	/workspace/2.keymgr_sideload/latest

Test location	/workspace/coverage/default/2.keymgr_sideload_aes.1299847484
Short name	T856
Test name
Test status
Simulation time	36792818 ps
CPU time	2.42 seconds
Started	Apr 20 04:04:39 PM PDT 24
Finished	Apr 20 04:04:42 PM PDT 24
Peak memory	206896 kb
Host	smart-7a0eb811-d22f-429f-b23c-02e0d4677839
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299847484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.1299847484
Directory	/workspace/2.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/2.keymgr_sideload_kmac.2033872069
Short name	T197
Test name
Test status
Simulation time	132160094 ps
CPU time	2.41 seconds
Started	Apr 20 04:04:38 PM PDT 24
Finished	Apr 20 04:04:41 PM PDT 24
Peak memory	207432 kb
Host	smart-91692cca-79bd-47da-b22c-681f01c81af1
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033872069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.2033872069
Directory	/workspace/2.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/2.keymgr_sideload_otbn.2151874289
Short name	T958
Test name
Test status
Simulation time	534494474 ps
CPU time	5.41 seconds
Started	Apr 20 04:04:42 PM PDT 24
Finished	Apr 20 04:04:47 PM PDT 24
Peak memory	208372 kb
Host	smart-afcbb9c1-b752-409d-bd7f-3876f9b64266
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151874289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.2151874289
Directory	/workspace/2.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/2.keymgr_sideload_protect.3649632434
Short name	T681
Test name
Test status
Simulation time	41649037 ps
CPU time	1.8 seconds
Started	Apr 20 04:04:48 PM PDT 24
Finished	Apr 20 04:04:51 PM PDT 24
Peak memory	207948 kb
Host	smart-3677b879-db6f-40f4-a3f5-5d299ce34740
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3649632434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.3649632434
Directory	/workspace/2.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/2.keymgr_smoke.1451304889
Short name	T739
Test name
Test status
Simulation time	2194522183 ps
CPU time	9.47 seconds
Started	Apr 20 04:04:39 PM PDT 24
Finished	Apr 20 04:04:49 PM PDT 24
Peak memory	208424 kb
Host	smart-8b7ac0bf-7034-40e3-b37b-d669041954ed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1451304889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.1451304889
Directory	/workspace/2.keymgr_smoke/latest

Test location	/workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.3461429069
Short name	T980
Test name
Test status
Simulation time	1419440501 ps
CPU time	12.71 seconds
Started	Apr 20 04:04:48 PM PDT 24
Finished	Apr 20 04:05:02 PM PDT 24
Peak memory	222528 kb
Host	smart-c59a2051-8688-4a3c-a6b2-4dc3f346c150
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461429069 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.3461429069
Directory	/workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/2.keymgr_sw_invalid_input.1936770309
Short name	T796
Test name
Test status
Simulation time	584706750 ps
CPU time	3.89 seconds
Started	Apr 20 04:04:45 PM PDT 24
Finished	Apr 20 04:04:49 PM PDT 24
Peak memory	209748 kb
Host	smart-cc780a25-f766-4a32-89b7-8feba39c794b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1936770309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.1936770309
Directory	/workspace/2.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/20.keymgr_alert_test.2194087605
Short name	T571
Test name
Test status
Simulation time	109204322 ps
CPU time	0.8 seconds
Started	Apr 20 04:06:58 PM PDT 24
Finished	Apr 20 04:07:00 PM PDT 24
Peak memory	205848 kb
Host	smart-5d300541-5a08-4aa8-93bc-7958b1b6510f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194087605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.2194087605
Directory	/workspace/20.keymgr_alert_test/latest

Test location	/workspace/coverage/default/20.keymgr_cfg_regwen.647177283
Short name	T420
Test name
Test status
Simulation time	520975993 ps
CPU time	7.87 seconds
Started	Apr 20 04:06:56 PM PDT 24
Finished	Apr 20 04:07:04 PM PDT 24
Peak memory	214328 kb
Host	smart-30d655f3-423a-471d-b64d-68d979bdc263
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=647177283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.647177283
Directory	/workspace/20.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/20.keymgr_direct_to_disabled.3362426886
Short name	T651
Test name
Test status
Simulation time	72478136 ps
CPU time	1.68 seconds
Started	Apr 20 04:06:58 PM PDT 24
Finished	Apr 20 04:07:00 PM PDT 24
Peak memory	207240 kb
Host	smart-43f56cd5-4de0-407d-a0d2-527826a3493d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3362426886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.3362426886
Directory	/workspace/20.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/20.keymgr_hwsw_invalid_input.3673020434
Short name	T731
Test name
Test status
Simulation time	1134253552 ps
CPU time	6.25 seconds
Started	Apr 20 04:06:54 PM PDT 24
Finished	Apr 20 04:07:01 PM PDT 24
Peak memory	216368 kb
Host	smart-8a08b7bf-7b0a-4dd3-b4b7-9c1a8399eca2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3673020434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.3673020434
Directory	/workspace/20.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/20.keymgr_kmac_rsp_err.4029415795
Short name	T712
Test name
Test status
Simulation time	2465222834 ps
CPU time	9.39 seconds
Started	Apr 20 04:06:54 PM PDT 24
Finished	Apr 20 04:07:04 PM PDT 24
Peak memory	222528 kb
Host	smart-e415bd26-baec-42cb-8fc8-5b5043a3e31a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4029415795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.4029415795
Directory	/workspace/20.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/20.keymgr_lc_disable.3457854143
Short name	T904
Test name
Test status
Simulation time	142506128 ps
CPU time	4.11 seconds
Started	Apr 20 04:06:58 PM PDT 24
Finished	Apr 20 04:07:02 PM PDT 24
Peak memory	222488 kb
Host	smart-910f3d1d-fede-4698-80ff-b4498037734c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3457854143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.3457854143
Directory	/workspace/20.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/20.keymgr_random.1677943595
Short name	T398
Test name
Test status
Simulation time	3432410850 ps
CPU time	5.55 seconds
Started	Apr 20 04:06:55 PM PDT 24
Finished	Apr 20 04:07:01 PM PDT 24
Peak memory	207196 kb
Host	smart-f6606f00-6ecc-4052-a7b5-70005c3348a2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1677943595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.1677943595
Directory	/workspace/20.keymgr_random/latest

Test location	/workspace/coverage/default/20.keymgr_sideload.3396824424
Short name	T669
Test name
Test status
Simulation time	78195554 ps
CPU time	3.64 seconds
Started	Apr 20 04:06:53 PM PDT 24
Finished	Apr 20 04:06:57 PM PDT 24
Peak memory	208024 kb
Host	smart-1a2290f2-59b6-40bb-b366-37a6878d42e5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3396824424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.3396824424
Directory	/workspace/20.keymgr_sideload/latest

Test location	/workspace/coverage/default/20.keymgr_sideload_aes.304157917
Short name	T683
Test name
Test status
Simulation time	258209907 ps
CPU time	4.56 seconds
Started	Apr 20 04:06:54 PM PDT 24
Finished	Apr 20 04:06:59 PM PDT 24
Peak memory	206872 kb
Host	smart-2b4cd3da-a179-477e-b5c3-a8a1ceb20567
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304157917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.304157917
Directory	/workspace/20.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/20.keymgr_sideload_kmac.137587466
Short name	T805
Test name
Test status
Simulation time	1203040141 ps
CPU time	9.18 seconds
Started	Apr 20 04:07:01 PM PDT 24
Finished	Apr 20 04:07:10 PM PDT 24
Peak memory	208556 kb
Host	smart-e9eff42e-868a-41f8-a49d-86f88f60e205
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137587466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.137587466
Directory	/workspace/20.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/20.keymgr_sideload_otbn.849779305
Short name	T801
Test name
Test status
Simulation time	420214327 ps
CPU time	9.12 seconds
Started	Apr 20 04:06:53 PM PDT 24
Finished	Apr 20 04:07:03 PM PDT 24
Peak memory	208832 kb
Host	smart-d23ea440-3ee5-40e3-a95a-db5808b06a0d
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849779305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.849779305
Directory	/workspace/20.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/20.keymgr_sideload_protect.3691657728
Short name	T677
Test name
Test status
Simulation time	302272162 ps
CPU time	6.15 seconds
Started	Apr 20 04:06:56 PM PDT 24
Finished	Apr 20 04:07:03 PM PDT 24
Peak memory	208372 kb
Host	smart-4d77d691-5e74-4a4b-b4bf-ac21410471c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3691657728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.3691657728
Directory	/workspace/20.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/20.keymgr_smoke.2260609903
Short name	T815
Test name
Test status
Simulation time	3886391363 ps
CPU time	71.47 seconds
Started	Apr 20 04:06:57 PM PDT 24
Finished	Apr 20 04:08:09 PM PDT 24
Peak memory	208064 kb
Host	smart-a5e40a71-9bf0-46c3-92b9-f2a9d95b9ad9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2260609903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.2260609903
Directory	/workspace/20.keymgr_smoke/latest

Test location	/workspace/coverage/default/20.keymgr_stress_all.1361440985
Short name	T73
Test name
Test status
Simulation time	5831499626 ps
CPU time	34.17 seconds
Started	Apr 20 04:06:58 PM PDT 24
Finished	Apr 20 04:07:33 PM PDT 24
Peak memory	216288 kb
Host	smart-b06aaf29-4731-441d-8e48-b446ffec5127
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361440985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.1361440985
Directory	/workspace/20.keymgr_stress_all/latest

Test location	/workspace/coverage/default/20.keymgr_sw_invalid_input.3906506255
Short name	T1013
Test name
Test status
Simulation time	965760892 ps
CPU time	5.27 seconds
Started	Apr 20 04:06:54 PM PDT 24
Finished	Apr 20 04:07:00 PM PDT 24
Peak memory	207692 kb
Host	smart-71f07424-09c9-4cad-a9fa-756d27378681
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3906506255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.3906506255
Directory	/workspace/20.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/20.keymgr_sync_async_fault_cross.1200634367
Short name	T578
Test name
Test status
Simulation time	68046917 ps
CPU time	2.71 seconds
Started	Apr 20 04:06:57 PM PDT 24
Finished	Apr 20 04:07:00 PM PDT 24
Peak memory	214396 kb
Host	smart-01ab624c-9bcd-4412-bded-3307f8e51e39
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1200634367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.1200634367
Directory	/workspace/20.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/21.keymgr_alert_test.1077642664
Short name	T77
Test name
Test status
Simulation time	46945407 ps
CPU time	0.83 seconds
Started	Apr 20 04:07:04 PM PDT 24
Finished	Apr 20 04:07:05 PM PDT 24
Peak memory	205848 kb
Host	smart-822e7a67-046f-4fee-9a55-e71a0008d23c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077642664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.1077642664
Directory	/workspace/21.keymgr_alert_test/latest

Test location	/workspace/coverage/default/21.keymgr_cfg_regwen.3558934291
Short name	T406
Test name
Test status
Simulation time	208233093 ps
CPU time	4.25 seconds
Started	Apr 20 04:06:59 PM PDT 24
Finished	Apr 20 04:07:03 PM PDT 24
Peak memory	215124 kb
Host	smart-e76c4009-5141-4f3e-a25b-00c8ebaf5e0a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3558934291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.3558934291
Directory	/workspace/21.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/21.keymgr_custom_cm.185818244
Short name	T35
Test name
Test status
Simulation time	88054125 ps
CPU time	4.64 seconds
Started	Apr 20 04:07:04 PM PDT 24
Finished	Apr 20 04:07:09 PM PDT 24
Peak memory	220788 kb
Host	smart-cc5ba3b0-95c9-4cd5-acfa-3590e464c806
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=185818244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.185818244
Directory	/workspace/21.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/21.keymgr_direct_to_disabled.2862557289
Short name	T52
Test name
Test status
Simulation time	268919477 ps
CPU time	5.25 seconds
Started	Apr 20 04:06:58 PM PDT 24
Finished	Apr 20 04:07:04 PM PDT 24
Peak memory	214324 kb
Host	smart-64b704fc-4981-4524-9ef3-9c257b1ca21a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2862557289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.2862557289
Directory	/workspace/21.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/21.keymgr_hwsw_invalid_input.3198434786
Short name	T24
Test name
Test status
Simulation time	163365430 ps
CPU time	6.69 seconds
Started	Apr 20 04:07:00 PM PDT 24
Finished	Apr 20 04:07:07 PM PDT 24
Peak memory	208432 kb
Host	smart-288318d7-8436-48e8-ac30-3dfb31da1ee7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3198434786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.3198434786
Directory	/workspace/21.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/21.keymgr_lc_disable.2043978633
Short name	T57
Test name
Test status
Simulation time	2487364353 ps
CPU time	6.01 seconds
Started	Apr 20 04:06:58 PM PDT 24
Finished	Apr 20 04:07:04 PM PDT 24
Peak memory	210404 kb
Host	smart-42d22fd8-cbc4-48d8-ba74-ae845f32d4c4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2043978633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.2043978633
Directory	/workspace/21.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/21.keymgr_random.1228866271
Short name	T307
Test name
Test status
Simulation time	182289133 ps
CPU time	4.04 seconds
Started	Apr 20 04:06:58 PM PDT 24
Finished	Apr 20 04:07:03 PM PDT 24
Peak memory	218308 kb
Host	smart-8b4d38fe-a4d8-4727-904e-6aa7bf089a54
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1228866271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.1228866271
Directory	/workspace/21.keymgr_random/latest

Test location	/workspace/coverage/default/21.keymgr_sideload.275607240
Short name	T317
Test name
Test status
Simulation time	37531943 ps
CPU time	2.45 seconds
Started	Apr 20 04:06:57 PM PDT 24
Finished	Apr 20 04:07:00 PM PDT 24
Peak memory	207508 kb
Host	smart-d4188ce1-3b37-4fac-a444-663f84a80564
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=275607240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.275607240
Directory	/workspace/21.keymgr_sideload/latest

Test location	/workspace/coverage/default/21.keymgr_sideload_aes.4078408986
Short name	T196
Test name
Test status
Simulation time	1684448880 ps
CPU time	39.99 seconds
Started	Apr 20 04:06:59 PM PDT 24
Finished	Apr 20 04:07:39 PM PDT 24
Peak memory	207896 kb
Host	smart-d4e53034-6ffe-4102-8741-327e9f51d963
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078408986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.4078408986
Directory	/workspace/21.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/21.keymgr_sideload_kmac.2101344076
Short name	T692
Test name
Test status
Simulation time	258132163 ps
CPU time	8.79 seconds
Started	Apr 20 04:06:59 PM PDT 24
Finished	Apr 20 04:07:08 PM PDT 24
Peak memory	208404 kb
Host	smart-519a8a79-736b-47f6-af68-6b45f43ed6db
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101344076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.2101344076
Directory	/workspace/21.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/21.keymgr_sideload_otbn.1521868081
Short name	T261
Test name
Test status
Simulation time	79703196 ps
CPU time	1.85 seconds
Started	Apr 20 04:06:58 PM PDT 24
Finished	Apr 20 04:07:00 PM PDT 24
Peak memory	207520 kb
Host	smart-b33859ef-c876-45f7-aed9-7ecbb14e198d
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521868081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.1521868081
Directory	/workspace/21.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/21.keymgr_sideload_protect.2131237337
Short name	T132
Test name
Test status
Simulation time	221213615 ps
CPU time	5.03 seconds
Started	Apr 20 04:07:06 PM PDT 24
Finished	Apr 20 04:07:11 PM PDT 24
Peak memory	208152 kb
Host	smart-c09feace-e7ed-4e6c-97c6-77e283028335
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2131237337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.2131237337
Directory	/workspace/21.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/21.keymgr_smoke.2028377586
Short name	T3
Test name
Test status
Simulation time	2243999385 ps
CPU time	7.08 seconds
Started	Apr 20 04:06:59 PM PDT 24
Finished	Apr 20 04:07:06 PM PDT 24
Peak memory	206852 kb
Host	smart-4670bbaa-f3ad-4f0b-9e4f-31a5d0cd7ff5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2028377586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.2028377586
Directory	/workspace/21.keymgr_smoke/latest

Test location	/workspace/coverage/default/21.keymgr_stress_all.3621394845
Short name	T933
Test name
Test status
Simulation time	2435825227 ps
CPU time	18.74 seconds
Started	Apr 20 04:07:03 PM PDT 24
Finished	Apr 20 04:07:22 PM PDT 24
Peak memory	208764 kb
Host	smart-a9124783-405a-457f-b1af-7c71f91588e3
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621394845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.3621394845
Directory	/workspace/21.keymgr_stress_all/latest

Test location	/workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.840935661
Short name	T891
Test name
Test status
Simulation time	583576807 ps
CPU time	6.61 seconds
Started	Apr 20 04:07:02 PM PDT 24
Finished	Apr 20 04:07:09 PM PDT 24
Peak memory	222632 kb
Host	smart-a6d138de-a365-4d9b-88f1-92a40495e36b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840935661 -assert nopost proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.840935661
Directory	/workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/21.keymgr_sw_invalid_input.1308046914
Short name	T1000
Test name
Test status
Simulation time	153977386 ps
CPU time	2.96 seconds
Started	Apr 20 04:07:00 PM PDT 24
Finished	Apr 20 04:07:03 PM PDT 24
Peak memory	214260 kb
Host	smart-71c04d0d-8a98-4c0d-a4c8-e6ffecee70ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1308046914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.1308046914
Directory	/workspace/21.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/21.keymgr_sync_async_fault_cross.1489550119
Short name	T751
Test name
Test status
Simulation time	62493459 ps
CPU time	2.7 seconds
Started	Apr 20 04:07:02 PM PDT 24
Finished	Apr 20 04:07:05 PM PDT 24
Peak memory	210540 kb
Host	smart-e9080cf0-a694-42cd-b641-aa8d9b31c2fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1489550119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.1489550119
Directory	/workspace/21.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/22.keymgr_alert_test.3749480439
Short name	T798
Test name
Test status
Simulation time	15085480 ps
CPU time	0.79 seconds
Started	Apr 20 04:07:10 PM PDT 24
Finished	Apr 20 04:07:12 PM PDT 24
Peak memory	205868 kb
Host	smart-dbc81a1f-5168-4079-8282-ea288594cbfd
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749480439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.3749480439
Directory	/workspace/22.keymgr_alert_test/latest

Test location	/workspace/coverage/default/22.keymgr_custom_cm.199497919
Short name	T761
Test name
Test status
Simulation time	260688461 ps
CPU time	7.79 seconds
Started	Apr 20 04:07:11 PM PDT 24
Finished	Apr 20 04:07:19 PM PDT 24
Peak memory	218260 kb
Host	smart-40494f87-d3ad-49eb-84c1-0ac3b43e5aad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=199497919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.199497919
Directory	/workspace/22.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/22.keymgr_direct_to_disabled.1601412465
Short name	T228
Test name
Test status
Simulation time	37594884 ps
CPU time	2.65 seconds
Started	Apr 20 04:07:07 PM PDT 24
Finished	Apr 20 04:07:10 PM PDT 24
Peak memory	214320 kb
Host	smart-180c7a48-e1ae-4fea-b873-a13b645c58b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1601412465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.1601412465
Directory	/workspace/22.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/22.keymgr_kmac_rsp_err.2902467213
Short name	T325
Test name
Test status
Simulation time	191410959 ps
CPU time	7.17 seconds
Started	Apr 20 04:07:07 PM PDT 24
Finished	Apr 20 04:07:15 PM PDT 24
Peak memory	214416 kb
Host	smart-f13b102f-de3e-4505-96b7-e78033683890
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2902467213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.2902467213
Directory	/workspace/22.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/22.keymgr_lc_disable.2742115641
Short name	T8
Test name
Test status
Simulation time	339326819 ps
CPU time	2.74 seconds
Started	Apr 20 04:07:06 PM PDT 24
Finished	Apr 20 04:07:09 PM PDT 24
Peak memory	222432 kb
Host	smart-f684eac5-5924-429c-9a6f-0a628fafbeae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2742115641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.2742115641
Directory	/workspace/22.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/22.keymgr_random.3445800282
Short name	T948
Test name
Test status
Simulation time	410719462 ps
CPU time	4.52 seconds
Started	Apr 20 04:07:05 PM PDT 24
Finished	Apr 20 04:07:10 PM PDT 24
Peak memory	218180 kb
Host	smart-56cc808e-e7ae-4e86-b4ca-2e116a5dee14
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3445800282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.3445800282
Directory	/workspace/22.keymgr_random/latest

Test location	/workspace/coverage/default/22.keymgr_sideload.402697261
Short name	T240
Test name
Test status
Simulation time	150568848 ps
CPU time	3.69 seconds
Started	Apr 20 04:07:02 PM PDT 24
Finished	Apr 20 04:07:06 PM PDT 24
Peak memory	208696 kb
Host	smart-58b9f0d4-9e63-491d-94f9-c0f7f2cf9a3d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=402697261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.402697261
Directory	/workspace/22.keymgr_sideload/latest

Test location	/workspace/coverage/default/22.keymgr_sideload_aes.3200056684
Short name	T82
Test name
Test status
Simulation time	10343909380 ps
CPU time	88.95 seconds
Started	Apr 20 04:07:06 PM PDT 24
Finished	Apr 20 04:08:36 PM PDT 24
Peak memory	209184 kb
Host	smart-6248c8f3-c0cf-4cc7-b3a5-58bd854ca100
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200056684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.3200056684
Directory	/workspace/22.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/22.keymgr_sideload_kmac.2849431743
Short name	T593
Test name
Test status
Simulation time	4952490305 ps
CPU time	32.29 seconds
Started	Apr 20 04:07:02 PM PDT 24
Finished	Apr 20 04:07:35 PM PDT 24
Peak memory	208544 kb
Host	smart-089c7872-9c00-4218-9dfa-c4556ec19658
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849431743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.2849431743
Directory	/workspace/22.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/22.keymgr_sideload_otbn.2197542174
Short name	T319
Test name
Test status
Simulation time	963984482 ps
CPU time	26.48 seconds
Started	Apr 20 04:07:06 PM PDT 24
Finished	Apr 20 04:07:33 PM PDT 24
Peak memory	208032 kb
Host	smart-0943e5ac-f302-4d2d-bbe1-9ab4167553d7
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197542174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.2197542174
Directory	/workspace/22.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/22.keymgr_sideload_protect.2389996675
Short name	T655
Test name
Test status
Simulation time	104115690 ps
CPU time	2.96 seconds
Started	Apr 20 04:07:11 PM PDT 24
Finished	Apr 20 04:07:14 PM PDT 24
Peak memory	209092 kb
Host	smart-a56ccb40-e17e-4373-bb11-82ba603d7876
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2389996675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.2389996675
Directory	/workspace/22.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/22.keymgr_smoke.2402475983
Short name	T789
Test name
Test status
Simulation time	70501892 ps
CPU time	2.32 seconds
Started	Apr 20 04:07:03 PM PDT 24
Finished	Apr 20 04:07:05 PM PDT 24
Peak memory	206660 kb
Host	smart-6a7c7eaf-f0bd-424f-a909-eeef017f952e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2402475983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.2402475983
Directory	/workspace/22.keymgr_smoke/latest

Test location	/workspace/coverage/default/22.keymgr_sw_invalid_input.3071266110
Short name	T286
Test name
Test status
Simulation time	2336551026 ps
CPU time	31.08 seconds
Started	Apr 20 04:07:07 PM PDT 24
Finished	Apr 20 04:07:39 PM PDT 24
Peak memory	209792 kb
Host	smart-33c36d5a-04a3-4333-bddd-7fb1a9c4642f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3071266110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.3071266110
Directory	/workspace/22.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/22.keymgr_sync_async_fault_cross.2504023367
Short name	T555
Test name
Test status
Simulation time	51635013 ps
CPU time	1.86 seconds
Started	Apr 20 04:07:13 PM PDT 24
Finished	Apr 20 04:07:15 PM PDT 24
Peak memory	209676 kb
Host	smart-9c09442a-3879-4812-98b3-fe43a71e4636
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2504023367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.2504023367
Directory	/workspace/22.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/23.keymgr_alert_test.1357023820
Short name	T877
Test name
Test status
Simulation time	13267396 ps
CPU time	0.76 seconds
Started	Apr 20 04:07:16 PM PDT 24
Finished	Apr 20 04:07:18 PM PDT 24
Peak memory	205864 kb
Host	smart-aba7cfa5-ea61-4287-965a-0c13509c97b4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357023820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.1357023820
Directory	/workspace/23.keymgr_alert_test/latest

Test location	/workspace/coverage/default/23.keymgr_custom_cm.2451967472
Short name	T764
Test name
Test status
Simulation time	60615498 ps
CPU time	2.43 seconds
Started	Apr 20 04:07:17 PM PDT 24
Finished	Apr 20 04:07:20 PM PDT 24
Peak memory	208056 kb
Host	smart-87efd0cd-3905-4d0c-87f3-cfefbe46dda3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2451967472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.2451967472
Directory	/workspace/23.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/23.keymgr_direct_to_disabled.25067262
Short name	T663
Test name
Test status
Simulation time	1084208942 ps
CPU time	29.31 seconds
Started	Apr 20 04:07:13 PM PDT 24
Finished	Apr 20 04:07:42 PM PDT 24
Peak memory	218368 kb
Host	smart-ad358037-4955-4e52-bb6f-97b950ff8288
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=25067262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.25067262
Directory	/workspace/23.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/23.keymgr_hwsw_invalid_input.827574203
Short name	T343
Test name
Test status
Simulation time	104699096 ps
CPU time	4.53 seconds
Started	Apr 20 04:07:11 PM PDT 24
Finished	Apr 20 04:07:15 PM PDT 24
Peak memory	214356 kb
Host	smart-3676cc21-9be4-4f85-8fe0-3e7a57c4cda9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=827574203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.827574203
Directory	/workspace/23.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/23.keymgr_kmac_rsp_err.2631309209
Short name	T98
Test name
Test status
Simulation time	268958908 ps
CPU time	4.22 seconds
Started	Apr 20 04:07:14 PM PDT 24
Finished	Apr 20 04:07:18 PM PDT 24
Peak memory	214200 kb
Host	smart-f65ec974-d744-4458-9d32-7b83d8b98ce6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2631309209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.2631309209
Directory	/workspace/23.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/23.keymgr_random.4163150011
Short name	T745
Test name
Test status
Simulation time	246361054 ps
CPU time	5.37 seconds
Started	Apr 20 04:07:13 PM PDT 24
Finished	Apr 20 04:07:19 PM PDT 24
Peak memory	208696 kb
Host	smart-8262c480-276b-4dfe-af69-ea7de7ebfc1d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4163150011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.4163150011
Directory	/workspace/23.keymgr_random/latest

Test location	/workspace/coverage/default/23.keymgr_sideload.986358895
Short name	T830
Test name
Test status
Simulation time	25884836 ps
CPU time	2.16 seconds
Started	Apr 20 04:07:10 PM PDT 24
Finished	Apr 20 04:07:12 PM PDT 24
Peak memory	208644 kb
Host	smart-605ad82f-c984-48c2-abbc-5b8f85daaff5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=986358895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.986358895
Directory	/workspace/23.keymgr_sideload/latest

Test location	/workspace/coverage/default/23.keymgr_sideload_aes.1279402601
Short name	T737
Test name
Test status
Simulation time	428066387 ps
CPU time	6.39 seconds
Started	Apr 20 04:07:13 PM PDT 24
Finished	Apr 20 04:07:20 PM PDT 24
Peak memory	208308 kb
Host	smart-130f3420-f1a0-4b00-a192-a3354df10448
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279402601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.1279402601
Directory	/workspace/23.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/23.keymgr_sideload_kmac.1772875711
Short name	T699
Test name
Test status
Simulation time	365022924 ps
CPU time	12.01 seconds
Started	Apr 20 04:07:14 PM PDT 24
Finished	Apr 20 04:07:26 PM PDT 24
Peak memory	207864 kb
Host	smart-204b37f1-0daa-4869-9f1e-c56c9c8fdf05
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772875711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.1772875711
Directory	/workspace/23.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/23.keymgr_sideload_otbn.4227337376
Short name	T799
Test name
Test status
Simulation time	134052535 ps
CPU time	3.64 seconds
Started	Apr 20 04:07:13 PM PDT 24
Finished	Apr 20 04:07:17 PM PDT 24
Peak memory	208700 kb
Host	smart-61c23102-3d31-4ac7-8907-e77ec80cf9a5
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227337376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.4227337376
Directory	/workspace/23.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/23.keymgr_sideload_protect.2500592747
Short name	T561
Test name
Test status
Simulation time	488158934 ps
CPU time	14.75 seconds
Started	Apr 20 04:07:16 PM PDT 24
Finished	Apr 20 04:07:31 PM PDT 24
Peak memory	209548 kb
Host	smart-8286879b-6478-4e0a-a400-4dde2d145377
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2500592747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.2500592747
Directory	/workspace/23.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/23.keymgr_smoke.1984616220
Short name	T615
Test name
Test status
Simulation time	300824124 ps
CPU time	4.19 seconds
Started	Apr 20 04:07:09 PM PDT 24
Finished	Apr 20 04:07:13 PM PDT 24
Peak memory	207164 kb
Host	smart-5e1a31ca-5618-4fa9-8cb8-2ec0d99d03da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1984616220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.1984616220
Directory	/workspace/23.keymgr_smoke/latest

Test location	/workspace/coverage/default/23.keymgr_stress_all.3478606357
Short name	T305
Test name
Test status
Simulation time	7388565519 ps
CPU time	47.4 seconds
Started	Apr 20 04:07:16 PM PDT 24
Finished	Apr 20 04:08:03 PM PDT 24
Peak memory	222424 kb
Host	smart-11e5650b-f63f-4cf0-8b54-d263abbedc27
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478606357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.3478606357
Directory	/workspace/23.keymgr_stress_all/latest

Test location	/workspace/coverage/default/23.keymgr_sw_invalid_input.1697678078
Short name	T625
Test name
Test status
Simulation time	195249391 ps
CPU time	2.92 seconds
Started	Apr 20 04:07:16 PM PDT 24
Finished	Apr 20 04:07:20 PM PDT 24
Peak memory	207904 kb
Host	smart-4f705ac2-6487-4571-b88e-dcf1d7e1ec7f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1697678078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.1697678078
Directory	/workspace/23.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/23.keymgr_sync_async_fault_cross.316492110
Short name	T734
Test name
Test status
Simulation time	1754446548 ps
CPU time	17.06 seconds
Started	Apr 20 04:07:17 PM PDT 24
Finished	Apr 20 04:07:34 PM PDT 24
Peak memory	210408 kb
Host	smart-1dd905ec-ec5a-4f40-a41a-e1f916742c9e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=316492110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.316492110
Directory	/workspace/23.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/24.keymgr_alert_test.1826252250
Short name	T563
Test name
Test status
Simulation time	20647725 ps
CPU time	0.87 seconds
Started	Apr 20 04:07:21 PM PDT 24
Finished	Apr 20 04:07:22 PM PDT 24
Peak memory	205892 kb
Host	smart-3af80ea5-6df2-45f2-928b-8f73299f3d3d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826252250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.1826252250
Directory	/workspace/24.keymgr_alert_test/latest

Test location	/workspace/coverage/default/24.keymgr_cfg_regwen.3531176854
Short name	T330
Test name
Test status
Simulation time	488276766 ps
CPU time	25.49 seconds
Started	Apr 20 04:07:16 PM PDT 24
Finished	Apr 20 04:07:42 PM PDT 24
Peak memory	214948 kb
Host	smart-ae8699c0-9115-4c5f-82b4-9692621f064e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3531176854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.3531176854
Directory	/workspace/24.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/24.keymgr_custom_cm.2230017085
Short name	T1055
Test name
Test status
Simulation time	295048812 ps
CPU time	2.57 seconds
Started	Apr 20 04:07:20 PM PDT 24
Finished	Apr 20 04:07:22 PM PDT 24
Peak memory	209124 kb
Host	smart-846a5304-b261-4c77-acad-417be227a80d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2230017085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.2230017085
Directory	/workspace/24.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/24.keymgr_direct_to_disabled.2623272887
Short name	T18
Test name
Test status
Simulation time	65911993 ps
CPU time	2.74 seconds
Started	Apr 20 04:07:22 PM PDT 24
Finished	Apr 20 04:07:25 PM PDT 24
Peak memory	207328 kb
Host	smart-f6250d33-d172-40c6-ba82-380c5f5d8125
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2623272887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.2623272887
Directory	/workspace/24.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/24.keymgr_kmac_rsp_err.2277970125
Short name	T327
Test name
Test status
Simulation time	190173608 ps
CPU time	6.89 seconds
Started	Apr 20 04:07:20 PM PDT 24
Finished	Apr 20 04:07:27 PM PDT 24
Peak memory	209728 kb
Host	smart-3d39dfc3-c0ac-4601-bee7-85485fe85901
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2277970125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.2277970125
Directory	/workspace/24.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/24.keymgr_lc_disable.1542030908
Short name	T916
Test name
Test status
Simulation time	168936895 ps
CPU time	3.05 seconds
Started	Apr 20 04:07:20 PM PDT 24
Finished	Apr 20 04:07:23 PM PDT 24
Peak memory	215432 kb
Host	smart-6d666045-e612-42f1-a4e0-f328fcb5f68c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1542030908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.1542030908
Directory	/workspace/24.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/24.keymgr_random.336772510
Short name	T630
Test name
Test status
Simulation time	321660383 ps
CPU time	3.79 seconds
Started	Apr 20 04:07:18 PM PDT 24
Finished	Apr 20 04:07:22 PM PDT 24
Peak memory	207340 kb
Host	smart-11e3e90d-85af-46a0-87e5-d7545c6d6ade
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=336772510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.336772510
Directory	/workspace/24.keymgr_random/latest

Test location	/workspace/coverage/default/24.keymgr_sideload.1435688770
Short name	T290
Test name
Test status
Simulation time	49364909 ps
CPU time	2.76 seconds
Started	Apr 20 04:07:16 PM PDT 24
Finished	Apr 20 04:07:20 PM PDT 24
Peak memory	206972 kb
Host	smart-1282db36-fee6-4096-9f26-ac792d321562
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1435688770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.1435688770
Directory	/workspace/24.keymgr_sideload/latest

Test location	/workspace/coverage/default/24.keymgr_sideload_aes.41479586
Short name	T658
Test name
Test status
Simulation time	159522540 ps
CPU time	2.46 seconds
Started	Apr 20 04:07:17 PM PDT 24
Finished	Apr 20 04:07:19 PM PDT 24
Peak memory	206872 kb
Host	smart-2c064d35-3fdd-4052-9b09-338783c81613
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41479586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.41479586
Directory	/workspace/24.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/24.keymgr_sideload_kmac.4045227437
Short name	T665
Test name
Test status
Simulation time	488874456 ps
CPU time	10.59 seconds
Started	Apr 20 04:07:17 PM PDT 24
Finished	Apr 20 04:07:28 PM PDT 24
Peak memory	208148 kb
Host	smart-120f1d9c-6353-457a-8e25-abb2a7cac854
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045227437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.4045227437
Directory	/workspace/24.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/24.keymgr_sideload_otbn.1833359456
Short name	T689
Test name
Test status
Simulation time	72748151 ps
CPU time	2.89 seconds
Started	Apr 20 04:07:19 PM PDT 24
Finished	Apr 20 04:07:22 PM PDT 24
Peak memory	207960 kb
Host	smart-208bc589-5e1a-42e1-8d78-63328fa5e9f0
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833359456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.1833359456
Directory	/workspace/24.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/24.keymgr_sideload_protect.3504505408
Short name	T633
Test name
Test status
Simulation time	389142464 ps
CPU time	3.53 seconds
Started	Apr 20 04:07:20 PM PDT 24
Finished	Apr 20 04:07:24 PM PDT 24
Peak memory	208728 kb
Host	smart-298fc475-3e6c-4baf-bd4e-0e11c17baf0f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3504505408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.3504505408
Directory	/workspace/24.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/24.keymgr_smoke.287279018
Short name	T108
Test name
Test status
Simulation time	515556371 ps
CPU time	17.11 seconds
Started	Apr 20 04:07:18 PM PDT 24
Finished	Apr 20 04:07:35 PM PDT 24
Peak memory	207960 kb
Host	smart-04c71f0c-5956-47a2-9ae7-d70e87e9bd53
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=287279018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.287279018
Directory	/workspace/24.keymgr_smoke/latest

Test location	/workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.787499532
Short name	T203
Test name
Test status
Simulation time	622472900 ps
CPU time	9.02 seconds
Started	Apr 20 04:07:21 PM PDT 24
Finished	Apr 20 04:07:30 PM PDT 24
Peak memory	224076 kb
Host	smart-05ca8df0-e54e-4d54-a770-c67a9c421a1b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787499532 -assert nopost proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.787499532
Directory	/workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/24.keymgr_sw_invalid_input.1860856305
Short name	T269
Test name
Test status
Simulation time	232213608 ps
CPU time	9.62 seconds
Started	Apr 20 04:07:21 PM PDT 24
Finished	Apr 20 04:07:30 PM PDT 24
Peak memory	214300 kb
Host	smart-7eaadd0c-b83b-4d96-b013-ad87f50024bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1860856305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.1860856305
Directory	/workspace/24.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/24.keymgr_sync_async_fault_cross.1804864505
Short name	T998
Test name
Test status
Simulation time	10392218290 ps
CPU time	26.42 seconds
Started	Apr 20 04:07:20 PM PDT 24
Finished	Apr 20 04:07:47 PM PDT 24
Peak memory	211108 kb
Host	smart-f8759589-42f7-4ab7-a40d-c64a268b3a5b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1804864505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.1804864505
Directory	/workspace/24.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/25.keymgr_alert_test.3874825462
Short name	T1050
Test name
Test status
Simulation time	17415118 ps
CPU time	0.8 seconds
Started	Apr 20 04:07:31 PM PDT 24
Finished	Apr 20 04:07:32 PM PDT 24
Peak memory	205892 kb
Host	smart-839ad9d6-0903-4269-a696-08537ffca8ea
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874825462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.3874825462
Directory	/workspace/25.keymgr_alert_test/latest

Test location	/workspace/coverage/default/25.keymgr_cfg_regwen.3607324172
Short name	T405
Test name
Test status
Simulation time	29230638 ps
CPU time	2.72 seconds
Started	Apr 20 04:07:23 PM PDT 24
Finished	Apr 20 04:07:26 PM PDT 24
Peak memory	214292 kb
Host	smart-981fe905-5bc2-4559-93e5-f8cc7daf3236
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3607324172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.3607324172
Directory	/workspace/25.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/25.keymgr_custom_cm.3606422647
Short name	T40
Test name
Test status
Simulation time	239760717 ps
CPU time	2.13 seconds
Started	Apr 20 04:07:27 PM PDT 24
Finished	Apr 20 04:07:30 PM PDT 24
Peak memory	209936 kb
Host	smart-3c0614f5-e89b-4b28-b419-a74159b87cfd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3606422647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.3606422647
Directory	/workspace/25.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/25.keymgr_direct_to_disabled.850391445
Short name	T1048
Test name
Test status
Simulation time	1559325682 ps
CPU time	17.77 seconds
Started	Apr 20 04:07:23 PM PDT 24
Finished	Apr 20 04:07:41 PM PDT 24
Peak memory	214292 kb
Host	smart-bbaecb32-26ba-4131-bb3f-12f3729298f2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=850391445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.850391445
Directory	/workspace/25.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/25.keymgr_hwsw_invalid_input.1400851701
Short name	T83
Test name
Test status
Simulation time	380226506 ps
CPU time	4.41 seconds
Started	Apr 20 04:07:28 PM PDT 24
Finished	Apr 20 04:07:33 PM PDT 24
Peak memory	219372 kb
Host	smart-fb6463a8-f21e-4018-9c55-6d4b9a48709c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1400851701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.1400851701
Directory	/workspace/25.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/25.keymgr_kmac_rsp_err.3323636005
Short name	T25
Test name
Test status
Simulation time	50627827 ps
CPU time	3.14 seconds
Started	Apr 20 04:07:26 PM PDT 24
Finished	Apr 20 04:07:30 PM PDT 24
Peak memory	222352 kb
Host	smart-1e4b77ca-76cd-4aff-9b9b-acd7b5336e86
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3323636005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.3323636005
Directory	/workspace/25.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/25.keymgr_lc_disable.1080062712
Short name	T645
Test name
Test status
Simulation time	452290705 ps
CPU time	2.52 seconds
Started	Apr 20 04:07:26 PM PDT 24
Finished	Apr 20 04:07:29 PM PDT 24
Peak memory	214232 kb
Host	smart-172e5787-d4a3-4866-9a6f-0868dfa76ad7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1080062712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.1080062712
Directory	/workspace/25.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/25.keymgr_random.2026648075
Short name	T816
Test name
Test status
Simulation time	101494275 ps
CPU time	4.66 seconds
Started	Apr 20 04:07:23 PM PDT 24
Finished	Apr 20 04:07:28 PM PDT 24
Peak memory	210260 kb
Host	smart-cb6c9d18-b7a8-4f87-89e1-686e2ef720d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2026648075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.2026648075
Directory	/workspace/25.keymgr_random/latest

Test location	/workspace/coverage/default/25.keymgr_sideload.866494093
Short name	T374
Test name
Test status
Simulation time	241097080 ps
CPU time	8.02 seconds
Started	Apr 20 04:07:23 PM PDT 24
Finished	Apr 20 04:07:32 PM PDT 24
Peak memory	207964 kb
Host	smart-065299f0-827b-4c44-ad1b-139024285014
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=866494093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.866494093
Directory	/workspace/25.keymgr_sideload/latest

Test location	/workspace/coverage/default/25.keymgr_sideload_aes.875767430
Short name	T741
Test name
Test status
Simulation time	34976566 ps
CPU time	2.37 seconds
Started	Apr 20 04:07:36 PM PDT 24
Finished	Apr 20 04:07:38 PM PDT 24
Peak memory	206952 kb
Host	smart-d4d61111-2da5-42f0-82fe-93a27c4a7a18
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875767430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.875767430
Directory	/workspace/25.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/25.keymgr_sideload_kmac.649733511
Short name	T835
Test name
Test status
Simulation time	161178419 ps
CPU time	5.04 seconds
Started	Apr 20 04:07:22 PM PDT 24
Finished	Apr 20 04:07:28 PM PDT 24
Peak memory	208492 kb
Host	smart-5e2b127c-6579-4fd7-85ef-1f932f3478c1
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649733511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.649733511
Directory	/workspace/25.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/25.keymgr_sideload_otbn.1635829315
Short name	T902
Test name
Test status
Simulation time	67188611 ps
CPU time	2.83 seconds
Started	Apr 20 04:07:25 PM PDT 24
Finished	Apr 20 04:07:28 PM PDT 24
Peak memory	206740 kb
Host	smart-d09b5070-0a01-4224-b8e1-8e0d4ea8c06e
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635829315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.1635829315
Directory	/workspace/25.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/25.keymgr_sideload_protect.684187036
Short name	T944
Test name
Test status
Simulation time	2197741531 ps
CPU time	16.43 seconds
Started	Apr 20 04:07:25 PM PDT 24
Finished	Apr 20 04:07:42 PM PDT 24
Peak memory	208732 kb
Host	smart-ef442993-70e4-4a80-aa14-267eb1bc46c4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=684187036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.684187036
Directory	/workspace/25.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/25.keymgr_smoke.1499769764
Short name	T112
Test name
Test status
Simulation time	474509074 ps
CPU time	6.19 seconds
Started	Apr 20 04:07:20 PM PDT 24
Finished	Apr 20 04:07:27 PM PDT 24
Peak memory	207824 kb
Host	smart-cbb8b12b-28d6-4457-beac-eb4ddd019d20
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1499769764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.1499769764
Directory	/workspace/25.keymgr_smoke/latest

Test location	/workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.1955481247
Short name	T730
Test name
Test status
Simulation time	274913858 ps
CPU time	8.54 seconds
Started	Apr 20 04:07:32 PM PDT 24
Finished	Apr 20 04:07:41 PM PDT 24
Peak memory	223340 kb
Host	smart-57158449-d214-4a50-a5ed-ede85478bcef
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955481247 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.1955481247
Directory	/workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/25.keymgr_sw_invalid_input.3837343866
Short name	T679
Test name
Test status
Simulation time	10574093476 ps
CPU time	45.84 seconds
Started	Apr 20 04:07:23 PM PDT 24
Finished	Apr 20 04:08:09 PM PDT 24
Peak memory	208420 kb
Host	smart-33abcc91-f2e9-4f96-8d28-90f2aa0b42c6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3837343866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.3837343866
Directory	/workspace/25.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/25.keymgr_sync_async_fault_cross.796477720
Short name	T828
Test name
Test status
Simulation time	40211278 ps
CPU time	1.94 seconds
Started	Apr 20 04:07:27 PM PDT 24
Finished	Apr 20 04:07:29 PM PDT 24
Peak memory	209820 kb
Host	smart-8dc8581b-2f56-4aad-9454-1dc7cfa64a12
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=796477720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.796477720
Directory	/workspace/25.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/26.keymgr_alert_test.3608133912
Short name	T576
Test name
Test status
Simulation time	51882898 ps
CPU time	0.72 seconds
Started	Apr 20 04:07:33 PM PDT 24
Finished	Apr 20 04:07:34 PM PDT 24
Peak memory	205844 kb
Host	smart-e043227d-3860-4d10-b8e1-34dbe50480eb
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608133912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.3608133912
Directory	/workspace/26.keymgr_alert_test/latest

Test location	/workspace/coverage/default/26.keymgr_direct_to_disabled.170508226
Short name	T408
Test name
Test status
Simulation time	54626966 ps
CPU time	2.55 seconds
Started	Apr 20 04:07:33 PM PDT 24
Finished	Apr 20 04:07:36 PM PDT 24
Peak memory	218160 kb
Host	smart-8fe859e0-ff63-4067-bdf5-791e41a721bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=170508226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.170508226
Directory	/workspace/26.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/26.keymgr_hwsw_invalid_input.3833889668
Short name	T628
Test name
Test status
Simulation time	1256542771 ps
CPU time	9.32 seconds
Started	Apr 20 04:07:34 PM PDT 24
Finished	Apr 20 04:07:44 PM PDT 24
Peak memory	214200 kb
Host	smart-36eca521-1aab-4566-a2a9-665822b2d5ef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3833889668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.3833889668
Directory	/workspace/26.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/26.keymgr_lc_disable.3336297159
Short name	T787
Test name
Test status
Simulation time	357699098 ps
CPU time	4.37 seconds
Started	Apr 20 04:07:34 PM PDT 24
Finished	Apr 20 04:07:38 PM PDT 24
Peak memory	209560 kb
Host	smart-e9da178a-c58f-4a62-ba0f-bfb696417e3b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3336297159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.3336297159
Directory	/workspace/26.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/26.keymgr_random.2773207885
Short name	T903
Test name
Test status
Simulation time	1783035943 ps
CPU time	25.21 seconds
Started	Apr 20 04:07:30 PM PDT 24
Finished	Apr 20 04:07:55 PM PDT 24
Peak memory	218476 kb
Host	smart-65d0b0dd-8771-4680-aec2-4522129a413a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2773207885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.2773207885
Directory	/workspace/26.keymgr_random/latest

Test location	/workspace/coverage/default/26.keymgr_sideload.438500782
Short name	T790
Test name
Test status
Simulation time	632873816 ps
CPU time	8.01 seconds
Started	Apr 20 04:07:30 PM PDT 24
Finished	Apr 20 04:07:38 PM PDT 24
Peak memory	208520 kb
Host	smart-d2012d90-9489-45db-8e12-a655ed6f300f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=438500782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.438500782
Directory	/workspace/26.keymgr_sideload/latest

Test location	/workspace/coverage/default/26.keymgr_sideload_aes.4113662967
Short name	T970
Test name
Test status
Simulation time	138028802 ps
CPU time	3.71 seconds
Started	Apr 20 04:07:30 PM PDT 24
Finished	Apr 20 04:07:34 PM PDT 24
Peak memory	206932 kb
Host	smart-1487a380-5841-4ec5-a183-b71f5b7139c3
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113662967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.4113662967
Directory	/workspace/26.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/26.keymgr_sideload_kmac.3283427159
Short name	T921
Test name
Test status
Simulation time	54962884 ps
CPU time	3.03 seconds
Started	Apr 20 04:07:32 PM PDT 24
Finished	Apr 20 04:07:36 PM PDT 24
Peak memory	208400 kb
Host	smart-3c9a32d6-d1b8-42f8-b4aa-e507f1327da0
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283427159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.3283427159
Directory	/workspace/26.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/26.keymgr_sideload_otbn.382485496
Short name	T670
Test name
Test status
Simulation time	14347240438 ps
CPU time	34.82 seconds
Started	Apr 20 04:07:29 PM PDT 24
Finished	Apr 20 04:08:04 PM PDT 24
Peak memory	208872 kb
Host	smart-b0e7447d-a4b5-4eb8-9a76-932a4951a37c
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382485496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.382485496
Directory	/workspace/26.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/26.keymgr_sideload_protect.753334639
Short name	T777
Test name
Test status
Simulation time	124111366 ps
CPU time	4.73 seconds
Started	Apr 20 04:07:32 PM PDT 24
Finished	Apr 20 04:07:37 PM PDT 24
Peak memory	209688 kb
Host	smart-a57524cb-ee96-440a-93af-2fb540fddd96
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=753334639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.753334639
Directory	/workspace/26.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/26.keymgr_smoke.4212397650
Short name	T81
Test name
Test status
Simulation time	115937284 ps
CPU time	2.97 seconds
Started	Apr 20 04:07:31 PM PDT 24
Finished	Apr 20 04:07:35 PM PDT 24
Peak memory	208008 kb
Host	smart-b9ef219c-664a-41dc-b63e-7fa041d671c0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4212397650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.4212397650
Directory	/workspace/26.keymgr_smoke/latest

Test location	/workspace/coverage/default/26.keymgr_stress_all.426555709
Short name	T239
Test name
Test status
Simulation time	1073408765 ps
CPU time	36.52 seconds
Started	Apr 20 04:07:37 PM PDT 24
Finished	Apr 20 04:08:14 PM PDT 24
Peak memory	216496 kb
Host	smart-3034b912-b8f2-477c-a079-f257b7ee47fa
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426555709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.426555709
Directory	/workspace/26.keymgr_stress_all/latest

Test location	/workspace/coverage/default/26.keymgr_sw_invalid_input.3017677378
Short name	T1059
Test name
Test status
Simulation time	10912823545 ps
CPU time	69.14 seconds
Started	Apr 20 04:07:36 PM PDT 24
Finished	Apr 20 04:08:45 PM PDT 24
Peak memory	209180 kb
Host	smart-af1e5059-6dc2-4dde-bc93-d811c715966e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3017677378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.3017677378
Directory	/workspace/26.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/26.keymgr_sync_async_fault_cross.565154064
Short name	T728
Test name
Test status
Simulation time	197625388 ps
CPU time	4.42 seconds
Started	Apr 20 04:07:32 PM PDT 24
Finished	Apr 20 04:07:37 PM PDT 24
Peak memory	210580 kb
Host	smart-3a67c035-de5a-4504-a35d-608fb1345d71
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=565154064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.565154064
Directory	/workspace/26.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/27.keymgr_alert_test.3799368784
Short name	T1031
Test name
Test status
Simulation time	18566691 ps
CPU time	0.86 seconds
Started	Apr 20 04:07:41 PM PDT 24
Finished	Apr 20 04:07:43 PM PDT 24
Peak memory	205844 kb
Host	smart-5246279a-bea4-4625-b8a4-0a81b35bdf52
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799368784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.3799368784
Directory	/workspace/27.keymgr_alert_test/latest

Test location	/workspace/coverage/default/27.keymgr_custom_cm.2277746500
Short name	T30
Test name
Test status
Simulation time	422835289 ps
CPU time	3.33 seconds
Started	Apr 20 04:07:36 PM PDT 24
Finished	Apr 20 04:07:40 PM PDT 24
Peak memory	216972 kb
Host	smart-a93c5cdd-d1b8-48ad-a8e1-43124d09fb5f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2277746500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.2277746500
Directory	/workspace/27.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/27.keymgr_direct_to_disabled.1000138881
Short name	T71
Test name
Test status
Simulation time	92835111 ps
CPU time	2.62 seconds
Started	Apr 20 04:07:35 PM PDT 24
Finished	Apr 20 04:07:38 PM PDT 24
Peak memory	214240 kb
Host	smart-58fd16e9-20c6-4e1f-8284-a7f29f8ad384
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1000138881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.1000138881
Directory	/workspace/27.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/27.keymgr_lc_disable.3096617865
Short name	T825
Test name
Test status
Simulation time	111927477 ps
CPU time	2.95 seconds
Started	Apr 20 04:07:35 PM PDT 24
Finished	Apr 20 04:07:38 PM PDT 24
Peak memory	215188 kb
Host	smart-80397311-5b34-4c4f-a174-c35b960bf58b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3096617865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.3096617865
Directory	/workspace/27.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/27.keymgr_random.2483987788
Short name	T346
Test name
Test status
Simulation time	24739727200 ps
CPU time	45.49 seconds
Started	Apr 20 04:07:39 PM PDT 24
Finished	Apr 20 04:08:25 PM PDT 24
Peak memory	219944 kb
Host	smart-5f36dbb1-7404-4fc3-a21f-34e8bfbf1c19
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2483987788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.2483987788
Directory	/workspace/27.keymgr_random/latest

Test location	/workspace/coverage/default/27.keymgr_sideload.280602042
Short name	T352
Test name
Test status
Simulation time	125704417 ps
CPU time	3.27 seconds
Started	Apr 20 04:07:33 PM PDT 24
Finished	Apr 20 04:07:37 PM PDT 24
Peak memory	208612 kb
Host	smart-d3320beb-7b4d-40c2-a8d0-a3e8301c1800
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=280602042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.280602042
Directory	/workspace/27.keymgr_sideload/latest

Test location	/workspace/coverage/default/27.keymgr_sideload_aes.2909269326
Short name	T606
Test name
Test status
Simulation time	74500978 ps
CPU time	2.12 seconds
Started	Apr 20 04:07:34 PM PDT 24
Finished	Apr 20 04:07:36 PM PDT 24
Peak memory	206848 kb
Host	smart-d80e7a7b-41c6-4782-857c-5dfa953c88bb
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909269326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.2909269326
Directory	/workspace/27.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/27.keymgr_sideload_kmac.3827750919
Short name	T772
Test name
Test status
Simulation time	478153837 ps
CPU time	9.47 seconds
Started	Apr 20 04:07:36 PM PDT 24
Finished	Apr 20 04:07:46 PM PDT 24
Peak memory	208572 kb
Host	smart-1ac66104-f0c0-4f5c-b816-d25ac9359083
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827750919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.3827750919
Directory	/workspace/27.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/27.keymgr_sideload_otbn.3660805022
Short name	T1067
Test name
Test status
Simulation time	222538079 ps
CPU time	2.61 seconds
Started	Apr 20 04:07:36 PM PDT 24
Finished	Apr 20 04:07:39 PM PDT 24
Peak memory	208656 kb
Host	smart-6dd82b0f-25a2-45f1-9b8a-b3e0b477de21
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660805022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.3660805022
Directory	/workspace/27.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/27.keymgr_sideload_protect.1356872233
Short name	T300
Test name
Test status
Simulation time	148335379 ps
CPU time	3.51 seconds
Started	Apr 20 04:07:37 PM PDT 24
Finished	Apr 20 04:07:41 PM PDT 24
Peak memory	218532 kb
Host	smart-f6bab423-9337-4091-88c7-e9842cacc667
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1356872233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.1356872233
Directory	/workspace/27.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/27.keymgr_smoke.1482077580
Short name	T646
Test name
Test status
Simulation time	136844205 ps
CPU time	4.02 seconds
Started	Apr 20 04:07:33 PM PDT 24
Finished	Apr 20 04:07:37 PM PDT 24
Peak memory	208220 kb
Host	smart-17409c27-0327-4eed-ab1b-a75bca97171f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1482077580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.1482077580
Directory	/workspace/27.keymgr_smoke/latest

Test location	/workspace/coverage/default/27.keymgr_stress_all.3192223265
Short name	T267
Test name
Test status
Simulation time	1336862420 ps
CPU time	51.97 seconds
Started	Apr 20 04:07:38 PM PDT 24
Finished	Apr 20 04:08:31 PM PDT 24
Peak memory	222460 kb
Host	smart-bab1cb50-771c-48ee-90d5-7d25ad15c0b5
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192223265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.3192223265
Directory	/workspace/27.keymgr_stress_all/latest

Test location	/workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.3514043727
Short name	T833
Test name
Test status
Simulation time	94174454 ps
CPU time	5.33 seconds
Started	Apr 20 04:07:38 PM PDT 24
Finished	Apr 20 04:07:44 PM PDT 24
Peak memory	222576 kb
Host	smart-3894c60f-a24a-49b0-8f9d-a1c4ffdf9003
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514043727 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.3514043727
Directory	/workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/27.keymgr_sw_invalid_input.159973689
Short name	T288
Test name
Test status
Simulation time	195723361 ps
CPU time	3.67 seconds
Started	Apr 20 04:07:37 PM PDT 24
Finished	Apr 20 04:07:41 PM PDT 24
Peak memory	207900 kb
Host	smart-1f7b4df5-3589-48ef-af2d-8884e30a9991
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=159973689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.159973689
Directory	/workspace/27.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/27.keymgr_sync_async_fault_cross.2959163132
Short name	T579
Test name
Test status
Simulation time	61570818 ps
CPU time	1.75 seconds
Started	Apr 20 04:07:35 PM PDT 24
Finished	Apr 20 04:07:38 PM PDT 24
Peak memory	210084 kb
Host	smart-421a1daf-200d-4744-a5a0-5abaea4ea944
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2959163132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.2959163132
Directory	/workspace/27.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/28.keymgr_alert_test.3911791589
Short name	T1017
Test name
Test status
Simulation time	29290165 ps
CPU time	0.76 seconds
Started	Apr 20 04:07:46 PM PDT 24
Finished	Apr 20 04:07:47 PM PDT 24
Peak memory	205808 kb
Host	smart-d9e1f948-2b4e-42d2-ada7-35958afb0001
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911791589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.3911791589
Directory	/workspace/28.keymgr_alert_test/latest

Test location	/workspace/coverage/default/28.keymgr_cfg_regwen.1816895219
Short name	T225
Test name
Test status
Simulation time	1356039256 ps
CPU time	13.23 seconds
Started	Apr 20 04:07:51 PM PDT 24
Finished	Apr 20 04:08:04 PM PDT 24
Peak memory	214396 kb
Host	smart-ffcd5473-8ead-4e50-ba72-4c7103a05db0
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1816895219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.1816895219
Directory	/workspace/28.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/28.keymgr_custom_cm.3264856794
Short name	T909
Test name
Test status
Simulation time	53574864 ps
CPU time	2.39 seconds
Started	Apr 20 04:07:44 PM PDT 24
Finished	Apr 20 04:07:47 PM PDT 24
Peak memory	210440 kb
Host	smart-6566fe78-fb1e-4f5a-aa75-b582584c74a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3264856794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.3264856794
Directory	/workspace/28.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/28.keymgr_direct_to_disabled.500369655
Short name	T358
Test name
Test status
Simulation time	263915629 ps
CPU time	4.24 seconds
Started	Apr 20 04:07:43 PM PDT 24
Finished	Apr 20 04:07:48 PM PDT 24
Peak memory	218264 kb
Host	smart-fa548994-feb9-4c36-bb1f-91e016384fe6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=500369655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.500369655
Directory	/workspace/28.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/28.keymgr_hwsw_invalid_input.1831304314
Short name	T90
Test name
Test status
Simulation time	249215048 ps
CPU time	6.99 seconds
Started	Apr 20 04:07:43 PM PDT 24
Finished	Apr 20 04:07:51 PM PDT 24
Peak memory	209632 kb
Host	smart-7b19fe4d-2ef4-4762-b71a-0d4709213b08
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1831304314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.1831304314
Directory	/workspace/28.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/28.keymgr_lc_disable.2516307294
Short name	T1004
Test name
Test status
Simulation time	503377287 ps
CPU time	3.72 seconds
Started	Apr 20 04:07:43 PM PDT 24
Finished	Apr 20 04:07:47 PM PDT 24
Peak memory	215484 kb
Host	smart-121f8187-feb0-433d-a940-bd729d173cea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2516307294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.2516307294
Directory	/workspace/28.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/28.keymgr_random.839552371
Short name	T930
Test name
Test status
Simulation time	289183507 ps
CPU time	9.77 seconds
Started	Apr 20 04:07:40 PM PDT 24
Finished	Apr 20 04:07:50 PM PDT 24
Peak memory	214208 kb
Host	smart-541f321a-87fc-4c7b-be4f-35e22404db70
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=839552371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.839552371
Directory	/workspace/28.keymgr_random/latest

Test location	/workspace/coverage/default/28.keymgr_sideload.3360290180
Short name	T1025
Test name
Test status
Simulation time	663490614 ps
CPU time	4.64 seconds
Started	Apr 20 04:07:40 PM PDT 24
Finished	Apr 20 04:07:46 PM PDT 24
Peak memory	207116 kb
Host	smart-59fbefaa-687c-4bcc-995a-20d418523c1f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3360290180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.3360290180
Directory	/workspace/28.keymgr_sideload/latest

Test location	/workspace/coverage/default/28.keymgr_sideload_aes.1408966854
Short name	T701
Test name
Test status
Simulation time	873248092 ps
CPU time	7.04 seconds
Started	Apr 20 04:07:40 PM PDT 24
Finished	Apr 20 04:07:47 PM PDT 24
Peak memory	208668 kb
Host	smart-bd42ce6f-0233-4df6-85f3-60b9df9a3c1c
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408966854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.1408966854
Directory	/workspace/28.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/28.keymgr_sideload_kmac.3459504075
Short name	T859
Test name
Test status
Simulation time	389258307 ps
CPU time	6.43 seconds
Started	Apr 20 04:07:39 PM PDT 24
Finished	Apr 20 04:07:46 PM PDT 24
Peak memory	208404 kb
Host	smart-ecfad0ab-6df2-4187-9dee-f06a01efcb10
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459504075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.3459504075
Directory	/workspace/28.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/28.keymgr_sideload_otbn.1415458939
Short name	T1015
Test name
Test status
Simulation time	769073356 ps
CPU time	2.54 seconds
Started	Apr 20 04:07:40 PM PDT 24
Finished	Apr 20 04:07:43 PM PDT 24
Peak memory	206816 kb
Host	smart-93d562a1-880d-4ab4-9951-eba76871d2f8
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415458939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.1415458939
Directory	/workspace/28.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/28.keymgr_sideload_protect.481029829
Short name	T811
Test name
Test status
Simulation time	749328031 ps
CPU time	3.86 seconds
Started	Apr 20 04:07:42 PM PDT 24
Finished	Apr 20 04:07:46 PM PDT 24
Peak memory	218192 kb
Host	smart-8b38f55e-992a-48f9-a3b1-9bea5e7a7326
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=481029829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.481029829
Directory	/workspace/28.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/28.keymgr_smoke.470853677
Short name	T562
Test name
Test status
Simulation time	48169007 ps
CPU time	2.55 seconds
Started	Apr 20 04:07:40 PM PDT 24
Finished	Apr 20 04:07:43 PM PDT 24
Peak memory	208408 kb
Host	smart-52982f7f-916a-4509-9569-39e03e6747c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=470853677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.470853677
Directory	/workspace/28.keymgr_smoke/latest

Test location	/workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.2140519544
Short name	T671
Test name
Test status
Simulation time	692091709 ps
CPU time	3.47 seconds
Started	Apr 20 04:07:47 PM PDT 24
Finished	Apr 20 04:07:51 PM PDT 24
Peak memory	219228 kb
Host	smart-0e3b3020-6b9d-403f-9f51-2d7bfb2963c3
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140519544 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.2140519544
Directory	/workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/28.keymgr_sw_invalid_input.3708317517
Short name	T184
Test name
Test status
Simulation time	429226685 ps
CPU time	3.69 seconds
Started	Apr 20 04:07:47 PM PDT 24
Finished	Apr 20 04:07:51 PM PDT 24
Peak memory	208268 kb
Host	smart-f4e645f0-a2be-4839-975f-0d1b791fc4d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3708317517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.3708317517
Directory	/workspace/28.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/28.keymgr_sync_async_fault_cross.3409032840
Short name	T957
Test name
Test status
Simulation time	564932148 ps
CPU time	2.18 seconds
Started	Apr 20 04:07:42 PM PDT 24
Finished	Apr 20 04:07:45 PM PDT 24
Peak memory	209640 kb
Host	smart-785c3f2d-4822-451a-893f-f7a7f5b82341
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3409032840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.3409032840
Directory	/workspace/28.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/29.keymgr_alert_test.2932292512
Short name	T702
Test name
Test status
Simulation time	16058282 ps
CPU time	0.8 seconds
Started	Apr 20 04:07:52 PM PDT 24
Finished	Apr 20 04:07:53 PM PDT 24
Peak memory	205784 kb
Host	smart-87e19ad2-6ea1-441c-8cd2-d3b0055ee2ef
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932292512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.2932292512
Directory	/workspace/29.keymgr_alert_test/latest

Test location	/workspace/coverage/default/29.keymgr_cfg_regwen.137177337
Short name	T340
Test name
Test status
Simulation time	480697611 ps
CPU time	3.08 seconds
Started	Apr 20 04:07:46 PM PDT 24
Finished	Apr 20 04:07:49 PM PDT 24
Peak memory	215084 kb
Host	smart-54abf4be-ee0a-418e-b8fc-0d8170a70a67
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=137177337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.137177337
Directory	/workspace/29.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/29.keymgr_custom_cm.2980435866
Short name	T42
Test name
Test status
Simulation time	58299275 ps
CPU time	2.59 seconds
Started	Apr 20 04:07:51 PM PDT 24
Finished	Apr 20 04:07:54 PM PDT 24
Peak memory	208996 kb
Host	smart-4fb85833-0c97-40ac-b849-fa612c988ae5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2980435866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.2980435866
Directory	/workspace/29.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/29.keymgr_direct_to_disabled.3045362807
Short name	T928
Test name
Test status
Simulation time	132155993 ps
CPU time	4.37 seconds
Started	Apr 20 04:07:48 PM PDT 24
Finished	Apr 20 04:07:53 PM PDT 24
Peak memory	209148 kb
Host	smart-6b796c2d-9535-4447-86f2-5177ac3a8bca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3045362807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.3045362807
Directory	/workspace/29.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/29.keymgr_hwsw_invalid_input.620650792
Short name	T342
Test name
Test status
Simulation time	299182913 ps
CPU time	6.28 seconds
Started	Apr 20 04:07:53 PM PDT 24
Finished	Apr 20 04:07:59 PM PDT 24
Peak memory	219840 kb
Host	smart-95f9e969-097c-495e-8964-3e94a2330f0c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=620650792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.620650792
Directory	/workspace/29.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/29.keymgr_lc_disable.950422507
Short name	T338
Test name
Test status
Simulation time	66451550 ps
CPU time	4.68 seconds
Started	Apr 20 04:07:52 PM PDT 24
Finished	Apr 20 04:07:57 PM PDT 24
Peak memory	210568 kb
Host	smart-5fa4716a-6e2a-4de0-b0a9-2c0b4b17278f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=950422507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.950422507
Directory	/workspace/29.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/29.keymgr_random.184482432
Short name	T627
Test name
Test status
Simulation time	3217651452 ps
CPU time	36.65 seconds
Started	Apr 20 04:07:48 PM PDT 24
Finished	Apr 20 04:08:24 PM PDT 24
Peak memory	222496 kb
Host	smart-d4362f86-b395-4f38-b774-7550647fa52d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=184482432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.184482432
Directory	/workspace/29.keymgr_random/latest

Test location	/workspace/coverage/default/29.keymgr_sideload.1369893625
Short name	T942
Test name
Test status
Simulation time	2265287877 ps
CPU time	42.56 seconds
Started	Apr 20 04:07:48 PM PDT 24
Finished	Apr 20 04:08:31 PM PDT 24
Peak memory	208932 kb
Host	smart-7afa1c3e-8e5e-4d69-9728-dd561b82d0e9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1369893625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.1369893625
Directory	/workspace/29.keymgr_sideload/latest

Test location	/workspace/coverage/default/29.keymgr_sideload_aes.786254147
Short name	T977
Test name
Test status
Simulation time	115211353 ps
CPU time	4.25 seconds
Started	Apr 20 04:07:48 PM PDT 24
Finished	Apr 20 04:07:52 PM PDT 24
Peak memory	206824 kb
Host	smart-9e914e51-407d-444a-bf28-f8ebc8840d88
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786254147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.786254147
Directory	/workspace/29.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/29.keymgr_sideload_kmac.1912662431
Short name	T299
Test name
Test status
Simulation time	696180093 ps
CPU time	18.68 seconds
Started	Apr 20 04:07:47 PM PDT 24
Finished	Apr 20 04:08:06 PM PDT 24
Peak memory	209048 kb
Host	smart-aa11a07a-c1aa-49eb-b449-5bb484590341
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912662431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.1912662431
Directory	/workspace/29.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/29.keymgr_sideload_otbn.1424038103
Short name	T616
Test name
Test status
Simulation time	67836422 ps
CPU time	3.03 seconds
Started	Apr 20 04:07:47 PM PDT 24
Finished	Apr 20 04:07:51 PM PDT 24
Peak memory	206800 kb
Host	smart-553903a2-5b4e-4b27-ad45-935315d999e8
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424038103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.1424038103
Directory	/workspace/29.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/29.keymgr_sideload_protect.452108293
Short name	T263
Test name
Test status
Simulation time	71978949 ps
CPU time	3.1 seconds
Started	Apr 20 04:07:51 PM PDT 24
Finished	Apr 20 04:07:55 PM PDT 24
Peak memory	208800 kb
Host	smart-5aeed31e-aa86-4f67-b3cc-5ca487557d57
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=452108293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.452108293
Directory	/workspace/29.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/29.keymgr_smoke.938829213
Short name	T1056
Test name
Test status
Simulation time	61625767 ps
CPU time	3.36 seconds
Started	Apr 20 04:07:47 PM PDT 24
Finished	Apr 20 04:07:51 PM PDT 24
Peak memory	208364 kb
Host	smart-8066b97e-80ad-44c9-97bb-a18466d66ed7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=938829213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.938829213
Directory	/workspace/29.keymgr_smoke/latest

Test location	/workspace/coverage/default/29.keymgr_stress_all.4142150520
Short name	T697
Test name
Test status
Simulation time	5123125705 ps
CPU time	101.31 seconds
Started	Apr 20 04:07:52 PM PDT 24
Finished	Apr 20 04:09:34 PM PDT 24
Peak memory	222468 kb
Host	smart-d0bd553e-9c5f-4e96-bd66-b2d012802ca6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142150520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.4142150520
Directory	/workspace/29.keymgr_stress_all/latest

Test location	/workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.580279070
Short name	T599
Test name
Test status
Simulation time	328812024 ps
CPU time	5.43 seconds
Started	Apr 20 04:07:51 PM PDT 24
Finished	Apr 20 04:07:56 PM PDT 24
Peak memory	222592 kb
Host	smart-4212ab5f-d3cc-4e1d-a44f-28e104aa63fa
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580279070 -assert nopost proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.580279070
Directory	/workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/29.keymgr_sw_invalid_input.1397891051
Short name	T1020
Test name
Test status
Simulation time	683700482 ps
CPU time	4.64 seconds
Started	Apr 20 04:07:54 PM PDT 24
Finished	Apr 20 04:07:59 PM PDT 24
Peak memory	209504 kb
Host	smart-ae82014b-ac10-4316-bc86-0ef55182b02f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1397891051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.1397891051
Directory	/workspace/29.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/29.keymgr_sync_async_fault_cross.3508572916
Short name	T155
Test name
Test status
Simulation time	383820473 ps
CPU time	3.09 seconds
Started	Apr 20 04:07:50 PM PDT 24
Finished	Apr 20 04:07:53 PM PDT 24
Peak memory	210564 kb
Host	smart-dc8d3142-1d3e-4a10-9f76-751d6d8711ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3508572916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.3508572916
Directory	/workspace/29.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/3.keymgr_alert_test.1573388718
Short name	T875
Test name
Test status
Simulation time	35221537 ps
CPU time	0.74 seconds
Started	Apr 20 04:04:58 PM PDT 24
Finished	Apr 20 04:04:59 PM PDT 24
Peak memory	205828 kb
Host	smart-adb73d00-100f-48e5-84e6-ef1feef438d5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573388718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.1573388718
Directory	/workspace/3.keymgr_alert_test/latest

Test location	/workspace/coverage/default/3.keymgr_cfg_regwen.3260167290
Short name	T404
Test name
Test status
Simulation time	65923781 ps
CPU time	2.85 seconds
Started	Apr 20 04:04:48 PM PDT 24
Finished	Apr 20 04:04:52 PM PDT 24
Peak memory	214412 kb
Host	smart-dee43a16-c9cf-4bf6-ac93-1e78c171acb8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3260167290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.3260167290
Directory	/workspace/3.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/3.keymgr_direct_to_disabled.2004512951
Short name	T967
Test name
Test status
Simulation time	822201291 ps
CPU time	9.26 seconds
Started	Apr 20 04:04:51 PM PDT 24
Finished	Apr 20 04:05:01 PM PDT 24
Peak memory	218448 kb
Host	smart-84868e5f-ee6d-4c9c-9252-9928523dd784
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2004512951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.2004512951
Directory	/workspace/3.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/3.keymgr_hwsw_invalid_input.3602748691
Short name	T978
Test name
Test status
Simulation time	386162833 ps
CPU time	7.89 seconds
Started	Apr 20 04:04:53 PM PDT 24
Finished	Apr 20 04:05:02 PM PDT 24
Peak memory	219132 kb
Host	smart-196689e4-43a8-4eb5-97fa-b0345c3619bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3602748691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.3602748691
Directory	/workspace/3.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/3.keymgr_kmac_rsp_err.975175870
Short name	T359
Test name
Test status
Simulation time	782209930 ps
CPU time	7.31 seconds
Started	Apr 20 04:04:54 PM PDT 24
Finished	Apr 20 04:05:01 PM PDT 24
Peak memory	214268 kb
Host	smart-4a35e630-4059-4894-9fe0-c305d45acac2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=975175870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.975175870
Directory	/workspace/3.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/3.keymgr_lc_disable.2125537901
Short name	T7
Test name
Test status
Simulation time	99791396 ps
CPU time	3.68 seconds
Started	Apr 20 04:04:53 PM PDT 24
Finished	Apr 20 04:04:57 PM PDT 24
Peak memory	214412 kb
Host	smart-a32cc4ff-e41c-4865-9075-6ec031250390
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2125537901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.2125537901
Directory	/workspace/3.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/3.keymgr_random.3332461312
Short name	T753
Test name
Test status
Simulation time	300295500 ps
CPU time	4.98 seconds
Started	Apr 20 04:04:50 PM PDT 24
Finished	Apr 20 04:04:56 PM PDT 24
Peak memory	209260 kb
Host	smart-be5cd615-7512-4227-b6c1-5c1e033ecf5b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3332461312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.3332461312
Directory	/workspace/3.keymgr_random/latest

Test location	/workspace/coverage/default/3.keymgr_sec_cm.573730973
Short name	T105
Test name
Test status
Simulation time	337538586 ps
CPU time	12.17 seconds
Started	Apr 20 04:04:56 PM PDT 24
Finished	Apr 20 04:05:09 PM PDT 24
Peak memory	238216 kb
Host	smart-af0f7fce-3409-4e42-9452-c7ec14319fd2
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573730973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.573730973
Directory	/workspace/3.keymgr_sec_cm/latest

Test location	/workspace/coverage/default/3.keymgr_sideload.2499744141
Short name	T653
Test name
Test status
Simulation time	111745219 ps
CPU time	2.9 seconds
Started	Apr 20 04:04:46 PM PDT 24
Finished	Apr 20 04:04:49 PM PDT 24
Peak memory	208124 kb
Host	smart-9370ae84-1d14-4606-963a-05d95da32c35
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2499744141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.2499744141
Directory	/workspace/3.keymgr_sideload/latest

Test location	/workspace/coverage/default/3.keymgr_sideload_aes.802908573
Short name	T853
Test name
Test status
Simulation time	159799962 ps
CPU time	2.55 seconds
Started	Apr 20 04:04:53 PM PDT 24
Finished	Apr 20 04:04:56 PM PDT 24
Peak memory	206756 kb
Host	smart-90e27030-d042-45b1-8a29-3d6883d47365
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802908573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.802908573
Directory	/workspace/3.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/3.keymgr_sideload_kmac.3826119417
Short name	T634
Test name
Test status
Simulation time	143235073 ps
CPU time	2.71 seconds
Started	Apr 20 04:04:51 PM PDT 24
Finished	Apr 20 04:04:54 PM PDT 24
Peak memory	208744 kb
Host	smart-33a0f8ed-2089-42b3-9854-0e79358d004c
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826119417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.3826119417
Directory	/workspace/3.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/3.keymgr_sideload_otbn.1793036784
Short name	T797
Test name
Test status
Simulation time	611777748 ps
CPU time	5.25 seconds
Started	Apr 20 04:04:49 PM PDT 24
Finished	Apr 20 04:04:55 PM PDT 24
Peak memory	206828 kb
Host	smart-574f7a76-d74b-4e80-a164-8cd6f77dfac6
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793036784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.1793036784
Directory	/workspace/3.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/3.keymgr_sideload_protect.802573786
Short name	T590
Test name
Test status
Simulation time	23478374 ps
CPU time	1.71 seconds
Started	Apr 20 04:04:57 PM PDT 24
Finished	Apr 20 04:04:59 PM PDT 24
Peak memory	209036 kb
Host	smart-b33745d1-9a15-4d61-ac7f-37e4b0040485
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=802573786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.802573786
Directory	/workspace/3.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/3.keymgr_smoke.3928457553
Short name	T556
Test name
Test status
Simulation time	35171794 ps
CPU time	2.31 seconds
Started	Apr 20 04:04:49 PM PDT 24
Finished	Apr 20 04:04:51 PM PDT 24
Peak memory	206780 kb
Host	smart-81d2981a-16b0-4aaf-8fd6-18180a1d8559
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3928457553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.3928457553
Directory	/workspace/3.keymgr_smoke/latest

Test location	/workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.3758277521
Short name	T594
Test name
Test status
Simulation time	304350513 ps
CPU time	3.12 seconds
Started	Apr 20 04:04:57 PM PDT 24
Finished	Apr 20 04:05:01 PM PDT 24
Peak memory	222588 kb
Host	smart-0268d3eb-b454-487c-973b-afb124ba47f0
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758277521 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.3758277521
Directory	/workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/3.keymgr_sw_invalid_input.2082035354
Short name	T409
Test name
Test status
Simulation time	667812985 ps
CPU time	7.44 seconds
Started	Apr 20 04:04:54 PM PDT 24
Finished	Apr 20 04:05:02 PM PDT 24
Peak memory	210032 kb
Host	smart-998e6481-93e8-4f41-8fed-6945591e918e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2082035354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.2082035354
Directory	/workspace/3.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/3.keymgr_sync_async_fault_cross.3610148673
Short name	T713
Test name
Test status
Simulation time	86142308 ps
CPU time	2.04 seconds
Started	Apr 20 04:04:56 PM PDT 24
Finished	Apr 20 04:04:59 PM PDT 24
Peak memory	209840 kb
Host	smart-9bce7049-274a-4a8a-849d-4d48454d4f4c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3610148673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.3610148673
Directory	/workspace/3.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/30.keymgr_alert_test.4208721130
Short name	T570
Test name
Test status
Simulation time	11866600 ps
CPU time	0.74 seconds
Started	Apr 20 04:07:58 PM PDT 24
Finished	Apr 20 04:07:59 PM PDT 24
Peak memory	205876 kb
Host	smart-ec9c0192-0465-423c-9aef-42ec57aec5de
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208721130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.4208721130
Directory	/workspace/30.keymgr_alert_test/latest

Test location	/workspace/coverage/default/30.keymgr_cfg_regwen.755039123
Short name	T242
Test name
Test status
Simulation time	798990899 ps
CPU time	11.74 seconds
Started	Apr 20 04:07:57 PM PDT 24
Finished	Apr 20 04:08:09 PM PDT 24
Peak memory	215192 kb
Host	smart-54f1864b-26c3-4d7e-bab3-a8b160987b37
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=755039123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.755039123
Directory	/workspace/30.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/30.keymgr_direct_to_disabled.1921601785
Short name	T189
Test name
Test status
Simulation time	180426293 ps
CPU time	4.13 seconds
Started	Apr 20 04:07:55 PM PDT 24
Finished	Apr 20 04:08:00 PM PDT 24
Peak memory	218076 kb
Host	smart-38c5a6f9-6d6d-4a09-8397-dee45f1712bf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1921601785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.1921601785
Directory	/workspace/30.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/30.keymgr_hwsw_invalid_input.2159989052
Short name	T752
Test name
Test status
Simulation time	5318585452 ps
CPU time	19.16 seconds
Started	Apr 20 04:07:56 PM PDT 24
Finished	Apr 20 04:08:15 PM PDT 24
Peak memory	222536 kb
Host	smart-1702d6d2-88da-4776-9f24-b380a6ff6325
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2159989052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.2159989052
Directory	/workspace/30.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/30.keymgr_lc_disable.4121525007
Short name	T220
Test name
Test status
Simulation time	54438250 ps
CPU time	3.66 seconds
Started	Apr 20 04:07:55 PM PDT 24
Finished	Apr 20 04:07:59 PM PDT 24
Peak memory	220216 kb
Host	smart-57f6ebe6-63c1-490e-ab1b-8f94af0d6862
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4121525007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.4121525007
Directory	/workspace/30.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/30.keymgr_random.1147353275
Short name	T183
Test name
Test status
Simulation time	69552857 ps
CPU time	3.84 seconds
Started	Apr 20 04:07:54 PM PDT 24
Finished	Apr 20 04:07:58 PM PDT 24
Peak memory	208644 kb
Host	smart-113706cf-e4c5-4307-917e-279544909014
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1147353275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.1147353275
Directory	/workspace/30.keymgr_random/latest

Test location	/workspace/coverage/default/30.keymgr_sideload.2629633987
Short name	T884
Test name
Test status
Simulation time	294293931 ps
CPU time	3.73 seconds
Started	Apr 20 04:07:50 PM PDT 24
Finished	Apr 20 04:07:54 PM PDT 24
Peak memory	206728 kb
Host	smart-b96bb404-00a2-4311-b7f7-98a496563f25
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2629633987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.2629633987
Directory	/workspace/30.keymgr_sideload/latest

Test location	/workspace/coverage/default/30.keymgr_sideload_aes.1875622190
Short name	T786
Test name
Test status
Simulation time	142164132 ps
CPU time	4.12 seconds
Started	Apr 20 04:07:54 PM PDT 24
Finished	Apr 20 04:07:58 PM PDT 24
Peak memory	208392 kb
Host	smart-a1e8e30c-68ce-4101-a79b-6f916975da31
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875622190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.1875622190
Directory	/workspace/30.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/30.keymgr_sideload_kmac.2191886566
Short name	T194
Test name
Test status
Simulation time	277703268 ps
CPU time	3.13 seconds
Started	Apr 20 04:07:51 PM PDT 24
Finished	Apr 20 04:07:55 PM PDT 24
Peak memory	206940 kb
Host	smart-358316d2-f3a0-4775-9e0b-89867d873099
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191886566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.2191886566
Directory	/workspace/30.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/30.keymgr_sideload_otbn.1755525411
Short name	T1012
Test name
Test status
Simulation time	641521075 ps
CPU time	7.94 seconds
Started	Apr 20 04:07:52 PM PDT 24
Finished	Apr 20 04:08:01 PM PDT 24
Peak memory	208152 kb
Host	smart-a6bb7b0c-77cc-46c8-a77b-174df612fe63
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755525411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.1755525411
Directory	/workspace/30.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/30.keymgr_sideload_protect.1340286822
Short name	T682
Test name
Test status
Simulation time	856242754 ps
CPU time	5.35 seconds
Started	Apr 20 04:07:57 PM PDT 24
Finished	Apr 20 04:08:03 PM PDT 24
Peak memory	218292 kb
Host	smart-ef0a54ab-6127-4406-be8d-76892857fd47
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1340286822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.1340286822
Directory	/workspace/30.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/30.keymgr_smoke.1483806368
Short name	T824
Test name
Test status
Simulation time	198959565 ps
CPU time	2.95 seconds
Started	Apr 20 04:07:52 PM PDT 24
Finished	Apr 20 04:07:55 PM PDT 24
Peak memory	206808 kb
Host	smart-2b0c7613-c333-4001-b9c0-b69ccd052769
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1483806368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.1483806368
Directory	/workspace/30.keymgr_smoke/latest

Test location	/workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.1146710751
Short name	T803
Test name
Test status
Simulation time	1738171967 ps
CPU time	7.32 seconds
Started	Apr 20 04:07:58 PM PDT 24
Finished	Apr 20 04:08:06 PM PDT 24
Peak memory	222660 kb
Host	smart-5f422abd-0a61-4a11-a7ca-78366ff09152
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146710751 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.1146710751
Directory	/workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/30.keymgr_sw_invalid_input.1925212263
Short name	T367
Test name
Test status
Simulation time	521612191 ps
CPU time	6.7 seconds
Started	Apr 20 04:07:55 PM PDT 24
Finished	Apr 20 04:08:02 PM PDT 24
Peak memory	210368 kb
Host	smart-c818c4ad-7290-4bb0-87f2-1f38710787cf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1925212263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.1925212263
Directory	/workspace/30.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/30.keymgr_sync_async_fault_cross.2878257345
Short name	T569
Test name
Test status
Simulation time	66195434 ps
CPU time	2.76 seconds
Started	Apr 20 04:07:58 PM PDT 24
Finished	Apr 20 04:08:02 PM PDT 24
Peak memory	210296 kb
Host	smart-3d7484da-66c4-4179-a0dd-fe5d5646eb7b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2878257345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.2878257345
Directory	/workspace/30.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/31.keymgr_alert_test.1329670129
Short name	T939
Test name
Test status
Simulation time	58891275 ps
CPU time	0.82 seconds
Started	Apr 20 04:08:07 PM PDT 24
Finished	Apr 20 04:08:08 PM PDT 24
Peak memory	205808 kb
Host	smart-51e6863e-b772-4f74-b92c-4c8a2df73eb9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329670129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.1329670129
Directory	/workspace/31.keymgr_alert_test/latest

Test location	/workspace/coverage/default/31.keymgr_cfg_regwen.3384478938
Short name	T415
Test name
Test status
Simulation time	597289665 ps
CPU time	2.88 seconds
Started	Apr 20 04:08:07 PM PDT 24
Finished	Apr 20 04:08:10 PM PDT 24
Peak memory	215516 kb
Host	smart-f93d8e2e-346b-4b87-8927-fdcb51a63080
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3384478938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.3384478938
Directory	/workspace/31.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/31.keymgr_custom_cm.3389927844
Short name	T676
Test name
Test status
Simulation time	312820622 ps
CPU time	4.83 seconds
Started	Apr 20 04:08:00 PM PDT 24
Finished	Apr 20 04:08:06 PM PDT 24
Peak memory	222700 kb
Host	smart-4393f606-454c-43cf-ab86-0af4646dbcb2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3389927844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.3389927844
Directory	/workspace/31.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/31.keymgr_direct_to_disabled.2271581078
Short name	T268
Test name
Test status
Simulation time	151022632 ps
CPU time	2.48 seconds
Started	Apr 20 04:08:00 PM PDT 24
Finished	Apr 20 04:08:03 PM PDT 24
Peak memory	208644 kb
Host	smart-4b702d3c-c82f-4f6f-81aa-4a9f5fd10ea1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2271581078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.2271581078
Directory	/workspace/31.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/31.keymgr_hwsw_invalid_input.3346291419
Short name	T793
Test name
Test status
Simulation time	7049920914 ps
CPU time	34.45 seconds
Started	Apr 20 04:08:01 PM PDT 24
Finished	Apr 20 04:08:35 PM PDT 24
Peak memory	214392 kb
Host	smart-8ba37eff-49f5-48e2-9169-d1dac46e8925
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3346291419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.3346291419
Directory	/workspace/31.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/31.keymgr_kmac_rsp_err.2104513227
Short name	T97
Test name
Test status
Simulation time	244986114 ps
CPU time	6.93 seconds
Started	Apr 20 04:08:07 PM PDT 24
Finished	Apr 20 04:08:15 PM PDT 24
Peak memory	221808 kb
Host	smart-a4eed8e2-629c-4b92-9a99-109c8184ee4f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2104513227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.2104513227
Directory	/workspace/31.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/31.keymgr_lc_disable.3293795871
Short name	T894
Test name
Test status
Simulation time	237545313 ps
CPU time	3.64 seconds
Started	Apr 20 04:08:04 PM PDT 24
Finished	Apr 20 04:08:08 PM PDT 24
Peak memory	208956 kb
Host	smart-e7459bc9-8084-4248-bf76-58c8bff3c273
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3293795871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.3293795871
Directory	/workspace/31.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/31.keymgr_random.2208162021
Short name	T372
Test name
Test status
Simulation time	68715046 ps
CPU time	4 seconds
Started	Apr 20 04:08:07 PM PDT 24
Finished	Apr 20 04:08:12 PM PDT 24
Peak memory	218180 kb
Host	smart-9016b4b7-0da1-4102-87d5-c4e67927bb1f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2208162021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.2208162021
Directory	/workspace/31.keymgr_random/latest

Test location	/workspace/coverage/default/31.keymgr_sideload.782170571
Short name	T991
Test name
Test status
Simulation time	884925362 ps
CPU time	9.32 seconds
Started	Apr 20 04:07:59 PM PDT 24
Finished	Apr 20 04:08:09 PM PDT 24
Peak memory	208000 kb
Host	smart-81abf274-9707-4dde-b35d-a52751658cc0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=782170571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.782170571
Directory	/workspace/31.keymgr_sideload/latest

Test location	/workspace/coverage/default/31.keymgr_sideload_aes.2115985280
Short name	T795
Test name
Test status
Simulation time	69698987 ps
CPU time	3.46 seconds
Started	Apr 20 04:08:01 PM PDT 24
Finished	Apr 20 04:08:05 PM PDT 24
Peak memory	208796 kb
Host	smart-1785c2fc-8cf4-4f5b-b393-3107065994bf
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115985280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.2115985280
Directory	/workspace/31.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/31.keymgr_sideload_kmac.1715450431
Short name	T318
Test name
Test status
Simulation time	137292485 ps
CPU time	2.64 seconds
Started	Apr 20 04:08:01 PM PDT 24
Finished	Apr 20 04:08:04 PM PDT 24
Peak memory	206908 kb
Host	smart-eff5d45b-5a02-49e1-b68a-9ab26817b539
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715450431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.1715450431
Directory	/workspace/31.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/31.keymgr_sideload_otbn.2073038480
Short name	T897
Test name
Test status
Simulation time	243497520 ps
CPU time	2.91 seconds
Started	Apr 20 04:08:01 PM PDT 24
Finished	Apr 20 04:08:05 PM PDT 24
Peak memory	206804 kb
Host	smart-3ce6e919-1e73-448c-9066-de13501e2a9d
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073038480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.2073038480
Directory	/workspace/31.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/31.keymgr_sideload_protect.1966977550
Short name	T558
Test name
Test status
Simulation time	28699133 ps
CPU time	2.17 seconds
Started	Apr 20 04:08:08 PM PDT 24
Finished	Apr 20 04:08:11 PM PDT 24
Peak memory	215864 kb
Host	smart-1ffd3aeb-470a-4642-89ef-62a84b075c2d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1966977550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.1966977550
Directory	/workspace/31.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/31.keymgr_smoke.1051930312
Short name	T719
Test name
Test status
Simulation time	262083528 ps
CPU time	6.39 seconds
Started	Apr 20 04:07:58 PM PDT 24
Finished	Apr 20 04:08:05 PM PDT 24
Peak memory	208480 kb
Host	smart-a7b34ca3-7fb4-4618-95fd-5db27d04face
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1051930312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.1051930312
Directory	/workspace/31.keymgr_smoke/latest

Test location	/workspace/coverage/default/31.keymgr_stress_all.3546650197
Short name	T266
Test name
Test status
Simulation time	9222137817 ps
CPU time	209.26 seconds
Started	Apr 20 04:08:08 PM PDT 24
Finished	Apr 20 04:11:37 PM PDT 24
Peak memory	224380 kb
Host	smart-f7881487-39d3-43d3-b7fd-cc905197aa58
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546650197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.3546650197
Directory	/workspace/31.keymgr_stress_all/latest

Test location	/workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.1573922820
Short name	T820
Test name
Test status
Simulation time	1244820978 ps
CPU time	14.15 seconds
Started	Apr 20 04:08:03 PM PDT 24
Finished	Apr 20 04:08:17 PM PDT 24
Peak memory	222664 kb
Host	smart-3ed0ab00-4f6f-47e0-b042-0b2eff83b4b1
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573922820 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.1573922820
Directory	/workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/31.keymgr_sw_invalid_input.2693760237
Short name	T878
Test name
Test status
Simulation time	167721417 ps
CPU time	3.28 seconds
Started	Apr 20 04:08:03 PM PDT 24
Finished	Apr 20 04:08:06 PM PDT 24
Peak memory	207156 kb
Host	smart-f0aee98d-938a-46a7-9765-6bd9b3b339e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2693760237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.2693760237
Directory	/workspace/31.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/31.keymgr_sync_async_fault_cross.3754793043
Short name	T37
Test name
Test status
Simulation time	316269080 ps
CPU time	4.28 seconds
Started	Apr 20 04:08:02 PM PDT 24
Finished	Apr 20 04:08:06 PM PDT 24
Peak memory	210944 kb
Host	smart-c173b7df-8d86-44af-b73b-b43f815a3ff5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3754793043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.3754793043
Directory	/workspace/31.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/32.keymgr_alert_test.3486331731
Short name	T887
Test name
Test status
Simulation time	21942829 ps
CPU time	0.73 seconds
Started	Apr 20 04:08:10 PM PDT 24
Finished	Apr 20 04:08:11 PM PDT 24
Peak memory	205816 kb
Host	smart-7eaf6a5c-0cbc-42ed-ab27-352398bca103
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486331731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.3486331731
Directory	/workspace/32.keymgr_alert_test/latest

Test location	/workspace/coverage/default/32.keymgr_custom_cm.282606676
Short name	T328
Test name
Test status
Simulation time	649513850 ps
CPU time	5.4 seconds
Started	Apr 20 04:08:10 PM PDT 24
Finished	Apr 20 04:08:15 PM PDT 24
Peak memory	210432 kb
Host	smart-92f5c78a-838f-4498-8ceb-b3cd9e94fff3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=282606676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.282606676
Directory	/workspace/32.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/32.keymgr_direct_to_disabled.1506430706
Short name	T355
Test name
Test status
Simulation time	214864567 ps
CPU time	2.75 seconds
Started	Apr 20 04:08:04 PM PDT 24
Finished	Apr 20 04:08:07 PM PDT 24
Peak memory	207128 kb
Host	smart-f60abde2-69d4-4932-a09c-c0f5ca6aa660
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1506430706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.1506430706
Directory	/workspace/32.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/32.keymgr_kmac_rsp_err.2499039893
Short name	T1023
Test name
Test status
Simulation time	56917284 ps
CPU time	3.27 seconds
Started	Apr 20 04:08:08 PM PDT 24
Finished	Apr 20 04:08:12 PM PDT 24
Peak memory	221104 kb
Host	smart-211d6438-9dad-4177-874c-bf0a0dfc3d8a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2499039893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.2499039893
Directory	/workspace/32.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/32.keymgr_lc_disable.2045520579
Short name	T927
Test name
Test status
Simulation time	124622550 ps
CPU time	4.05 seconds
Started	Apr 20 04:08:05 PM PDT 24
Finished	Apr 20 04:08:09 PM PDT 24
Peak memory	214336 kb
Host	smart-41c79b21-83b2-4cb1-a85a-2986f664c719
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2045520579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.2045520579
Directory	/workspace/32.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/32.keymgr_random.2427200089
Short name	T277
Test name
Test status
Simulation time	490240475 ps
CPU time	5.6 seconds
Started	Apr 20 04:08:08 PM PDT 24
Finished	Apr 20 04:08:14 PM PDT 24
Peak memory	207104 kb
Host	smart-36d30e24-ab23-4a5d-96be-c0e3e54e30c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2427200089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.2427200089
Directory	/workspace/32.keymgr_random/latest

Test location	/workspace/coverage/default/32.keymgr_sideload.4258226034
Short name	T312
Test name
Test status
Simulation time	5071857416 ps
CPU time	54.72 seconds
Started	Apr 20 04:08:05 PM PDT 24
Finished	Apr 20 04:09:00 PM PDT 24
Peak memory	208608 kb
Host	smart-58e9b4a5-48da-4272-928e-8b18393933d8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4258226034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.4258226034
Directory	/workspace/32.keymgr_sideload/latest

Test location	/workspace/coverage/default/32.keymgr_sideload_aes.3073017693
Short name	T882
Test name
Test status
Simulation time	100815383 ps
CPU time	2.62 seconds
Started	Apr 20 04:08:05 PM PDT 24
Finished	Apr 20 04:08:08 PM PDT 24
Peak memory	206856 kb
Host	smart-2f4e588c-4763-4cb0-a673-150ed6bd9a69
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073017693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.3073017693
Directory	/workspace/32.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/32.keymgr_sideload_kmac.3517013024
Short name	T879
Test name
Test status
Simulation time	39271374 ps
CPU time	2.63 seconds
Started	Apr 20 04:08:04 PM PDT 24
Finished	Apr 20 04:08:07 PM PDT 24
Peak memory	206896 kb
Host	smart-95819ec6-4527-4d34-b482-ff0017a237c2
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517013024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.3517013024
Directory	/workspace/32.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/32.keymgr_sideload_protect.2098413278
Short name	T589
Test name
Test status
Simulation time	208094227 ps
CPU time	2.94 seconds
Started	Apr 20 04:08:08 PM PDT 24
Finished	Apr 20 04:08:12 PM PDT 24
Peak memory	209180 kb
Host	smart-4c26b021-ce3d-416f-ae44-fda27b31f21d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2098413278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.2098413278
Directory	/workspace/32.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/32.keymgr_smoke.2440719224
Short name	T907
Test name
Test status
Simulation time	644087446 ps
CPU time	7.75 seconds
Started	Apr 20 04:08:08 PM PDT 24
Finished	Apr 20 04:08:16 PM PDT 24
Peak memory	208536 kb
Host	smart-de1c7cc5-7a32-482d-bd84-27c026d7a09e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2440719224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.2440719224
Directory	/workspace/32.keymgr_smoke/latest

Test location	/workspace/coverage/default/32.keymgr_stress_all.3127292953
Short name	T210
Test name
Test status
Simulation time	9318481607 ps
CPU time	98.9 seconds
Started	Apr 20 04:08:08 PM PDT 24
Finished	Apr 20 04:09:48 PM PDT 24
Peak memory	215208 kb
Host	smart-b7213d72-c649-4d05-8f55-ff92104a4d6b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127292953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.3127292953
Directory	/workspace/32.keymgr_stress_all/latest

Test location	/workspace/coverage/default/32.keymgr_sw_invalid_input.5660964
Short name	T705
Test name
Test status
Simulation time	41544502 ps
CPU time	2.99 seconds
Started	Apr 20 04:08:06 PM PDT 24
Finished	Apr 20 04:08:10 PM PDT 24
Peak memory	207592 kb
Host	smart-ab786d36-9cc5-4f0a-9e4f-6ca1cd4e857c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=5660964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.5660964
Directory	/workspace/32.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/32.keymgr_sync_async_fault_cross.1377978234
Short name	T639
Test name
Test status
Simulation time	180052510 ps
CPU time	3.18 seconds
Started	Apr 20 04:08:10 PM PDT 24
Finished	Apr 20 04:08:14 PM PDT 24
Peak memory	210380 kb
Host	smart-5f7ec8a3-c42c-42ff-b504-6bf2210f31e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1377978234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.1377978234
Directory	/workspace/32.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/33.keymgr_alert_test.1243048592
Short name	T899
Test name
Test status
Simulation time	73021248 ps
CPU time	0.92 seconds
Started	Apr 20 04:08:14 PM PDT 24
Finished	Apr 20 04:08:15 PM PDT 24
Peak memory	205844 kb
Host	smart-c82664cc-ec6c-4515-977f-d73f25078217
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243048592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.1243048592
Directory	/workspace/33.keymgr_alert_test/latest

Test location	/workspace/coverage/default/33.keymgr_custom_cm.1968114075
Short name	T994
Test name
Test status
Simulation time	193575490 ps
CPU time	6.71 seconds
Started	Apr 20 04:08:19 PM PDT 24
Finished	Apr 20 04:08:27 PM PDT 24
Peak memory	209152 kb
Host	smart-07f510a4-60cd-46df-9522-b4472acbd6d3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1968114075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.1968114075
Directory	/workspace/33.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/33.keymgr_direct_to_disabled.3888555799
Short name	T322
Test name
Test status
Simulation time	2976745644 ps
CPU time	30.4 seconds
Started	Apr 20 04:08:12 PM PDT 24
Finished	Apr 20 04:08:43 PM PDT 24
Peak memory	218400 kb
Host	smart-fbefeb72-21d8-4e98-b7ed-f3cc8b0ed311
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3888555799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.3888555799
Directory	/workspace/33.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/33.keymgr_hwsw_invalid_input.75897801
Short name	T329
Test name
Test status
Simulation time	346428942 ps
CPU time	5.33 seconds
Started	Apr 20 04:08:13 PM PDT 24
Finished	Apr 20 04:08:18 PM PDT 24
Peak memory	220208 kb
Host	smart-fd4f9cc9-7a85-4e23-820e-d1ab6fe9ee49
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=75897801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.75897801
Directory	/workspace/33.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/33.keymgr_kmac_rsp_err.1353858182
Short name	T193
Test name
Test status
Simulation time	1188429537 ps
CPU time	9.63 seconds
Started	Apr 20 04:08:18 PM PDT 24
Finished	Apr 20 04:08:29 PM PDT 24
Peak memory	214236 kb
Host	smart-6fb8dff7-cee9-4711-b633-00979627086b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1353858182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.1353858182
Directory	/workspace/33.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/33.keymgr_lc_disable.1318638306
Short name	T205
Test name
Test status
Simulation time	123422190 ps
CPU time	2.45 seconds
Started	Apr 20 04:08:12 PM PDT 24
Finished	Apr 20 04:08:15 PM PDT 24
Peak memory	215832 kb
Host	smart-2e89cd34-824a-4532-adee-d1a4f79a9199
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1318638306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.1318638306
Directory	/workspace/33.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/33.keymgr_random.1126593495
Short name	T913
Test name
Test status
Simulation time	3682531448 ps
CPU time	45.23 seconds
Started	Apr 20 04:08:09 PM PDT 24
Finished	Apr 20 04:08:55 PM PDT 24
Peak memory	208368 kb
Host	smart-9d10fd9e-ddca-489d-9e61-c6042427f9ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1126593495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.1126593495
Directory	/workspace/33.keymgr_random/latest

Test location	/workspace/coverage/default/33.keymgr_sideload.241702861
Short name	T568
Test name
Test status
Simulation time	202143363 ps
CPU time	2.8 seconds
Started	Apr 20 04:08:10 PM PDT 24
Finished	Apr 20 04:08:13 PM PDT 24
Peak memory	206900 kb
Host	smart-7b45c439-ac67-4234-b6a2-28b73b0d5bba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=241702861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.241702861
Directory	/workspace/33.keymgr_sideload/latest

Test location	/workspace/coverage/default/33.keymgr_sideload_aes.733617981
Short name	T965
Test name
Test status
Simulation time	47902975 ps
CPU time	2 seconds
Started	Apr 20 04:08:09 PM PDT 24
Finished	Apr 20 04:08:11 PM PDT 24
Peak memory	207312 kb
Host	smart-e0a50d5f-2d65-474a-80e7-2e6d04caef91
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733617981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.733617981
Directory	/workspace/33.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/33.keymgr_sideload_kmac.4144963216
Short name	T591
Test name
Test status
Simulation time	39335483 ps
CPU time	2.39 seconds
Started	Apr 20 04:08:10 PM PDT 24
Finished	Apr 20 04:08:13 PM PDT 24
Peak memory	206976 kb
Host	smart-90f122bc-ed3e-408a-9027-b8f4a4529c0e
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144963216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.4144963216
Directory	/workspace/33.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/33.keymgr_sideload_otbn.4038503417
Short name	T989
Test name
Test status
Simulation time	116511550 ps
CPU time	4.09 seconds
Started	Apr 20 04:08:10 PM PDT 24
Finished	Apr 20 04:08:15 PM PDT 24
Peak memory	208680 kb
Host	smart-cd289f69-304c-456a-9edb-86e88f8fc621
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038503417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.4038503417
Directory	/workspace/33.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/33.keymgr_sideload_protect.434383898
Short name	T688
Test name
Test status
Simulation time	381922712 ps
CPU time	4.61 seconds
Started	Apr 20 04:08:12 PM PDT 24
Finished	Apr 20 04:08:17 PM PDT 24
Peak memory	220476 kb
Host	smart-16e5657e-c07d-44c4-b5e8-fa30e33188d8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=434383898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.434383898
Directory	/workspace/33.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/33.keymgr_smoke.1872797459
Short name	T814
Test name
Test status
Simulation time	50714599 ps
CPU time	1.88 seconds
Started	Apr 20 04:08:10 PM PDT 24
Finished	Apr 20 04:08:12 PM PDT 24
Peak memory	206788 kb
Host	smart-07f69c84-7ef2-4184-a6d1-80fedc1c9649
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1872797459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.1872797459
Directory	/workspace/33.keymgr_smoke/latest

Test location	/workspace/coverage/default/33.keymgr_stress_all.1651834315
Short name	T303
Test name
Test status
Simulation time	86868365211 ps
CPU time	120.17 seconds
Started	Apr 20 04:08:14 PM PDT 24
Finished	Apr 20 04:10:14 PM PDT 24
Peak memory	217516 kb
Host	smart-7a40fbd5-716f-4768-9c05-9ec8137d8d8b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651834315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.1651834315
Directory	/workspace/33.keymgr_stress_all/latest

Test location	/workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.2136753764
Short name	T995
Test name
Test status
Simulation time	319744136 ps
CPU time	7.54 seconds
Started	Apr 20 04:08:13 PM PDT 24
Finished	Apr 20 04:08:21 PM PDT 24
Peak memory	219544 kb
Host	smart-5ab84d4b-0d02-4507-91b0-cae1f157a977
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136753764 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.2136753764
Directory	/workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/33.keymgr_sw_invalid_input.2506497060
Short name	T704
Test name
Test status
Simulation time	255610106 ps
CPU time	4.95 seconds
Started	Apr 20 04:08:12 PM PDT 24
Finished	Apr 20 04:08:17 PM PDT 24
Peak memory	207904 kb
Host	smart-8862d06b-c42f-4bb8-9f25-d90359591ccc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2506497060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.2506497060
Directory	/workspace/33.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/34.keymgr_alert_test.3755997966
Short name	T1054
Test name
Test status
Simulation time	12917363 ps
CPU time	0.89 seconds
Started	Apr 20 04:08:19 PM PDT 24
Finished	Apr 20 04:08:21 PM PDT 24
Peak memory	205904 kb
Host	smart-4a024282-a31c-48d3-9d4c-7c1caa3c582f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755997966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.3755997966
Directory	/workspace/34.keymgr_alert_test/latest

Test location	/workspace/coverage/default/34.keymgr_custom_cm.307689672
Short name	T9
Test name
Test status
Simulation time	1245342028 ps
CPU time	14.29 seconds
Started	Apr 20 04:08:15 PM PDT 24
Finished	Apr 20 04:08:30 PM PDT 24
Peak memory	214520 kb
Host	smart-d69e826a-1fea-420a-92f7-bb4c75611f49
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=307689672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.307689672
Directory	/workspace/34.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/34.keymgr_direct_to_disabled.650148920
Short name	T49
Test name
Test status
Simulation time	597594525 ps
CPU time	2.33 seconds
Started	Apr 20 04:08:19 PM PDT 24
Finished	Apr 20 04:08:22 PM PDT 24
Peak memory	209624 kb
Host	smart-de734d13-bf11-4062-9b0c-135d3cd9aa1f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=650148920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.650148920
Directory	/workspace/34.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/34.keymgr_hwsw_invalid_input.2194568225
Short name	T345
Test name
Test status
Simulation time	249207879 ps
CPU time	6.8 seconds
Started	Apr 20 04:08:18 PM PDT 24
Finished	Apr 20 04:08:26 PM PDT 24
Peak memory	209096 kb
Host	smart-57ab4ff6-341d-4b6e-ba34-e52d00fb9c4f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2194568225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.2194568225
Directory	/workspace/34.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/34.keymgr_lc_disable.3656207217
Short name	T600
Test name
Test status
Simulation time	279432905 ps
CPU time	3.65 seconds
Started	Apr 20 04:08:16 PM PDT 24
Finished	Apr 20 04:08:20 PM PDT 24
Peak memory	210564 kb
Host	smart-48917a5b-d1f9-4081-b297-4755cabbf2b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3656207217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.3656207217
Directory	/workspace/34.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/34.keymgr_random.889537068
Short name	T1021
Test name
Test status
Simulation time	80702626 ps
CPU time	4.21 seconds
Started	Apr 20 04:08:16 PM PDT 24
Finished	Apr 20 04:08:20 PM PDT 24
Peak memory	209232 kb
Host	smart-e2d98741-2cfc-4fcc-9fc6-b8abe5e874fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=889537068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.889537068
Directory	/workspace/34.keymgr_random/latest

Test location	/workspace/coverage/default/34.keymgr_sideload.1875318879
Short name	T661
Test name
Test status
Simulation time	1724628891 ps
CPU time	16.53 seconds
Started	Apr 20 04:08:19 PM PDT 24
Finished	Apr 20 04:08:36 PM PDT 24
Peak memory	208268 kb
Host	smart-9edf4e7b-7f2e-4695-98ea-b1d90c83e7d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1875318879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.1875318879
Directory	/workspace/34.keymgr_sideload/latest

Test location	/workspace/coverage/default/34.keymgr_sideload_aes.2002490695
Short name	T659
Test name
Test status
Simulation time	171938658 ps
CPU time	6.99 seconds
Started	Apr 20 04:08:12 PM PDT 24
Finished	Apr 20 04:08:19 PM PDT 24
Peak memory	208836 kb
Host	smart-cb16780c-231c-4747-9d23-5cbc2bc1599d
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002490695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.2002490695
Directory	/workspace/34.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/34.keymgr_sideload_kmac.450852116
Short name	T362
Test name
Test status
Simulation time	23839625 ps
CPU time	1.98 seconds
Started	Apr 20 04:08:13 PM PDT 24
Finished	Apr 20 04:08:15 PM PDT 24
Peak memory	208816 kb
Host	smart-79dbdf45-7fc2-444b-94e1-475c4e64e16d
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450852116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.450852116
Directory	/workspace/34.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/34.keymgr_sideload_otbn.2933100664
Short name	T397
Test name
Test status
Simulation time	803361484 ps
CPU time	8.95 seconds
Started	Apr 20 04:08:15 PM PDT 24
Finished	Apr 20 04:08:24 PM PDT 24
Peak memory	207756 kb
Host	smart-e16427a5-cd3e-4b97-b9e7-f569ae410d96
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933100664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.2933100664
Directory	/workspace/34.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/34.keymgr_sideload_protect.801058090
Short name	T311
Test name
Test status
Simulation time	57770601 ps
CPU time	2.81 seconds
Started	Apr 20 04:08:17 PM PDT 24
Finished	Apr 20 04:08:20 PM PDT 24
Peak memory	209096 kb
Host	smart-51fc80f1-7f43-4c1a-978f-15f4c99d3f00
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=801058090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.801058090
Directory	/workspace/34.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/34.keymgr_smoke.4111903658
Short name	T996
Test name
Test status
Simulation time	121976130 ps
CPU time	4.5 seconds
Started	Apr 20 04:08:18 PM PDT 24
Finished	Apr 20 04:08:23 PM PDT 24
Peak memory	208812 kb
Host	smart-b215af7c-ff63-4c75-8324-188cecdc9a4a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4111903658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.4111903658
Directory	/workspace/34.keymgr_smoke/latest

Test location	/workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.2305475674
Short name	T749
Test name
Test status
Simulation time	722936022 ps
CPU time	7.81 seconds
Started	Apr 20 04:08:19 PM PDT 24
Finished	Apr 20 04:08:28 PM PDT 24
Peak memory	220408 kb
Host	smart-e4577a11-e0c3-4ec6-8a05-354dd7d01236
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305475674 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.2305475674
Directory	/workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/34.keymgr_sw_invalid_input.2653657574
Short name	T648
Test name
Test status
Simulation time	3825765642 ps
CPU time	42.64 seconds
Started	Apr 20 04:08:17 PM PDT 24
Finished	Apr 20 04:09:00 PM PDT 24
Peak memory	218092 kb
Host	smart-11622604-7787-4a5e-9450-23879cf1cf6c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2653657574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.2653657574
Directory	/workspace/34.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/34.keymgr_sync_async_fault_cross.3214131956
Short name	T161
Test name
Test status
Simulation time	1040020313 ps
CPU time	4.9 seconds
Started	Apr 20 04:08:18 PM PDT 24
Finished	Apr 20 04:08:24 PM PDT 24
Peak memory	210036 kb
Host	smart-2443b147-fd21-4289-9293-916fa0e410c4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3214131956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.3214131956
Directory	/workspace/34.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/35.keymgr_alert_test.2261983686
Short name	T574
Test name
Test status
Simulation time	17220500 ps
CPU time	0.88 seconds
Started	Apr 20 04:08:22 PM PDT 24
Finished	Apr 20 04:08:24 PM PDT 24
Peak memory	205904 kb
Host	smart-46a044db-3e69-491c-9cc4-c84e15318ae6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261983686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.2261983686
Directory	/workspace/35.keymgr_alert_test/latest

Test location	/workspace/coverage/default/35.keymgr_cfg_regwen.1239007949
Short name	T350
Test name
Test status
Simulation time	103843766 ps
CPU time	4.13 seconds
Started	Apr 20 04:08:20 PM PDT 24
Finished	Apr 20 04:08:24 PM PDT 24
Peak memory	214968 kb
Host	smart-f10bee2e-0a27-4b8b-b818-cf59fb59ae0f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1239007949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.1239007949
Directory	/workspace/35.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/35.keymgr_custom_cm.779057161
Short name	T971
Test name
Test status
Simulation time	110033324 ps
CPU time	4.39 seconds
Started	Apr 20 04:08:22 PM PDT 24
Finished	Apr 20 04:08:27 PM PDT 24
Peak memory	219588 kb
Host	smart-ee58c22f-ff72-4bb1-8a78-028bea2d3a58
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=779057161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.779057161
Directory	/workspace/35.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/35.keymgr_direct_to_disabled.3921468680
Short name	T758
Test name
Test status
Simulation time	781691688 ps
CPU time	18.01 seconds
Started	Apr 20 04:08:18 PM PDT 24
Finished	Apr 20 04:08:36 PM PDT 24
Peak memory	218204 kb
Host	smart-25c1fd4e-2e6f-4b0c-bce6-b3228fd49fde
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3921468680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.3921468680
Directory	/workspace/35.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/35.keymgr_hwsw_invalid_input.4214288
Short name	T827
Test name
Test status
Simulation time	200730870 ps
CPU time	4.38 seconds
Started	Apr 20 04:08:23 PM PDT 24
Finished	Apr 20 04:08:28 PM PDT 24
Peak memory	208688 kb
Host	smart-7cbe86db-d606-4b22-9d84-4ae3ceeb142c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4214288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.4214288
Directory	/workspace/35.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/35.keymgr_lc_disable.3878765207
Short name	T792
Test name
Test status
Simulation time	1281938909 ps
CPU time	4.59 seconds
Started	Apr 20 04:08:25 PM PDT 24
Finished	Apr 20 04:08:29 PM PDT 24
Peak memory	208668 kb
Host	smart-0cc56c30-537a-46f0-b2c8-ae3851a49564
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3878765207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.3878765207
Directory	/workspace/35.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/35.keymgr_random.4250271324
Short name	T353
Test name
Test status
Simulation time	89847211 ps
CPU time	3.93 seconds
Started	Apr 20 04:08:17 PM PDT 24
Finished	Apr 20 04:08:21 PM PDT 24
Peak memory	218388 kb
Host	smart-5f9440c1-4aba-4d07-bc4b-3f4111cc9254
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4250271324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.4250271324
Directory	/workspace/35.keymgr_random/latest

Test location	/workspace/coverage/default/35.keymgr_sideload.826370748
Short name	T785
Test name
Test status
Simulation time	68294026 ps
CPU time	2.78 seconds
Started	Apr 20 04:08:22 PM PDT 24
Finished	Apr 20 04:08:26 PM PDT 24
Peak memory	206652 kb
Host	smart-fffbb602-e6e4-4b61-bc39-f9caa6146b61
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=826370748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.826370748
Directory	/workspace/35.keymgr_sideload/latest

Test location	/workspace/coverage/default/35.keymgr_sideload_aes.1074874752
Short name	T1064
Test name
Test status
Simulation time	122430343 ps
CPU time	2.48 seconds
Started	Apr 20 04:08:19 PM PDT 24
Finished	Apr 20 04:08:22 PM PDT 24
Peak memory	206984 kb
Host	smart-8634b1df-441a-4af1-a663-468b80efe374
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074874752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.1074874752
Directory	/workspace/35.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/35.keymgr_sideload_kmac.2036155927
Short name	T583
Test name
Test status
Simulation time	1097293220 ps
CPU time	32.39 seconds
Started	Apr 20 04:08:20 PM PDT 24
Finished	Apr 20 04:08:53 PM PDT 24
Peak memory	208140 kb
Host	smart-ebad63f0-def3-4ae9-9240-dae9fd44b32c
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036155927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.2036155927
Directory	/workspace/35.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/35.keymgr_sideload_otbn.2455277072
Short name	T791
Test name
Test status
Simulation time	163183855 ps
CPU time	2.7 seconds
Started	Apr 20 04:08:18 PM PDT 24
Finished	Apr 20 04:08:21 PM PDT 24
Peak memory	207496 kb
Host	smart-1f7dbdda-d593-4ebc-9029-3d64eb7e0bbe
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455277072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.2455277072
Directory	/workspace/35.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/35.keymgr_sideload_protect.2614736964
Short name	T642
Test name
Test status
Simulation time	143162568 ps
CPU time	3.81 seconds
Started	Apr 20 04:08:23 PM PDT 24
Finished	Apr 20 04:08:27 PM PDT 24
Peak memory	214260 kb
Host	smart-ed8dc90c-377c-4cae-9bf1-a1018603f1d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2614736964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.2614736964
Directory	/workspace/35.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/35.keymgr_smoke.1408744914
Short name	T842
Test name
Test status
Simulation time	386098937 ps
CPU time	4.24 seconds
Started	Apr 20 04:08:19 PM PDT 24
Finished	Apr 20 04:08:24 PM PDT 24
Peak memory	208708 kb
Host	smart-f09d7e18-422d-4845-b08c-338673e2b0d6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1408744914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.1408744914
Directory	/workspace/35.keymgr_smoke/latest

Test location	/workspace/coverage/default/35.keymgr_stress_all.1959745461
Short name	T846
Test name
Test status
Simulation time	490026880 ps
CPU time	20.73 seconds
Started	Apr 20 04:08:36 PM PDT 24
Finished	Apr 20 04:08:58 PM PDT 24
Peak memory	222604 kb
Host	smart-698747b9-105b-4c9c-93ce-5143a38c800f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959745461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.1959745461
Directory	/workspace/35.keymgr_stress_all/latest

Test location	/workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.239504352
Short name	T986
Test name
Test status
Simulation time	166658495 ps
CPU time	4.07 seconds
Started	Apr 20 04:08:24 PM PDT 24
Finished	Apr 20 04:08:28 PM PDT 24
Peak memory	218748 kb
Host	smart-8e2b5bd4-a146-4e8f-b1d3-f0e3037a8021
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239504352 -assert nopost proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.239504352
Directory	/workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/35.keymgr_sw_invalid_input.3398935193
Short name	T186
Test name
Test status
Simulation time	506840311 ps
CPU time	13.34 seconds
Started	Apr 20 04:08:22 PM PDT 24
Finished	Apr 20 04:08:36 PM PDT 24
Peak memory	208092 kb
Host	smart-26165849-c94f-48d7-9941-51a4851b2d20
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3398935193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.3398935193
Directory	/workspace/35.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/35.keymgr_sync_async_fault_cross.3159639930
Short name	T2
Test name
Test status
Simulation time	116813768 ps
CPU time	3.53 seconds
Started	Apr 20 04:08:21 PM PDT 24
Finished	Apr 20 04:08:25 PM PDT 24
Peak memory	209848 kb
Host	smart-1985f26b-823e-4c31-9457-979f9ebd2abc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3159639930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.3159639930
Directory	/workspace/35.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/36.keymgr_alert_test.3375775591
Short name	T572
Test name
Test status
Simulation time	61925526 ps
CPU time	0.77 seconds
Started	Apr 20 04:08:32 PM PDT 24
Finished	Apr 20 04:08:33 PM PDT 24
Peak memory	205800 kb
Host	smart-b18b391c-378c-4091-9ce4-a77f2d95d388
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375775591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.3375775591
Directory	/workspace/36.keymgr_alert_test/latest

Test location	/workspace/coverage/default/36.keymgr_cfg_regwen.1883062177
Short name	T351
Test name
Test status
Simulation time	169379267 ps
CPU time	3.18 seconds
Started	Apr 20 04:08:26 PM PDT 24
Finished	Apr 20 04:08:30 PM PDT 24
Peak memory	214360 kb
Host	smart-ee814f3b-045a-43ea-a91c-ea2dd6a604a6
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1883062177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.1883062177
Directory	/workspace/36.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/36.keymgr_custom_cm.1418805378
Short name	T708
Test name
Test status
Simulation time	68570365 ps
CPU time	3.48 seconds
Started	Apr 20 04:08:28 PM PDT 24
Finished	Apr 20 04:08:32 PM PDT 24
Peak memory	221880 kb
Host	smart-6a8c69f0-2ca6-4cc6-ace2-c1d56c96ce76
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1418805378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.1418805378
Directory	/workspace/36.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/36.keymgr_direct_to_disabled.937536591
Short name	T394
Test name
Test status
Simulation time	211103329 ps
CPU time	4.48 seconds
Started	Apr 20 04:08:27 PM PDT 24
Finished	Apr 20 04:08:32 PM PDT 24
Peak memory	222464 kb
Host	smart-1dfb0b15-cfeb-494c-9fa8-564b6f0830c6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=937536591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.937536591
Directory	/workspace/36.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/36.keymgr_hwsw_invalid_input.2765026252
Short name	T258
Test name
Test status
Simulation time	395137264 ps
CPU time	7.28 seconds
Started	Apr 20 04:08:26 PM PDT 24
Finished	Apr 20 04:08:33 PM PDT 24
Peak memory	214248 kb
Host	smart-b4a8ac6a-1f84-45c4-adcb-540d1721f52b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2765026252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.2765026252
Directory	/workspace/36.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/36.keymgr_kmac_rsp_err.3753124095
Short name	T185
Test name
Test status
Simulation time	3462941491 ps
CPU time	8.56 seconds
Started	Apr 20 04:08:27 PM PDT 24
Finished	Apr 20 04:08:36 PM PDT 24
Peak memory	211168 kb
Host	smart-be80ec68-fe89-4e61-bbc4-a7fbacf290fe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3753124095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.3753124095
Directory	/workspace/36.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/36.keymgr_lc_disable.973613123
Short name	T750
Test name
Test status
Simulation time	48886957 ps
CPU time	2.43 seconds
Started	Apr 20 04:08:26 PM PDT 24
Finished	Apr 20 04:08:29 PM PDT 24
Peak memory	209620 kb
Host	smart-aa49727e-0b26-4b26-a1fb-e877e43d1fcc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=973613123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.973613123
Directory	/workspace/36.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/36.keymgr_random.1410164322
Short name	T874
Test name
Test status
Simulation time	174581038 ps
CPU time	3.21 seconds
Started	Apr 20 04:08:26 PM PDT 24
Finished	Apr 20 04:08:30 PM PDT 24
Peak memory	207468 kb
Host	smart-c3498d76-82ab-45d4-9f33-582e40a9801a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1410164322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.1410164322
Directory	/workspace/36.keymgr_random/latest

Test location	/workspace/coverage/default/36.keymgr_sideload.1985251811
Short name	T908
Test name
Test status
Simulation time	2177115144 ps
CPU time	43.82 seconds
Started	Apr 20 04:08:25 PM PDT 24
Finished	Apr 20 04:09:09 PM PDT 24
Peak memory	209136 kb
Host	smart-69007c17-8f22-4487-b4b7-a15857bc6da6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1985251811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.1985251811
Directory	/workspace/36.keymgr_sideload/latest

Test location	/workspace/coverage/default/36.keymgr_sideload_aes.2061474334
Short name	T274
Test name
Test status
Simulation time	1039568887 ps
CPU time	7.23 seconds
Started	Apr 20 04:08:25 PM PDT 24
Finished	Apr 20 04:08:32 PM PDT 24
Peak memory	207976 kb
Host	smart-1eeed38c-1b01-4b96-a63a-791ccb869963
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061474334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.2061474334
Directory	/workspace/36.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/36.keymgr_sideload_kmac.166513082
Short name	T867
Test name
Test status
Simulation time	3174460645 ps
CPU time	24.85 seconds
Started	Apr 20 04:08:27 PM PDT 24
Finished	Apr 20 04:08:52 PM PDT 24
Peak memory	208176 kb
Host	smart-1f07f537-daa5-49d7-b0bc-64784f2f2c73
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166513082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.166513082
Directory	/workspace/36.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/36.keymgr_sideload_otbn.658680024
Short name	T233
Test name
Test status
Simulation time	258341176 ps
CPU time	3.2 seconds
Started	Apr 20 04:08:25 PM PDT 24
Finished	Apr 20 04:08:28 PM PDT 24
Peak memory	208392 kb
Host	smart-21a34af7-7aca-468d-9586-263647dc1779
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658680024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.658680024
Directory	/workspace/36.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/36.keymgr_smoke.657857539
Short name	T567
Test name
Test status
Simulation time	1020460881 ps
CPU time	3.76 seconds
Started	Apr 20 04:08:23 PM PDT 24
Finished	Apr 20 04:08:27 PM PDT 24
Peak memory	206732 kb
Host	smart-eb98b527-15ec-41d6-84b5-2c59603a176f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=657857539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.657857539
Directory	/workspace/36.keymgr_smoke/latest

Test location	/workspace/coverage/default/36.keymgr_stress_all.2307591685
Short name	T74
Test name
Test status
Simulation time	251637887 ps
CPU time	11.96 seconds
Started	Apr 20 04:08:30 PM PDT 24
Finished	Apr 20 04:08:42 PM PDT 24
Peak memory	215308 kb
Host	smart-2ac4161f-459a-46e2-a616-82decf47f6b9
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307591685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.2307591685
Directory	/workspace/36.keymgr_stress_all/latest

Test location	/workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.2365775679
Short name	T200
Test name
Test status
Simulation time	1015322552 ps
CPU time	7.46 seconds
Started	Apr 20 04:08:28 PM PDT 24
Finished	Apr 20 04:08:36 PM PDT 24
Peak memory	222556 kb
Host	smart-0ed8948d-76f2-404a-82a9-7dc2c2d69000
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365775679 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.2365775679
Directory	/workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/36.keymgr_sw_invalid_input.1515503547
Short name	T680
Test name
Test status
Simulation time	102927174 ps
CPU time	3.2 seconds
Started	Apr 20 04:08:26 PM PDT 24
Finished	Apr 20 04:08:29 PM PDT 24
Peak memory	207608 kb
Host	smart-5b6eb646-e2c3-4bf4-a5c8-1b41891230b3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1515503547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.1515503547
Directory	/workspace/36.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/36.keymgr_sync_async_fault_cross.3020920584
Short name	T956
Test name
Test status
Simulation time	27743831 ps
CPU time	1.47 seconds
Started	Apr 20 04:08:28 PM PDT 24
Finished	Apr 20 04:08:30 PM PDT 24
Peak memory	209852 kb
Host	smart-3cd3eccc-e518-485c-8572-b9a12efc89ab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3020920584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.3020920584
Directory	/workspace/36.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/37.keymgr_alert_test.1117600267
Short name	T765
Test name
Test status
Simulation time	42580696 ps
CPU time	0.78 seconds
Started	Apr 20 04:08:35 PM PDT 24
Finished	Apr 20 04:08:36 PM PDT 24
Peak memory	205848 kb
Host	smart-be5bd94a-c6b2-43d5-950a-20afa6a2e30e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117600267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.1117600267
Directory	/workspace/37.keymgr_alert_test/latest

Test location	/workspace/coverage/default/37.keymgr_custom_cm.2484559226
Short name	T629
Test name
Test status
Simulation time	122179540 ps
CPU time	3.56 seconds
Started	Apr 20 04:08:38 PM PDT 24
Finished	Apr 20 04:08:42 PM PDT 24
Peak memory	219016 kb
Host	smart-0621cee2-f4bd-422d-9adb-5206e859d1ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2484559226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.2484559226
Directory	/workspace/37.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/37.keymgr_direct_to_disabled.1213644163
Short name	T271
Test name
Test status
Simulation time	153170409 ps
CPU time	4.83 seconds
Started	Apr 20 04:08:33 PM PDT 24
Finished	Apr 20 04:08:38 PM PDT 24
Peak memory	214340 kb
Host	smart-e090128b-3c89-4cf2-b4c0-eeeedea0b150
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1213644163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.1213644163
Directory	/workspace/37.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/37.keymgr_hwsw_invalid_input.2210863786
Short name	T344
Test name
Test status
Simulation time	475748178 ps
CPU time	5.36 seconds
Started	Apr 20 04:08:36 PM PDT 24
Finished	Apr 20 04:08:42 PM PDT 24
Peak memory	222412 kb
Host	smart-edb47f53-f669-4c2d-a6a4-1bc699e5cde7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2210863786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.2210863786
Directory	/workspace/37.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/37.keymgr_kmac_rsp_err.2577267765
Short name	T253
Test name
Test status
Simulation time	616122952 ps
CPU time	6.57 seconds
Started	Apr 20 04:08:37 PM PDT 24
Finished	Apr 20 04:08:45 PM PDT 24
Peak memory	222424 kb
Host	smart-99f2231f-f467-469c-8415-7f560ffc6a9c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2577267765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.2577267765
Directory	/workspace/37.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/37.keymgr_lc_disable.1723103903
Short name	T812
Test name
Test status
Simulation time	78777220 ps
CPU time	3.19 seconds
Started	Apr 20 04:08:42 PM PDT 24
Finished	Apr 20 04:08:46 PM PDT 24
Peak memory	214384 kb
Host	smart-ccce7727-3ea4-450c-8608-432910b5a6fe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1723103903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.1723103903
Directory	/workspace/37.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/37.keymgr_random.4112233707
Short name	T379
Test name
Test status
Simulation time	1754633781 ps
CPU time	44.08 seconds
Started	Apr 20 04:08:34 PM PDT 24
Finished	Apr 20 04:09:19 PM PDT 24
Peak memory	208852 kb
Host	smart-d244436e-3ec0-43ce-b643-cfe4a891b1a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4112233707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.4112233707
Directory	/workspace/37.keymgr_random/latest

Test location	/workspace/coverage/default/37.keymgr_sideload.2947190166
Short name	T226
Test name
Test status
Simulation time	65341377 ps
CPU time	2.6 seconds
Started	Apr 20 04:08:32 PM PDT 24
Finished	Apr 20 04:08:35 PM PDT 24
Peak memory	206896 kb
Host	smart-38669299-8391-46ea-b214-e7481d80085d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2947190166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.2947190166
Directory	/workspace/37.keymgr_sideload/latest

Test location	/workspace/coverage/default/37.keymgr_sideload_aes.2646353676
Short name	T847
Test name
Test status
Simulation time	251657182 ps
CPU time	4.08 seconds
Started	Apr 20 04:08:32 PM PDT 24
Finished	Apr 20 04:08:37 PM PDT 24
Peak memory	208572 kb
Host	smart-119ac9c1-cd62-4662-a3d9-34953ed57be7
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646353676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.2646353676
Directory	/workspace/37.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/37.keymgr_sideload_kmac.4178542286
Short name	T883
Test name
Test status
Simulation time	133581267 ps
CPU time	5.29 seconds
Started	Apr 20 04:08:33 PM PDT 24
Finished	Apr 20 04:08:39 PM PDT 24
Peak memory	208548 kb
Host	smart-f240feec-deaa-46ba-8793-b6d93a5419d6
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178542286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.4178542286
Directory	/workspace/37.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/37.keymgr_sideload_otbn.3401605182
Short name	T707
Test name
Test status
Simulation time	97413982 ps
CPU time	4.27 seconds
Started	Apr 20 04:08:31 PM PDT 24
Finished	Apr 20 04:08:36 PM PDT 24
Peak memory	207228 kb
Host	smart-53153c27-7c61-4fdc-b912-47c4e9277c56
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401605182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.3401605182
Directory	/workspace/37.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/37.keymgr_sideload_protect.872122884
Short name	T754
Test name
Test status
Simulation time	223497104 ps
CPU time	2.18 seconds
Started	Apr 20 04:08:37 PM PDT 24
Finished	Apr 20 04:08:39 PM PDT 24
Peak memory	217648 kb
Host	smart-3ce3195f-72a8-4c50-83f2-0e83ed8d7e25
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=872122884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.872122884
Directory	/workspace/37.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/37.keymgr_smoke.3452278906
Short name	T192
Test name
Test status
Simulation time	676159192 ps
CPU time	4.57 seconds
Started	Apr 20 04:08:33 PM PDT 24
Finished	Apr 20 04:08:38 PM PDT 24
Peak memory	208172 kb
Host	smart-e80f9336-3e89-44e5-a840-c48f92291473
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3452278906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.3452278906
Directory	/workspace/37.keymgr_smoke/latest

Test location	/workspace/coverage/default/37.keymgr_stress_all.1236515843
Short name	T257
Test name
Test status
Simulation time	1847116826 ps
CPU time	26.17 seconds
Started	Apr 20 04:08:42 PM PDT 24
Finished	Apr 20 04:09:09 PM PDT 24
Peak memory	220216 kb
Host	smart-97279821-c614-4e1a-9790-e1f3bdf82435
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236515843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.1236515843
Directory	/workspace/37.keymgr_stress_all/latest

Test location	/workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.2191415958
Short name	T202
Test name
Test status
Simulation time	2146942063 ps
CPU time	5.5 seconds
Started	Apr 20 04:08:39 PM PDT 24
Finished	Apr 20 04:08:46 PM PDT 24
Peak memory	219328 kb
Host	smart-959c53ff-65f2-4441-98f6-b148b499cd3f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191415958 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.2191415958
Directory	/workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/37.keymgr_sw_invalid_input.104192583
Short name	T733
Test name
Test status
Simulation time	192637353 ps
CPU time	5.52 seconds
Started	Apr 20 04:08:37 PM PDT 24
Finished	Apr 20 04:08:43 PM PDT 24
Peak memory	207000 kb
Host	smart-4996362e-3f4e-42aa-aee6-49d53055ec27
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=104192583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.104192583
Directory	/workspace/37.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/37.keymgr_sync_async_fault_cross.2248399529
Short name	T662
Test name
Test status
Simulation time	47063487 ps
CPU time	1.58 seconds
Started	Apr 20 04:08:38 PM PDT 24
Finished	Apr 20 04:08:40 PM PDT 24
Peak memory	208748 kb
Host	smart-75557a5f-ba3c-40a6-bfca-aedfa4763e0c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2248399529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.2248399529
Directory	/workspace/37.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/38.keymgr_alert_test.3187534189
Short name	T722
Test name
Test status
Simulation time	37932288 ps
CPU time	0.81 seconds
Started	Apr 20 04:08:40 PM PDT 24
Finished	Apr 20 04:08:42 PM PDT 24
Peak memory	205816 kb
Host	smart-4eb1c2d3-e52a-490d-9690-1a70f8f6c95a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187534189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.3187534189
Directory	/workspace/38.keymgr_alert_test/latest

Test location	/workspace/coverage/default/38.keymgr_cfg_regwen.1756783162
Short name	T366
Test name
Test status
Simulation time	231596023 ps
CPU time	4.37 seconds
Started	Apr 20 04:08:39 PM PDT 24
Finished	Apr 20 04:08:44 PM PDT 24
Peak memory	215072 kb
Host	smart-1018df4a-f9bc-493e-9774-5783a9e95208
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1756783162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.1756783162
Directory	/workspace/38.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/38.keymgr_custom_cm.2989168732
Short name	T955
Test name
Test status
Simulation time	644725008 ps
CPU time	6.36 seconds
Started	Apr 20 04:08:40 PM PDT 24
Finished	Apr 20 04:08:47 PM PDT 24
Peak memory	210500 kb
Host	smart-bda1e132-2079-4efc-80a3-4c7a0d7104ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2989168732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.2989168732
Directory	/workspace/38.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/38.keymgr_direct_to_disabled.2980041005
Short name	T58
Test name
Test status
Simulation time	177675624 ps
CPU time	4.97 seconds
Started	Apr 20 04:08:40 PM PDT 24
Finished	Apr 20 04:08:46 PM PDT 24
Peak memory	208956 kb
Host	smart-e86d2b3f-e50c-434d-9890-9b4ba71eff7b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2980041005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.2980041005
Directory	/workspace/38.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/38.keymgr_hwsw_invalid_input.2347124165
Short name	T232
Test name
Test status
Simulation time	127027497 ps
CPU time	5.42 seconds
Started	Apr 20 04:08:41 PM PDT 24
Finished	Apr 20 04:08:47 PM PDT 24
Peak memory	221452 kb
Host	smart-d66a7fe3-a5f6-41c4-897f-42dcfee6d655
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2347124165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.2347124165
Directory	/workspace/38.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/38.keymgr_kmac_rsp_err.1365923150
Short name	T252
Test name
Test status
Simulation time	158685688 ps
CPU time	5.91 seconds
Started	Apr 20 04:08:42 PM PDT 24
Finished	Apr 20 04:08:49 PM PDT 24
Peak memory	214360 kb
Host	smart-b7ecbfa4-431e-4cc3-9bf5-6b3b9392dadf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1365923150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.1365923150
Directory	/workspace/38.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/38.keymgr_lc_disable.4146197068
Short name	T1027
Test name
Test status
Simulation time	257092221 ps
CPU time	2.9 seconds
Started	Apr 20 04:08:42 PM PDT 24
Finished	Apr 20 04:08:46 PM PDT 24
Peak memory	214664 kb
Host	smart-43b45055-c43b-453f-9fa1-19ac40f9fe61
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4146197068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.4146197068
Directory	/workspace/38.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/38.keymgr_random.1876382546
Short name	T314
Test name
Test status
Simulation time	6995516968 ps
CPU time	44.62 seconds
Started	Apr 20 04:08:38 PM PDT 24
Finished	Apr 20 04:09:23 PM PDT 24
Peak memory	210272 kb
Host	smart-d8485fc8-83f5-47b2-a79d-2f2f3a3d0c21
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1876382546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.1876382546
Directory	/workspace/38.keymgr_random/latest

Test location	/workspace/coverage/default/38.keymgr_sideload.1210272909
Short name	T966
Test name
Test status
Simulation time	187334864 ps
CPU time	3.49 seconds
Started	Apr 20 04:08:38 PM PDT 24
Finished	Apr 20 04:08:41 PM PDT 24
Peak memory	208528 kb
Host	smart-7db1b6e6-eb97-4567-ad0d-647a43ade562
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1210272909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.1210272909
Directory	/workspace/38.keymgr_sideload/latest

Test location	/workspace/coverage/default/38.keymgr_sideload_aes.1755365295
Short name	T866
Test name
Test status
Simulation time	181449208 ps
CPU time	5.62 seconds
Started	Apr 20 04:08:39 PM PDT 24
Finished	Apr 20 04:08:45 PM PDT 24
Peak memory	208428 kb
Host	smart-72a57cea-1879-42bd-9d27-8c0fcc06b38b
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755365295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.1755365295
Directory	/workspace/38.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/38.keymgr_sideload_kmac.3545176658
Short name	T936
Test name
Test status
Simulation time	102022160 ps
CPU time	4.02 seconds
Started	Apr 20 04:08:42 PM PDT 24
Finished	Apr 20 04:08:47 PM PDT 24
Peak memory	206872 kb
Host	smart-82b7f8ca-df61-4cc2-a30d-6c9281132df5
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545176658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.3545176658
Directory	/workspace/38.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/38.keymgr_sideload_otbn.2903537153
Short name	T809
Test name
Test status
Simulation time	150231848 ps
CPU time	2.44 seconds
Started	Apr 20 04:08:38 PM PDT 24
Finished	Apr 20 04:08:41 PM PDT 24
Peak memory	206412 kb
Host	smart-036a86c9-a313-47e7-b8d2-7e97c82e1a21
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903537153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.2903537153
Directory	/workspace/38.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/38.keymgr_sideload_protect.4130967054
Short name	T76
Test name
Test status
Simulation time	296762971 ps
CPU time	2.93 seconds
Started	Apr 20 04:08:40 PM PDT 24
Finished	Apr 20 04:08:44 PM PDT 24
Peak memory	210404 kb
Host	smart-ac5ff2a5-615e-4588-9d81-5b125df2ccf0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4130967054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.4130967054
Directory	/workspace/38.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/38.keymgr_smoke.1621031325
Short name	T595
Test name
Test status
Simulation time	350339139 ps
CPU time	3.12 seconds
Started	Apr 20 04:08:37 PM PDT 24
Finished	Apr 20 04:08:41 PM PDT 24
Peak memory	206756 kb
Host	smart-b2752630-d0ab-4cb3-854c-7160ec39fd62
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1621031325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.1621031325
Directory	/workspace/38.keymgr_smoke/latest

Test location	/workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.1903973092
Short name	T873
Test name
Test status
Simulation time	274747739 ps
CPU time	6.44 seconds
Started	Apr 20 04:08:42 PM PDT 24
Finished	Apr 20 04:08:49 PM PDT 24
Peak memory	218796 kb
Host	smart-381a0c3f-eee9-454c-b893-108ca8a209ba
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903973092 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.1903973092
Directory	/workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/38.keymgr_sw_invalid_input.1596299199
Short name	T597
Test name
Test status
Simulation time	186841475 ps
CPU time	3.62 seconds
Started	Apr 20 04:08:42 PM PDT 24
Finished	Apr 20 04:08:46 PM PDT 24
Peak memory	207516 kb
Host	smart-ab258516-4a99-4505-9df3-a737c1c068a2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1596299199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.1596299199
Directory	/workspace/38.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/38.keymgr_sync_async_fault_cross.3014400284
Short name	T386
Test name
Test status
Simulation time	419509519 ps
CPU time	2.95 seconds
Started	Apr 20 04:08:39 PM PDT 24
Finished	Apr 20 04:08:43 PM PDT 24
Peak memory	210388 kb
Host	smart-919463b4-f01e-4637-9753-3bf60f4c7896
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3014400284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.3014400284
Directory	/workspace/38.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/39.keymgr_alert_test.664937907
Short name	T582
Test name
Test status
Simulation time	9487032 ps
CPU time	0.69 seconds
Started	Apr 20 04:08:44 PM PDT 24
Finished	Apr 20 04:08:45 PM PDT 24
Peak memory	205892 kb
Host	smart-3bd4b7e1-5286-4f61-99ae-cc9f0879b059
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664937907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.664937907
Directory	/workspace/39.keymgr_alert_test/latest

Test location	/workspace/coverage/default/39.keymgr_cfg_regwen.1727197546
Short name	T401
Test name
Test status
Simulation time	237010112 ps
CPU time	12.55 seconds
Started	Apr 20 04:08:44 PM PDT 24
Finished	Apr 20 04:08:57 PM PDT 24
Peak memory	222404 kb
Host	smart-e6e28119-fd19-46a8-b411-da4ad38c1fa0
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1727197546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.1727197546
Directory	/workspace/39.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/39.keymgr_custom_cm.4123504898
Short name	T23
Test name
Test status
Simulation time	106063346 ps
CPU time	2.18 seconds
Started	Apr 20 04:08:45 PM PDT 24
Finished	Apr 20 04:08:48 PM PDT 24
Peak memory	207840 kb
Host	smart-98498773-c674-48c4-b677-600ef57eaf5f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4123504898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.4123504898
Directory	/workspace/39.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/39.keymgr_direct_to_disabled.2647416477
Short name	T937
Test name
Test status
Simulation time	8969194660 ps
CPU time	27.94 seconds
Started	Apr 20 04:08:42 PM PDT 24
Finished	Apr 20 04:09:11 PM PDT 24
Peak memory	208664 kb
Host	smart-80c488f3-ccef-4f32-b07c-920cc7a4ce45
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2647416477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.2647416477
Directory	/workspace/39.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/39.keymgr_hwsw_invalid_input.749449735
Short name	T861
Test name
Test status
Simulation time	62536714 ps
CPU time	3.33 seconds
Started	Apr 20 04:08:43 PM PDT 24
Finished	Apr 20 04:08:47 PM PDT 24
Peak memory	220588 kb
Host	smart-1354129c-3068-4d80-863c-23fb71aeafe8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=749449735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.749449735
Directory	/workspace/39.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/39.keymgr_kmac_rsp_err.352701094
Short name	T378
Test name
Test status
Simulation time	1300079623 ps
CPU time	6.35 seconds
Started	Apr 20 04:08:42 PM PDT 24
Finished	Apr 20 04:08:49 PM PDT 24
Peak memory	222328 kb
Host	smart-0e05349c-f893-47c9-af0f-097e6d9c7986
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=352701094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.352701094
Directory	/workspace/39.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/39.keymgr_lc_disable.2017487726
Short name	T43
Test name
Test status
Simulation time	331870219 ps
CPU time	6.29 seconds
Started	Apr 20 04:08:42 PM PDT 24
Finished	Apr 20 04:08:50 PM PDT 24
Peak memory	222416 kb
Host	smart-b9a4395c-eabb-4447-b160-d5007133081b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2017487726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.2017487726
Directory	/workspace/39.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/39.keymgr_random.2018969719
Short name	T256
Test name
Test status
Simulation time	878361121 ps
CPU time	9.23 seconds
Started	Apr 20 04:08:45 PM PDT 24
Finished	Apr 20 04:08:55 PM PDT 24
Peak memory	214092 kb
Host	smart-982b2125-6d0b-4175-878c-2b92249db231
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2018969719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.2018969719
Directory	/workspace/39.keymgr_random/latest

Test location	/workspace/coverage/default/39.keymgr_sideload.3026743707
Short name	T961
Test name
Test status
Simulation time	898932593 ps
CPU time	21.61 seconds
Started	Apr 20 04:08:39 PM PDT 24
Finished	Apr 20 04:09:01 PM PDT 24
Peak memory	208328 kb
Host	smart-1627d933-07e6-4cad-bf54-6d4484e2715a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3026743707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.3026743707
Directory	/workspace/39.keymgr_sideload/latest

Test location	/workspace/coverage/default/39.keymgr_sideload_aes.1958180002
Short name	T613
Test name
Test status
Simulation time	1122199467 ps
CPU time	9.69 seconds
Started	Apr 20 04:08:41 PM PDT 24
Finished	Apr 20 04:08:51 PM PDT 24
Peak memory	208700 kb
Host	smart-3b39382c-de43-4e2f-8ab8-62b15c6c0ca4
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958180002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.1958180002
Directory	/workspace/39.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/39.keymgr_sideload_kmac.3762983547
Short name	T943
Test name
Test status
Simulation time	40841967 ps
CPU time	2.74 seconds
Started	Apr 20 04:08:42 PM PDT 24
Finished	Apr 20 04:08:46 PM PDT 24
Peak memory	208600 kb
Host	smart-b93e6c69-ee3c-4ecc-b71c-b22b169a1d99
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762983547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.3762983547
Directory	/workspace/39.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/39.keymgr_sideload_otbn.3870196565
Short name	T603
Test name
Test status
Simulation time	92255345 ps
CPU time	3.33 seconds
Started	Apr 20 04:08:40 PM PDT 24
Finished	Apr 20 04:08:44 PM PDT 24
Peak memory	208908 kb
Host	smart-6fdc5631-c5fa-436c-b2b2-d656f6cb97a7
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870196565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.3870196565
Directory	/workspace/39.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/39.keymgr_sideload_protect.1678395341
Short name	T1057
Test name
Test status
Simulation time	638667172 ps
CPU time	10.65 seconds
Started	Apr 20 04:08:43 PM PDT 24
Finished	Apr 20 04:08:54 PM PDT 24
Peak memory	209656 kb
Host	smart-b8e2658d-5cd4-48f4-9bf7-d9b217d801a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1678395341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.1678395341
Directory	/workspace/39.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/39.keymgr_smoke.591998832
Short name	T618
Test name
Test status
Simulation time	1000841101 ps
CPU time	28.62 seconds
Started	Apr 20 04:08:40 PM PDT 24
Finished	Apr 20 04:09:09 PM PDT 24
Peak memory	208632 kb
Host	smart-5cd5ec4f-5bb8-423b-8909-00c4997a3728
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=591998832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.591998832
Directory	/workspace/39.keymgr_smoke/latest

Test location	/workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.1258849519
Short name	T381
Test name
Test status
Simulation time	273990119 ps
CPU time	11.43 seconds
Started	Apr 20 04:08:42 PM PDT 24
Finished	Apr 20 04:08:55 PM PDT 24
Peak memory	222556 kb
Host	smart-c56e639e-34ac-4cfe-a722-027d4d2d8baf
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258849519 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.1258849519
Directory	/workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/39.keymgr_sw_invalid_input.1117540784
Short name	T244
Test name
Test status
Simulation time	236639672 ps
CPU time	3.38 seconds
Started	Apr 20 04:08:45 PM PDT 24
Finished	Apr 20 04:08:48 PM PDT 24
Peak memory	207516 kb
Host	smart-cbf0e0be-33e9-4fea-bd67-baaff195aff1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1117540784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.1117540784
Directory	/workspace/39.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/39.keymgr_sync_async_fault_cross.2396201341
Short name	T808
Test name
Test status
Simulation time	91879770 ps
CPU time	1.94 seconds
Started	Apr 20 04:08:42 PM PDT 24
Finished	Apr 20 04:08:45 PM PDT 24
Peak memory	210100 kb
Host	smart-f5f87609-2b3b-4cf0-808c-548aa846e9af
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2396201341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.2396201341
Directory	/workspace/39.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/4.keymgr_alert_test.666983193
Short name	T1009
Test name
Test status
Simulation time	17552341 ps
CPU time	0.95 seconds
Started	Apr 20 04:05:11 PM PDT 24
Finished	Apr 20 04:05:12 PM PDT 24
Peak memory	206000 kb
Host	smart-99a255a7-a4ea-4097-a08c-2d715143fdba
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666983193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.666983193
Directory	/workspace/4.keymgr_alert_test/latest

Test location	/workspace/coverage/default/4.keymgr_cfg_regwen.2013773410
Short name	T354
Test name
Test status
Simulation time	89286474 ps
CPU time	5.01 seconds
Started	Apr 20 04:05:00 PM PDT 24
Finished	Apr 20 04:05:05 PM PDT 24
Peak memory	215240 kb
Host	smart-b09d85e8-a53b-4ff8-ad9d-b35586739a50
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2013773410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.2013773410
Directory	/workspace/4.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/4.keymgr_direct_to_disabled.2474884935
Short name	T768
Test name
Test status
Simulation time	455205321 ps
CPU time	3.06 seconds
Started	Apr 20 04:05:02 PM PDT 24
Finished	Apr 20 04:05:05 PM PDT 24
Peak memory	208536 kb
Host	smart-2f9b2740-7a42-4357-a044-d451aa156d0a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2474884935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.2474884935
Directory	/workspace/4.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/4.keymgr_hwsw_invalid_input.1564465109
Short name	T361
Test name
Test status
Simulation time	58097203 ps
CPU time	3.4 seconds
Started	Apr 20 04:05:02 PM PDT 24
Finished	Apr 20 04:05:06 PM PDT 24
Peak memory	219056 kb
Host	smart-e01ad1eb-6a0d-49a7-94f0-35aa4ec513d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1564465109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.1564465109
Directory	/workspace/4.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/4.keymgr_kmac_rsp_err.887873707
Short name	T28
Test name
Test status
Simulation time	136147903 ps
CPU time	6.33 seconds
Started	Apr 20 04:05:03 PM PDT 24
Finished	Apr 20 04:05:10 PM PDT 24
Peak memory	222356 kb
Host	smart-a63aa0a3-c57c-41d5-ab56-92df59a53785
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=887873707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.887873707
Directory	/workspace/4.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/4.keymgr_lc_disable.3595784102
Short name	T235
Test name
Test status
Simulation time	463762297 ps
CPU time	4.06 seconds
Started	Apr 20 04:05:03 PM PDT 24
Finished	Apr 20 04:05:08 PM PDT 24
Peak memory	209612 kb
Host	smart-33877ec1-597d-47fa-bdb7-76c002829790
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3595784102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.3595784102
Directory	/workspace/4.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/4.keymgr_random.3981633617
Short name	T974
Test name
Test status
Simulation time	195451480 ps
CPU time	7.19 seconds
Started	Apr 20 04:05:00 PM PDT 24
Finished	Apr 20 04:05:07 PM PDT 24
Peak memory	208692 kb
Host	smart-99bc1dbd-e1f0-4487-860b-fda2f95aece1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3981633617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.3981633617
Directory	/workspace/4.keymgr_random/latest

Test location	/workspace/coverage/default/4.keymgr_sec_cm.4026969999
Short name	T106
Test name
Test status
Simulation time	2774685651 ps
CPU time	24.16 seconds
Started	Apr 20 04:05:09 PM PDT 24
Finished	Apr 20 04:05:33 PM PDT 24
Peak memory	232976 kb
Host	smart-465b542b-482d-4e4a-8ad4-a7f7b593550f
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026969999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.4026969999
Directory	/workspace/4.keymgr_sec_cm/latest

Test location	/workspace/coverage/default/4.keymgr_sideload.2231339039
Short name	T80
Test name
Test status
Simulation time	1150464775 ps
CPU time	26.2 seconds
Started	Apr 20 04:04:59 PM PDT 24
Finished	Apr 20 04:05:25 PM PDT 24
Peak memory	208804 kb
Host	smart-0627030d-ae54-4c00-8681-1db779cd99e9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2231339039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.2231339039
Directory	/workspace/4.keymgr_sideload/latest

Test location	/workspace/coverage/default/4.keymgr_sideload_aes.634148681
Short name	T1041
Test name
Test status
Simulation time	3642181768 ps
CPU time	45.18 seconds
Started	Apr 20 04:05:03 PM PDT 24
Finished	Apr 20 04:05:48 PM PDT 24
Peak memory	208788 kb
Host	smart-23ad88d7-5ed7-4334-b67d-ddb2f575e023
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634148681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.634148681
Directory	/workspace/4.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/4.keymgr_sideload_kmac.2668384095
Short name	T922
Test name
Test status
Simulation time	373635311 ps
CPU time	4.5 seconds
Started	Apr 20 04:04:56 PM PDT 24
Finished	Apr 20 04:05:01 PM PDT 24
Peak memory	208872 kb
Host	smart-c6587739-2984-460d-8e97-5f1916937b41
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668384095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.2668384095
Directory	/workspace/4.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/4.keymgr_sideload_otbn.349839330
Short name	T227
Test name
Test status
Simulation time	447988547 ps
CPU time	2.67 seconds
Started	Apr 20 04:05:01 PM PDT 24
Finished	Apr 20 04:05:05 PM PDT 24
Peak memory	206940 kb
Host	smart-09c05cd5-16cc-4901-95ad-fe938d213412
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349839330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.349839330
Directory	/workspace/4.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/4.keymgr_sideload_protect.1162499405
Short name	T109
Test name
Test status
Simulation time	246529809 ps
CPU time	2.55 seconds
Started	Apr 20 04:05:03 PM PDT 24
Finished	Apr 20 04:05:06 PM PDT 24
Peak memory	208572 kb
Host	smart-ca4d396a-eaae-43b0-9cee-d83712f5c945
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1162499405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.1162499405
Directory	/workspace/4.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/4.keymgr_smoke.1074173936
Short name	T829
Test name
Test status
Simulation time	364355437 ps
CPU time	1.85 seconds
Started	Apr 20 04:04:57 PM PDT 24
Finished	Apr 20 04:04:59 PM PDT 24
Peak memory	206956 kb
Host	smart-5b1f2c7e-ec30-4596-bdee-834abcbece8f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1074173936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.1074173936
Directory	/workspace/4.keymgr_smoke/latest

Test location	/workspace/coverage/default/4.keymgr_stress_all.875950916
Short name	T219
Test name
Test status
Simulation time	534019496 ps
CPU time	10.15 seconds
Started	Apr 20 04:05:10 PM PDT 24
Finished	Apr 20 04:05:20 PM PDT 24
Peak memory	220436 kb
Host	smart-4f955b61-64b5-4246-8f4f-910382dae531
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875950916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.875950916
Directory	/workspace/4.keymgr_stress_all/latest

Test location	/workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.568940478
Short name	T1030
Test name
Test status
Simulation time	202207431 ps
CPU time	8.81 seconds
Started	Apr 20 04:05:09 PM PDT 24
Finished	Apr 20 04:05:18 PM PDT 24
Peak memory	222632 kb
Host	smart-61dad786-a546-44eb-b4d8-82747a30ea53
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568940478 -assert nopost proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.568940478
Directory	/workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/4.keymgr_sw_invalid_input.2714723739
Short name	T819
Test name
Test status
Simulation time	193053849 ps
CPU time	5.71 seconds
Started	Apr 20 04:05:04 PM PDT 24
Finished	Apr 20 04:05:10 PM PDT 24
Peak memory	218128 kb
Host	smart-2dca9f6d-f9a3-45d7-bf5d-25b7bf10ea5d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2714723739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.2714723739
Directory	/workspace/4.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/4.keymgr_sync_async_fault_cross.3363787122
Short name	T55
Test name
Test status
Simulation time	1040825612 ps
CPU time	3.07 seconds
Started	Apr 20 04:05:02 PM PDT 24
Finished	Apr 20 04:05:06 PM PDT 24
Peak memory	210956 kb
Host	smart-bd76796a-0f51-4e6d-989f-f9a13d7701aa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3363787122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.3363787122
Directory	/workspace/4.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/40.keymgr_alert_test.320489239
Short name	T554
Test name
Test status
Simulation time	11840818 ps
CPU time	0.85 seconds
Started	Apr 20 04:08:49 PM PDT 24
Finished	Apr 20 04:08:50 PM PDT 24
Peak memory	205816 kb
Host	smart-0535d5bd-eb71-4950-98fd-f81ec06f8e9e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320489239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.320489239
Directory	/workspace/40.keymgr_alert_test/latest

Test location	/workspace/coverage/default/40.keymgr_cfg_regwen.3325949639
Short name	T419
Test name
Test status
Simulation time	225602164 ps
CPU time	4.24 seconds
Started	Apr 20 04:08:49 PM PDT 24
Finished	Apr 20 04:08:53 PM PDT 24
Peak memory	215036 kb
Host	smart-ffc53924-0dd3-4ed0-a1b1-3f99eea997f5
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3325949639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.3325949639
Directory	/workspace/40.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/40.keymgr_custom_cm.568180416
Short name	T22
Test name
Test status
Simulation time	137724281 ps
CPU time	2.54 seconds
Started	Apr 20 04:08:48 PM PDT 24
Finished	Apr 20 04:08:51 PM PDT 24
Peak memory	215708 kb
Host	smart-4b93b4bd-10c3-43c2-a1ee-b46c8bb4efd4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=568180416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.568180416
Directory	/workspace/40.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/40.keymgr_direct_to_disabled.2835641127
Short name	T4
Test name
Test status
Simulation time	162605053 ps
CPU time	2.45 seconds
Started	Apr 20 04:08:49 PM PDT 24
Finished	Apr 20 04:08:52 PM PDT 24
Peak memory	208072 kb
Host	smart-3ec1a4cd-900c-4050-ac8f-1cdc328f2fc8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2835641127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.2835641127
Directory	/workspace/40.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/40.keymgr_hwsw_invalid_input.3773003074
Short name	T822
Test name
Test status
Simulation time	1358603601 ps
CPU time	8.52 seconds
Started	Apr 20 04:08:46 PM PDT 24
Finished	Apr 20 04:08:55 PM PDT 24
Peak memory	214448 kb
Host	smart-77f168fb-2b2a-4922-bf1f-f04d837ca4ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3773003074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.3773003074
Directory	/workspace/40.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/40.keymgr_kmac_rsp_err.69345711
Short name	T360
Test name
Test status
Simulation time	318782191 ps
CPU time	12.44 seconds
Started	Apr 20 04:08:47 PM PDT 24
Finished	Apr 20 04:08:59 PM PDT 24
Peak memory	214204 kb
Host	smart-f8b4e218-29dc-46a7-98f8-3b8f37b5762b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=69345711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.69345711
Directory	/workspace/40.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/40.keymgr_lc_disable.2136880707
Short name	T981
Test name
Test status
Simulation time	69300133 ps
CPU time	3.9 seconds
Started	Apr 20 04:08:48 PM PDT 24
Finished	Apr 20 04:08:52 PM PDT 24
Peak memory	209740 kb
Host	smart-495b0ac2-a75b-497f-8912-490e5615d8e6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2136880707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.2136880707
Directory	/workspace/40.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/40.keymgr_random.388942051
Short name	T79
Test name
Test status
Simulation time	68516763 ps
CPU time	2.71 seconds
Started	Apr 20 04:08:47 PM PDT 24
Finished	Apr 20 04:08:50 PM PDT 24
Peak memory	210104 kb
Host	smart-8b3a83d2-269a-40c7-b6bc-9be62d8ab454
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=388942051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.388942051
Directory	/workspace/40.keymgr_random/latest

Test location	/workspace/coverage/default/40.keymgr_sideload.2181820972
Short name	T649
Test name
Test status
Simulation time	349379408 ps
CPU time	7.85 seconds
Started	Apr 20 04:08:45 PM PDT 24
Finished	Apr 20 04:08:53 PM PDT 24
Peak memory	208284 kb
Host	smart-9ea87bba-6553-47c8-b67b-aec6a4ee7f6c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2181820972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.2181820972
Directory	/workspace/40.keymgr_sideload/latest

Test location	/workspace/coverage/default/40.keymgr_sideload_aes.1299004552
Short name	T950
Test name
Test status
Simulation time	75917230 ps
CPU time	3.44 seconds
Started	Apr 20 04:08:46 PM PDT 24
Finished	Apr 20 04:08:50 PM PDT 24
Peak memory	207840 kb
Host	smart-7af1b22a-b830-4588-81ca-ec45978a94d8
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299004552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.1299004552
Directory	/workspace/40.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/40.keymgr_sideload_kmac.3137912077
Short name	T1053
Test name
Test status
Simulation time	61521809 ps
CPU time	3.2 seconds
Started	Apr 20 04:08:48 PM PDT 24
Finished	Apr 20 04:08:51 PM PDT 24
Peak memory	208800 kb
Host	smart-da534efd-5d2e-4d40-9c2f-a794f3f33f2e
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137912077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.3137912077
Directory	/workspace/40.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/40.keymgr_sideload_otbn.466809194
Short name	T611
Test name
Test status
Simulation time	72418686 ps
CPU time	3.03 seconds
Started	Apr 20 04:08:49 PM PDT 24
Finished	Apr 20 04:08:52 PM PDT 24
Peak memory	206860 kb
Host	smart-1f395d61-96ae-49ac-a68f-a9e11c3bc0bb
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466809194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.466809194
Directory	/workspace/40.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/40.keymgr_sideload_protect.1572943514
Short name	T732
Test name
Test status
Simulation time	117428847 ps
CPU time	3.47 seconds
Started	Apr 20 04:08:49 PM PDT 24
Finished	Apr 20 04:08:53 PM PDT 24
Peak memory	218424 kb
Host	smart-7568b490-2a3d-41ec-8f56-711d427a2f57
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1572943514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.1572943514
Directory	/workspace/40.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/40.keymgr_smoke.3905654996
Short name	T596
Test name
Test status
Simulation time	411442252 ps
CPU time	3.96 seconds
Started	Apr 20 04:08:48 PM PDT 24
Finished	Apr 20 04:08:52 PM PDT 24
Peak memory	208556 kb
Host	smart-dae93996-0881-4d3a-a984-fa42acd7a865
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3905654996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.3905654996
Directory	/workspace/40.keymgr_smoke/latest

Test location	/workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.3653380188
Short name	T953
Test name
Test status
Simulation time	132387243 ps
CPU time	2.57 seconds
Started	Apr 20 04:08:48 PM PDT 24
Finished	Apr 20 04:08:51 PM PDT 24
Peak memory	222572 kb
Host	smart-b4709ddd-ffc7-4356-8ef4-98eaf8c3e9d8
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653380188 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.3653380188
Directory	/workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/40.keymgr_sw_invalid_input.1183744329
Short name	T270
Test name
Test status
Simulation time	60254642 ps
CPU time	3.33 seconds
Started	Apr 20 04:08:46 PM PDT 24
Finished	Apr 20 04:08:49 PM PDT 24
Peak memory	209656 kb
Host	smart-3f032d91-0397-4376-8f33-b9bd9000f3b2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1183744329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.1183744329
Directory	/workspace/40.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/40.keymgr_sync_async_fault_cross.1674024612
Short name	T911
Test name
Test status
Simulation time	234834006 ps
CPU time	2.09 seconds
Started	Apr 20 04:08:50 PM PDT 24
Finished	Apr 20 04:08:53 PM PDT 24
Peak memory	210076 kb
Host	smart-3a46cc9f-2029-4196-92e7-d4cc9f3d09b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1674024612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.1674024612
Directory	/workspace/40.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/41.keymgr_alert_test.487460212
Short name	T988
Test name
Test status
Simulation time	8645765 ps
CPU time	0.79 seconds
Started	Apr 20 04:08:57 PM PDT 24
Finished	Apr 20 04:08:58 PM PDT 24
Peak memory	205872 kb
Host	smart-193faa65-2d26-4c05-91c4-a0b18d8b6ef7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487460212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.487460212
Directory	/workspace/41.keymgr_alert_test/latest

Test location	/workspace/coverage/default/41.keymgr_cfg_regwen.1532140471
Short name	T403
Test name
Test status
Simulation time	155692100 ps
CPU time	6.82 seconds
Started	Apr 20 04:08:51 PM PDT 24
Finished	Apr 20 04:08:58 PM PDT 24
Peak memory	215520 kb
Host	smart-68610b49-2cc7-4efc-9843-750c406701df
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1532140471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.1532140471
Directory	/workspace/41.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/41.keymgr_direct_to_disabled.3132480682
Short name	T890
Test name
Test status
Simulation time	1464577921 ps
CPU time	13.92 seconds
Started	Apr 20 04:08:53 PM PDT 24
Finished	Apr 20 04:09:07 PM PDT 24
Peak memory	208908 kb
Host	smart-b5da8734-3e0b-46c6-a903-28ba78a011d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3132480682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.3132480682
Directory	/workspace/41.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/41.keymgr_hwsw_invalid_input.946050093
Short name	T720
Test name
Test status
Simulation time	215436795 ps
CPU time	3.86 seconds
Started	Apr 20 04:08:54 PM PDT 24
Finished	Apr 20 04:08:58 PM PDT 24
Peak memory	209320 kb
Host	smart-424586f6-d63d-4b32-879f-7f416f168a54
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=946050093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.946050093
Directory	/workspace/41.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/41.keymgr_kmac_rsp_err.535673770
Short name	T324
Test name
Test status
Simulation time	525411107 ps
CPU time	5.95 seconds
Started	Apr 20 04:08:51 PM PDT 24
Finished	Apr 20 04:08:58 PM PDT 24
Peak memory	214460 kb
Host	smart-b919a135-6691-4334-a72e-575f98cc4c6c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=535673770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.535673770
Directory	/workspace/41.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/41.keymgr_lc_disable.1628452455
Short name	T584
Test name
Test status
Simulation time	194586918 ps
CPU time	3.55 seconds
Started	Apr 20 04:08:53 PM PDT 24
Finished	Apr 20 04:08:57 PM PDT 24
Peak memory	214320 kb
Host	smart-f2e80662-187c-4845-b90c-dfc3d0cdc74b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1628452455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.1628452455
Directory	/workspace/41.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/41.keymgr_random.3650020556
Short name	T347
Test name
Test status
Simulation time	195597012 ps
CPU time	5.04 seconds
Started	Apr 20 04:08:53 PM PDT 24
Finished	Apr 20 04:08:58 PM PDT 24
Peak memory	209364 kb
Host	smart-e912093d-4a37-4f81-9dcd-21665c0c23d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3650020556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.3650020556
Directory	/workspace/41.keymgr_random/latest

Test location	/workspace/coverage/default/41.keymgr_sideload.264686956
Short name	T656
Test name
Test status
Simulation time	64692325 ps
CPU time	3.24 seconds
Started	Apr 20 04:08:48 PM PDT 24
Finished	Apr 20 04:08:51 PM PDT 24
Peak memory	206052 kb
Host	smart-1504a77b-69af-4515-9357-fefc3ef6e50e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=264686956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.264686956
Directory	/workspace/41.keymgr_sideload/latest

Test location	/workspace/coverage/default/41.keymgr_sideload_aes.4164619466
Short name	T672
Test name
Test status
Simulation time	718931756 ps
CPU time	3.59 seconds
Started	Apr 20 04:08:48 PM PDT 24
Finished	Apr 20 04:08:52 PM PDT 24
Peak memory	208448 kb
Host	smart-267eaf39-ef52-4960-bdc8-eb37c03b1e81
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164619466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.4164619466
Directory	/workspace/41.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/41.keymgr_sideload_kmac.1756367165
Short name	T773
Test name
Test status
Simulation time	97799135 ps
CPU time	4.3 seconds
Started	Apr 20 04:08:50 PM PDT 24
Finished	Apr 20 04:08:55 PM PDT 24
Peak memory	208852 kb
Host	smart-30e125ea-2b23-405d-9acd-86bb153d413e
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756367165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.1756367165
Directory	/workspace/41.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/41.keymgr_sideload_otbn.3689769724
Short name	T377
Test name
Test status
Simulation time	2135407702 ps
CPU time	32 seconds
Started	Apr 20 04:08:56 PM PDT 24
Finished	Apr 20 04:09:28 PM PDT 24
Peak memory	208656 kb
Host	smart-45b0d147-4478-4305-bc79-3f79cc9a2e1f
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689769724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.3689769724
Directory	/workspace/41.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/41.keymgr_sideload_protect.3365706628
Short name	T973
Test name
Test status
Simulation time	1245342345 ps
CPU time	30.16 seconds
Started	Apr 20 04:09:00 PM PDT 24
Finished	Apr 20 04:09:30 PM PDT 24
Peak memory	209512 kb
Host	smart-2c5cf221-df7f-457f-842b-f020dea60df9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3365706628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.3365706628
Directory	/workspace/41.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/41.keymgr_smoke.3861538850
Short name	T1065
Test name
Test status
Simulation time	61240510 ps
CPU time	2.93 seconds
Started	Apr 20 04:08:49 PM PDT 24
Finished	Apr 20 04:08:52 PM PDT 24
Peak memory	208696 kb
Host	smart-5641a7a1-e63e-45d1-8145-9d6939c0bcff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3861538850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.3861538850
Directory	/workspace/41.keymgr_smoke/latest

Test location	/workspace/coverage/default/41.keymgr_stress_all.3987764039
Short name	T333
Test name
Test status
Simulation time	12746482621 ps
CPU time	93.06 seconds
Started	Apr 20 04:08:55 PM PDT 24
Finished	Apr 20 04:10:28 PM PDT 24
Peak memory	222296 kb
Host	smart-8c150e5b-ddb3-47ef-9b8d-0b32163264d0
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987764039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.3987764039
Directory	/workspace/41.keymgr_stress_all/latest

Test location	/workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.170152799
Short name	T208
Test name
Test status
Simulation time	203619228 ps
CPU time	6.47 seconds
Started	Apr 20 04:08:55 PM PDT 24
Finished	Apr 20 04:09:02 PM PDT 24
Peak memory	222556 kb
Host	smart-ebaedf31-a1de-468a-9354-90071856301d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170152799 -assert nopost proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.170152799
Directory	/workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/41.keymgr_sw_invalid_input.2798734893
Short name	T637
Test name
Test status
Simulation time	3659114294 ps
CPU time	65.52 seconds
Started	Apr 20 04:08:52 PM PDT 24
Finished	Apr 20 04:09:58 PM PDT 24
Peak memory	209596 kb
Host	smart-321fb2f3-7e24-4f11-a670-8dc568de3d3b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2798734893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.2798734893
Directory	/workspace/41.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/41.keymgr_sync_async_fault_cross.3210065236
Short name	T863
Test name
Test status
Simulation time	380300788 ps
CPU time	3.85 seconds
Started	Apr 20 04:08:56 PM PDT 24
Finished	Apr 20 04:09:00 PM PDT 24
Peak memory	210556 kb
Host	smart-23177214-3d57-46a1-acf5-3c459ef38f4f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3210065236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.3210065236
Directory	/workspace/41.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/42.keymgr_alert_test.1025811707
Short name	T557
Test name
Test status
Simulation time	41981734 ps
CPU time	0.89 seconds
Started	Apr 20 04:09:05 PM PDT 24
Finished	Apr 20 04:09:06 PM PDT 24
Peak memory	205792 kb
Host	smart-2680f6e2-5d84-425a-8d84-7fe847013738
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025811707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.1025811707
Directory	/workspace/42.keymgr_alert_test/latest

Test location	/workspace/coverage/default/42.keymgr_cfg_regwen.2887118675
Short name	T332
Test name
Test status
Simulation time	275218067 ps
CPU time	7.87 seconds
Started	Apr 20 04:08:55 PM PDT 24
Finished	Apr 20 04:09:03 PM PDT 24
Peak memory	214356 kb
Host	smart-ee8daad0-1f58-4850-91be-fed79ad4d3c0
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2887118675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.2887118675
Directory	/workspace/42.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/42.keymgr_custom_cm.2470251647
Short name	T979
Test name
Test status
Simulation time	408339680 ps
CPU time	4.66 seconds
Started	Apr 20 04:09:05 PM PDT 24
Finished	Apr 20 04:09:10 PM PDT 24
Peak memory	209120 kb
Host	smart-bc260fb9-1277-4a0c-92d1-46140d74a0ab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2470251647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.2470251647
Directory	/workspace/42.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/42.keymgr_direct_to_disabled.3018858190
Short name	T387
Test name
Test status
Simulation time	597664673 ps
CPU time	5.23 seconds
Started	Apr 20 04:08:56 PM PDT 24
Finished	Apr 20 04:09:02 PM PDT 24
Peak memory	209252 kb
Host	smart-b03fab52-4d04-4a34-9f30-2094ca1c0ea3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3018858190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.3018858190
Directory	/workspace/42.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/42.keymgr_hwsw_invalid_input.3138453820
Short name	T807
Test name
Test status
Simulation time	303306585 ps
CPU time	4.02 seconds
Started	Apr 20 04:09:02 PM PDT 24
Finished	Apr 20 04:09:06 PM PDT 24
Peak memory	214360 kb
Host	smart-fcb59f3d-9007-4e8e-b1e4-c1ab75e0ebaa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3138453820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.3138453820
Directory	/workspace/42.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/42.keymgr_lc_disable.3326687804
Short name	T802
Test name
Test status
Simulation time	277044669 ps
CPU time	4.31 seconds
Started	Apr 20 04:09:00 PM PDT 24
Finished	Apr 20 04:09:05 PM PDT 24
Peak memory	209740 kb
Host	smart-545424c1-5e22-4f6c-bebb-d24916db47e5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3326687804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.3326687804
Directory	/workspace/42.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/42.keymgr_random.3963852142
Short name	T850
Test name
Test status
Simulation time	353428407 ps
CPU time	4.96 seconds
Started	Apr 20 04:09:00 PM PDT 24
Finished	Apr 20 04:09:05 PM PDT 24
Peak memory	207720 kb
Host	smart-d66f0c4f-d98f-44af-a1e2-911a2c2adaa6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3963852142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.3963852142
Directory	/workspace/42.keymgr_random/latest

Test location	/workspace/coverage/default/42.keymgr_sideload.1917176878
Short name	T717
Test name
Test status
Simulation time	419561180 ps
CPU time	6.52 seconds
Started	Apr 20 04:08:57 PM PDT 24
Finished	Apr 20 04:09:04 PM PDT 24
Peak memory	206728 kb
Host	smart-81b33850-d788-4192-bbfd-f9699d000f0f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1917176878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.1917176878
Directory	/workspace/42.keymgr_sideload/latest

Test location	/workspace/coverage/default/42.keymgr_sideload_aes.2072660570
Short name	T565
Test name
Test status
Simulation time	37799254 ps
CPU time	2.46 seconds
Started	Apr 20 04:08:57 PM PDT 24
Finished	Apr 20 04:09:00 PM PDT 24
Peak memory	206856 kb
Host	smart-912e67bb-0719-45e4-bb21-bc3040772378
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072660570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.2072660570
Directory	/workspace/42.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/42.keymgr_sideload_kmac.2682221452
Short name	T788
Test name
Test status
Simulation time	103158189 ps
CPU time	4.02 seconds
Started	Apr 20 04:08:56 PM PDT 24
Finished	Apr 20 04:09:00 PM PDT 24
Peak memory	208152 kb
Host	smart-784f045c-065b-4992-b145-093f4396af76
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682221452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.2682221452
Directory	/workspace/42.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/42.keymgr_sideload_otbn.3236922641
Short name	T762
Test name
Test status
Simulation time	70915615 ps
CPU time	2.91 seconds
Started	Apr 20 04:08:57 PM PDT 24
Finished	Apr 20 04:09:00 PM PDT 24
Peak memory	208912 kb
Host	smart-60f1701f-dd32-4426-8c01-34beb8dfc1b9
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236922641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.3236922641
Directory	/workspace/42.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/42.keymgr_sideload_protect.155894348
Short name	T264
Test name
Test status
Simulation time	76538484 ps
CPU time	2.88 seconds
Started	Apr 20 04:08:58 PM PDT 24
Finished	Apr 20 04:09:01 PM PDT 24
Peak memory	208912 kb
Host	smart-20dd1e22-cb11-480e-ad77-9cc3218bdc5e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=155894348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.155894348
Directory	/workspace/42.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/42.keymgr_smoke.3964271058
Short name	T755
Test name
Test status
Simulation time	51295641 ps
CPU time	2.69 seconds
Started	Apr 20 04:08:55 PM PDT 24
Finished	Apr 20 04:08:58 PM PDT 24
Peak memory	206644 kb
Host	smart-db4f6421-7eb0-4a7c-b39c-911018f9ebb7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3964271058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.3964271058
Directory	/workspace/42.keymgr_smoke/latest

Test location	/workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.2456268037
Short name	T410
Test name
Test status
Simulation time	223440525 ps
CPU time	1.82 seconds
Started	Apr 20 04:08:59 PM PDT 24
Finished	Apr 20 04:09:01 PM PDT 24
Peak memory	219536 kb
Host	smart-7a1add90-843a-442c-a43d-0ffb6b98346a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456268037 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.2456268037
Directory	/workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/42.keymgr_sw_invalid_input.2887516078
Short name	T407
Test name
Test status
Simulation time	328839450 ps
CPU time	4.21 seconds
Started	Apr 20 04:09:05 PM PDT 24
Finished	Apr 20 04:09:10 PM PDT 24
Peak memory	206904 kb
Host	smart-57bf321a-3a53-4bee-887a-6db0c5d2c509
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2887516078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.2887516078
Directory	/workspace/42.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/42.keymgr_sync_async_fault_cross.1196890567
Short name	T585
Test name
Test status
Simulation time	84494985 ps
CPU time	3.32 seconds
Started	Apr 20 04:08:59 PM PDT 24
Finished	Apr 20 04:09:02 PM PDT 24
Peak memory	209856 kb
Host	smart-c7dd6592-2666-4c25-8dd1-4bb84138a6a7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1196890567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.1196890567
Directory	/workspace/42.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/43.keymgr_alert_test.757376847
Short name	T623
Test name
Test status
Simulation time	30287213 ps
CPU time	0.75 seconds
Started	Apr 20 04:09:07 PM PDT 24
Finished	Apr 20 04:09:08 PM PDT 24
Peak memory	205832 kb
Host	smart-aeb7b49e-3f05-4e95-93e4-daae535c4247
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757376847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.757376847
Directory	/workspace/43.keymgr_alert_test/latest

Test location	/workspace/coverage/default/43.keymgr_cfg_regwen.1900845314
Short name	T1051
Test name
Test status
Simulation time	111372159 ps
CPU time	6.07 seconds
Started	Apr 20 04:09:02 PM PDT 24
Finished	Apr 20 04:09:08 PM PDT 24
Peak memory	214280 kb
Host	smart-5e0079ad-09b2-4737-affe-499be9d0952e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1900845314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.1900845314
Directory	/workspace/43.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/43.keymgr_custom_cm.4141896100
Short name	T11
Test name
Test status
Simulation time	90886925 ps
CPU time	3.26 seconds
Started	Apr 20 04:09:03 PM PDT 24
Finished	Apr 20 04:09:07 PM PDT 24
Peak memory	222828 kb
Host	smart-5950c833-6d5b-4319-af6b-db740052aa54
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4141896100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.4141896100
Directory	/workspace/43.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/43.keymgr_direct_to_disabled.4222387271
Short name	T230
Test name
Test status
Simulation time	3650336123 ps
CPU time	35.23 seconds
Started	Apr 20 04:09:04 PM PDT 24
Finished	Apr 20 04:09:39 PM PDT 24
Peak memory	218536 kb
Host	smart-2c3f5da3-d773-46f4-8783-6c6907977e99
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4222387271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.4222387271
Directory	/workspace/43.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/43.keymgr_hwsw_invalid_input.1811703396
Short name	T817
Test name
Test status
Simulation time	318977256 ps
CPU time	3.62 seconds
Started	Apr 20 04:09:02 PM PDT 24
Finished	Apr 20 04:09:06 PM PDT 24
Peak memory	208576 kb
Host	smart-0874a292-8713-4a95-aa7c-e6553aade6f6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1811703396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.1811703396
Directory	/workspace/43.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/43.keymgr_kmac_rsp_err.1195273063
Short name	T254
Test name
Test status
Simulation time	178770555 ps
CPU time	7.48 seconds
Started	Apr 20 04:09:04 PM PDT 24
Finished	Apr 20 04:09:12 PM PDT 24
Peak memory	209580 kb
Host	smart-648f08e7-38ec-4385-9a37-36bf5f5e8a71
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1195273063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.1195273063
Directory	/workspace/43.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/43.keymgr_random.539506001
Short name	T1002
Test name
Test status
Simulation time	330057458 ps
CPU time	4.27 seconds
Started	Apr 20 04:09:04 PM PDT 24
Finished	Apr 20 04:09:08 PM PDT 24
Peak memory	207464 kb
Host	smart-a3f3af10-5cdd-4593-babc-356f6d68ccfd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=539506001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.539506001
Directory	/workspace/43.keymgr_random/latest

Test location	/workspace/coverage/default/43.keymgr_sideload.3420284867
Short name	T560
Test name
Test status
Simulation time	174231416 ps
CPU time	2.71 seconds
Started	Apr 20 04:09:05 PM PDT 24
Finished	Apr 20 04:09:08 PM PDT 24
Peak memory	208172 kb
Host	smart-1783046d-856f-4d9d-9875-e87f549d6f5e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3420284867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.3420284867
Directory	/workspace/43.keymgr_sideload/latest

Test location	/workspace/coverage/default/43.keymgr_sideload_kmac.1391413322
Short name	T631
Test name
Test status
Simulation time	850473136 ps
CPU time	2.84 seconds
Started	Apr 20 04:08:59 PM PDT 24
Finished	Apr 20 04:09:02 PM PDT 24
Peak memory	208380 kb
Host	smart-53c6e00a-636f-4eaa-90af-471c31873016
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391413322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.1391413322
Directory	/workspace/43.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/43.keymgr_sideload_otbn.3495433877
Short name	T675
Test name
Test status
Simulation time	863723513 ps
CPU time	27.21 seconds
Started	Apr 20 04:09:02 PM PDT 24
Finished	Apr 20 04:09:30 PM PDT 24
Peak memory	208304 kb
Host	smart-74835da5-4398-4b75-bb10-9a2caced3bb9
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495433877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.3495433877
Directory	/workspace/43.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/43.keymgr_sideload_protect.2959688603
Short name	T693
Test name
Test status
Simulation time	47374440 ps
CPU time	2.04 seconds
Started	Apr 20 04:09:03 PM PDT 24
Finished	Apr 20 04:09:05 PM PDT 24
Peak memory	214408 kb
Host	smart-ef9c569c-7451-409c-b5c5-4eba2717b392
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2959688603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.2959688603
Directory	/workspace/43.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/43.keymgr_smoke.3705224497
Short name	T767
Test name
Test status
Simulation time	114135130 ps
CPU time	3.07 seconds
Started	Apr 20 04:08:58 PM PDT 24
Finished	Apr 20 04:09:02 PM PDT 24
Peak memory	206812 kb
Host	smart-916068b0-e463-467d-80fe-736379285032
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3705224497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.3705224497
Directory	/workspace/43.keymgr_smoke/latest

Test location	/workspace/coverage/default/43.keymgr_stress_all.1805830868
Short name	T316
Test name
Test status
Simulation time	1791587413 ps
CPU time	52.21 seconds
Started	Apr 20 04:09:05 PM PDT 24
Finished	Apr 20 04:09:58 PM PDT 24
Peak memory	222408 kb
Host	smart-fe7d9486-c052-4fa0-9d33-268f0c2f951e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805830868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.1805830868
Directory	/workspace/43.keymgr_stress_all/latest

Test location	/workspace/coverage/default/43.keymgr_sw_invalid_input.4083031374
Short name	T747
Test name
Test status
Simulation time	389508471 ps
CPU time	12.26 seconds
Started	Apr 20 04:09:05 PM PDT 24
Finished	Apr 20 04:09:18 PM PDT 24
Peak memory	218340 kb
Host	smart-0fdc8200-abdb-4c4d-b6f4-dc2b1c2499fe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4083031374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.4083031374
Directory	/workspace/43.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/43.keymgr_sync_async_fault_cross.78118411
Short name	T619
Test name
Test status
Simulation time	40587787 ps
CPU time	2.55 seconds
Started	Apr 20 04:09:05 PM PDT 24
Finished	Apr 20 04:09:08 PM PDT 24
Peak memory	210088 kb
Host	smart-fdde2d42-6f0d-4d03-ac1a-279d17ca86f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=78118411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.78118411
Directory	/workspace/43.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/44.keymgr_alert_test.3131970446
Short name	T1034
Test name
Test status
Simulation time	39428854 ps
CPU time	0.73 seconds
Started	Apr 20 04:09:15 PM PDT 24
Finished	Apr 20 04:09:16 PM PDT 24
Peak memory	205808 kb
Host	smart-dcdd76e7-d733-463e-a604-65fcc9c742d6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131970446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.3131970446
Directory	/workspace/44.keymgr_alert_test/latest

Test location	/workspace/coverage/default/44.keymgr_cfg_regwen.4237382479
Short name	T417
Test name
Test status
Simulation time	1565912885 ps
CPU time	10.58 seconds
Started	Apr 20 04:09:08 PM PDT 24
Finished	Apr 20 04:09:19 PM PDT 24
Peak memory	214284 kb
Host	smart-d5420cf4-c4ab-4478-b6e0-16bf06524f2a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4237382479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.4237382479
Directory	/workspace/44.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/44.keymgr_custom_cm.1330598815
Short name	T695
Test name
Test status
Simulation time	77781368 ps
CPU time	3.88 seconds
Started	Apr 20 04:09:07 PM PDT 24
Finished	Apr 20 04:09:11 PM PDT 24
Peak memory	210432 kb
Host	smart-7e0fb6d5-12a7-4a41-95e1-49f2317ca3e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1330598815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.1330598815
Directory	/workspace/44.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/44.keymgr_direct_to_disabled.3001752808
Short name	T892
Test name
Test status
Simulation time	1754369287 ps
CPU time	35.47 seconds
Started	Apr 20 04:09:07 PM PDT 24
Finished	Apr 20 04:09:43 PM PDT 24
Peak memory	214356 kb
Host	smart-76097d9f-1991-41a8-813a-e02889956353
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3001752808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.3001752808
Directory	/workspace/44.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/44.keymgr_hwsw_invalid_input.2797206542
Short name	T821
Test name
Test status
Simulation time	33266159 ps
CPU time	2.43 seconds
Started	Apr 20 04:09:11 PM PDT 24
Finished	Apr 20 04:09:14 PM PDT 24
Peak memory	209656 kb
Host	smart-4b8b0236-1fc0-42e1-8550-fc2e35181fcb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2797206542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.2797206542
Directory	/workspace/44.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/44.keymgr_kmac_rsp_err.1098293167
Short name	T293
Test name
Test status
Simulation time	347610985 ps
CPU time	5.56 seconds
Started	Apr 20 04:09:08 PM PDT 24
Finished	Apr 20 04:09:14 PM PDT 24
Peak memory	222316 kb
Host	smart-73607ead-8a7c-4c91-9fb5-0cd888a855e5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1098293167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.1098293167
Directory	/workspace/44.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/44.keymgr_random.4146377930
Short name	T348
Test name
Test status
Simulation time	739555821 ps
CPU time	24.23 seconds
Started	Apr 20 04:09:08 PM PDT 24
Finished	Apr 20 04:09:32 PM PDT 24
Peak memory	208996 kb
Host	smart-d137c6c7-121f-4c09-8112-bcb28932e432
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4146377930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.4146377930
Directory	/workspace/44.keymgr_random/latest

Test location	/workspace/coverage/default/44.keymgr_sideload.16115234
Short name	T729
Test name
Test status
Simulation time	109071794 ps
CPU time	2.95 seconds
Started	Apr 20 04:09:05 PM PDT 24
Finished	Apr 20 04:09:08 PM PDT 24
Peak memory	208920 kb
Host	smart-e673235b-155f-46a4-8877-0848c4e5c928
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=16115234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.16115234
Directory	/workspace/44.keymgr_sideload/latest

Test location	/workspace/coverage/default/44.keymgr_sideload_aes.3965219872
Short name	T723
Test name
Test status
Simulation time	669453279 ps
CPU time	3.77 seconds
Started	Apr 20 04:09:06 PM PDT 24
Finished	Apr 20 04:09:11 PM PDT 24
Peak memory	208340 kb
Host	smart-77c85c61-3c46-4465-8387-841c05fdccc7
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965219872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.3965219872
Directory	/workspace/44.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/44.keymgr_sideload_kmac.1131196143
Short name	T1066
Test name
Test status
Simulation time	226463578 ps
CPU time	3.57 seconds
Started	Apr 20 04:09:05 PM PDT 24
Finished	Apr 20 04:09:09 PM PDT 24
Peak memory	206776 kb
Host	smart-7e7cd440-6719-47a6-93a4-9b2a7ac93390
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131196143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.1131196143
Directory	/workspace/44.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/44.keymgr_sideload_otbn.2459195089
Short name	T826
Test name
Test status
Simulation time	24781876 ps
CPU time	2.15 seconds
Started	Apr 20 04:09:07 PM PDT 24
Finished	Apr 20 04:09:09 PM PDT 24
Peak memory	208752 kb
Host	smart-23187aa4-b688-4f75-8874-a4c36e179931
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459195089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.2459195089
Directory	/workspace/44.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/44.keymgr_sideload_protect.4132373885
Short name	T281
Test name
Test status
Simulation time	105594872 ps
CPU time	2.48 seconds
Started	Apr 20 04:09:10 PM PDT 24
Finished	Apr 20 04:09:13 PM PDT 24
Peak memory	218532 kb
Host	smart-bb74cb15-b34f-4012-b185-668dab99fb3b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4132373885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.4132373885
Directory	/workspace/44.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/44.keymgr_smoke.3428563963
Short name	T893
Test name
Test status
Simulation time	1518647489 ps
CPU time	17.34 seconds
Started	Apr 20 04:09:06 PM PDT 24
Finished	Apr 20 04:09:23 PM PDT 24
Peak memory	208324 kb
Host	smart-9066dddc-dd18-4777-8aa1-1adfeceac4ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3428563963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.3428563963
Directory	/workspace/44.keymgr_smoke/latest

Test location	/workspace/coverage/default/44.keymgr_stress_all.1577289018
Short name	T357
Test name
Test status
Simulation time	4678339013 ps
CPU time	122.53 seconds
Started	Apr 20 04:09:09 PM PDT 24
Finished	Apr 20 04:11:12 PM PDT 24
Peak memory	216876 kb
Host	smart-d692ba08-ad39-4a9c-b7ca-e7e1ec38f3f1
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577289018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.1577289018
Directory	/workspace/44.keymgr_stress_all/latest

Test location	/workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.1661679608
Short name	T984
Test name
Test status
Simulation time	1509851044 ps
CPU time	4.86 seconds
Started	Apr 20 04:09:15 PM PDT 24
Finished	Apr 20 04:09:20 PM PDT 24
Peak memory	219072 kb
Host	smart-b8112b3f-d131-44e5-96ab-2a0b206e432f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661679608 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.1661679608
Directory	/workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/44.keymgr_sw_invalid_input.868666002
Short name	T735
Test name
Test status
Simulation time	677787039 ps
CPU time	9.39 seconds
Started	Apr 20 04:09:10 PM PDT 24
Finished	Apr 20 04:09:19 PM PDT 24
Peak memory	214268 kb
Host	smart-01de5c3d-708f-454a-8ac2-ca1228118720
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=868666002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.868666002
Directory	/workspace/44.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/44.keymgr_sync_async_fault_cross.1035516018
Short name	T851
Test name
Test status
Simulation time	102473271 ps
CPU time	3.8 seconds
Started	Apr 20 04:09:08 PM PDT 24
Finished	Apr 20 04:09:12 PM PDT 24
Peak memory	210840 kb
Host	smart-c6b3be16-09a5-47cd-a94d-b0381397ec2f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1035516018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.1035516018
Directory	/workspace/44.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/45.keymgr_alert_test.4231094797
Short name	T608
Test name
Test status
Simulation time	15248315 ps
CPU time	0.79 seconds
Started	Apr 20 04:09:15 PM PDT 24
Finished	Apr 20 04:09:16 PM PDT 24
Peak memory	205804 kb
Host	smart-9b7a88fc-09da-4877-9d61-5aabb14b4157
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231094797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.4231094797
Directory	/workspace/45.keymgr_alert_test/latest

Test location	/workspace/coverage/default/45.keymgr_cfg_regwen.2147620411
Short name	T422
Test name
Test status
Simulation time	41630851 ps
CPU time	3.12 seconds
Started	Apr 20 04:09:11 PM PDT 24
Finished	Apr 20 04:09:14 PM PDT 24
Peak memory	214884 kb
Host	smart-aca34fc2-f5dd-4db7-891c-fc4c1588df25
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2147620411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.2147620411
Directory	/workspace/45.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/45.keymgr_custom_cm.182924986
Short name	T1008
Test name
Test status
Simulation time	185429788 ps
CPU time	4.31 seconds
Started	Apr 20 04:09:15 PM PDT 24
Finished	Apr 20 04:09:19 PM PDT 24
Peak memory	209792 kb
Host	smart-f939bfc8-3b29-49c3-bf1a-550cad542c78
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=182924986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.182924986
Directory	/workspace/45.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/45.keymgr_direct_to_disabled.4145300471
Short name	T643
Test name
Test status
Simulation time	5075929943 ps
CPU time	20.76 seconds
Started	Apr 20 04:09:20 PM PDT 24
Finished	Apr 20 04:09:41 PM PDT 24
Peak memory	218540 kb
Host	smart-9c68e04a-3233-4747-8dc9-19fad64511a1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4145300471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.4145300471
Directory	/workspace/45.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/45.keymgr_lc_disable.2839280929
Short name	T47
Test name
Test status
Simulation time	194583320 ps
CPU time	3.39 seconds
Started	Apr 20 04:09:21 PM PDT 24
Finished	Apr 20 04:09:25 PM PDT 24
Peak memory	214380 kb
Host	smart-955eab4a-9e5f-46a9-85ba-19d6008e11ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2839280929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.2839280929
Directory	/workspace/45.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/45.keymgr_random.2765364789
Short name	T1047
Test name
Test status
Simulation time	828573284 ps
CPU time	6.04 seconds
Started	Apr 20 04:09:13 PM PDT 24
Finished	Apr 20 04:09:19 PM PDT 24
Peak memory	218416 kb
Host	smart-2782eb8f-cf8d-412f-b75f-ebd1ade8bf0c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2765364789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.2765364789
Directory	/workspace/45.keymgr_random/latest

Test location	/workspace/coverage/default/45.keymgr_sideload.2524320959
Short name	T848
Test name
Test status
Simulation time	95257758 ps
CPU time	3.63 seconds
Started	Apr 20 04:09:14 PM PDT 24
Finished	Apr 20 04:09:18 PM PDT 24
Peak memory	208188 kb
Host	smart-953a9588-dbad-409e-aa82-20e72a276761
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2524320959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.2524320959
Directory	/workspace/45.keymgr_sideload/latest

Test location	/workspace/coverage/default/45.keymgr_sideload_aes.2907457394
Short name	T1003
Test name
Test status
Simulation time	197844815 ps
CPU time	2.82 seconds
Started	Apr 20 04:09:10 PM PDT 24
Finished	Apr 20 04:09:14 PM PDT 24
Peak memory	208784 kb
Host	smart-1fe3d327-eb57-4e94-9d74-0b4870e28eb5
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907457394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.2907457394
Directory	/workspace/45.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/45.keymgr_sideload_kmac.2414220947
Short name	T918
Test name
Test status
Simulation time	137148833 ps
CPU time	2.82 seconds
Started	Apr 20 04:09:11 PM PDT 24
Finished	Apr 20 04:09:14 PM PDT 24
Peak memory	206980 kb
Host	smart-bf4d7f63-32e6-4d53-86f8-2bacbd3e9967
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414220947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.2414220947
Directory	/workspace/45.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/45.keymgr_sideload_otbn.3474154413
Short name	T559
Test name
Test status
Simulation time	69542906 ps
CPU time	2.38 seconds
Started	Apr 20 04:09:10 PM PDT 24
Finished	Apr 20 04:09:13 PM PDT 24
Peak memory	206804 kb
Host	smart-e9753f39-6fe6-4301-9c92-2242d5e520cd
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474154413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.3474154413
Directory	/workspace/45.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/45.keymgr_sideload_protect.3587182746
Short name	T413
Test name
Test status
Simulation time	212846949 ps
CPU time	2.99 seconds
Started	Apr 20 04:09:17 PM PDT 24
Finished	Apr 20 04:09:20 PM PDT 24
Peak memory	207268 kb
Host	smart-a6932c9c-9ec0-4cfc-ac7b-56c7433ecd3e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3587182746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.3587182746
Directory	/workspace/45.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/45.keymgr_smoke.3641419787
Short name	T924
Test name
Test status
Simulation time	385831669 ps
CPU time	3.28 seconds
Started	Apr 20 04:09:15 PM PDT 24
Finished	Apr 20 04:09:18 PM PDT 24
Peak memory	208560 kb
Host	smart-91d2160c-0494-4269-84c2-9b69a1a6104d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3641419787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.3641419787
Directory	/workspace/45.keymgr_smoke/latest

Test location	/workspace/coverage/default/45.keymgr_stress_all.45754363
Short name	T575
Test name
Test status
Simulation time	36060953 ps
CPU time	0.76 seconds
Started	Apr 20 04:09:19 PM PDT 24
Finished	Apr 20 04:09:21 PM PDT 24
Peak memory	205828 kb
Host	smart-d2325687-4305-42e7-92db-a671d8c376e6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45754363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.45754363
Directory	/workspace/45.keymgr_stress_all/latest

Test location	/workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.2818201381
Short name	T906
Test name
Test status
Simulation time	210656616 ps
CPU time	6.38 seconds
Started	Apr 20 04:09:14 PM PDT 24
Finished	Apr 20 04:09:21 PM PDT 24
Peak memory	220540 kb
Host	smart-4fc94003-f99f-4664-9e77-5fac4cbb7841
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818201381 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.2818201381
Directory	/workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/45.keymgr_sw_invalid_input.1399778587
Short name	T917
Test name
Test status
Simulation time	74607864 ps
CPU time	3.6 seconds
Started	Apr 20 04:09:16 PM PDT 24
Finished	Apr 20 04:09:20 PM PDT 24
Peak memory	209188 kb
Host	smart-307ace3e-dd4a-4d1c-9700-2621bb76ebcd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1399778587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.1399778587
Directory	/workspace/45.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/45.keymgr_sync_async_fault_cross.91670895
Short name	T664
Test name
Test status
Simulation time	165786758 ps
CPU time	2.01 seconds
Started	Apr 20 04:09:16 PM PDT 24
Finished	Apr 20 04:09:18 PM PDT 24
Peak memory	209800 kb
Host	smart-e3aef8d5-0861-476c-9fc1-a266ef67576b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=91670895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.91670895
Directory	/workspace/45.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/46.keymgr_alert_test.2053804874
Short name	T684
Test name
Test status
Simulation time	23096675 ps
CPU time	0.91 seconds
Started	Apr 20 04:09:20 PM PDT 24
Finished	Apr 20 04:09:21 PM PDT 24
Peak memory	205816 kb
Host	smart-a3ccb7da-c948-4a04-bf76-7065758f904b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053804874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.2053804874
Directory	/workspace/46.keymgr_alert_test/latest

Test location	/workspace/coverage/default/46.keymgr_cfg_regwen.981241819
Short name	T402
Test name
Test status
Simulation time	193513612 ps
CPU time	3.57 seconds
Started	Apr 20 04:09:17 PM PDT 24
Finished	Apr 20 04:09:21 PM PDT 24
Peak memory	214540 kb
Host	smart-508f709d-9137-4e04-a5c9-c2c9969f558c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=981241819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.981241819
Directory	/workspace/46.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/46.keymgr_custom_cm.2909229976
Short name	T843
Test name
Test status
Simulation time	1233972805 ps
CPU time	13.25 seconds
Started	Apr 20 04:09:19 PM PDT 24
Finished	Apr 20 04:09:33 PM PDT 24
Peak memory	222784 kb
Host	smart-4342bf36-ed08-4cb3-b054-e563bc22f815
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2909229976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.2909229976
Directory	/workspace/46.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/46.keymgr_direct_to_disabled.2595351551
Short name	T748
Test name
Test status
Simulation time	1920321548 ps
CPU time	6.93 seconds
Started	Apr 20 04:09:16 PM PDT 24
Finished	Apr 20 04:09:24 PM PDT 24
Peak memory	209048 kb
Host	smart-781a6dcf-1073-4fba-a23e-770185126f64
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2595351551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.2595351551
Directory	/workspace/46.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/46.keymgr_hwsw_invalid_input.3053894555
Short name	T231
Test name
Test status
Simulation time	373816507 ps
CPU time	7.98 seconds
Started	Apr 20 04:09:22 PM PDT 24
Finished	Apr 20 04:09:30 PM PDT 24
Peak memory	214308 kb
Host	smart-a1410802-1ec7-4028-9449-4a5499dee5ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3053894555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.3053894555
Directory	/workspace/46.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/46.keymgr_kmac_rsp_err.2988783759
Short name	T280
Test name
Test status
Simulation time	205611259 ps
CPU time	4.95 seconds
Started	Apr 20 04:09:21 PM PDT 24
Finished	Apr 20 04:09:26 PM PDT 24
Peak memory	220744 kb
Host	smart-c6d7c3d4-6171-4191-840f-9dae0f823518
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2988783759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.2988783759
Directory	/workspace/46.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/46.keymgr_lc_disable.682266446
Short name	T391
Test name
Test status
Simulation time	256906397 ps
CPU time	3.49 seconds
Started	Apr 20 04:09:20 PM PDT 24
Finished	Apr 20 04:09:24 PM PDT 24
Peak memory	214232 kb
Host	smart-6da14271-c735-426e-8d0c-9c7395f7b0eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=682266446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.682266446
Directory	/workspace/46.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/46.keymgr_random.2027533499
Short name	T1049
Test name
Test status
Simulation time	480600076 ps
CPU time	10.15 seconds
Started	Apr 20 04:09:20 PM PDT 24
Finished	Apr 20 04:09:30 PM PDT 24
Peak memory	207196 kb
Host	smart-2038722b-66d3-4a6c-af84-e4157f6be7a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2027533499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.2027533499
Directory	/workspace/46.keymgr_random/latest

Test location	/workspace/coverage/default/46.keymgr_sideload.1457740112
Short name	T336
Test name
Test status
Simulation time	1163897503 ps
CPU time	29.32 seconds
Started	Apr 20 04:09:17 PM PDT 24
Finished	Apr 20 04:09:47 PM PDT 24
Peak memory	207788 kb
Host	smart-fe73aad6-c035-413c-aad0-e6d7666a1b77
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1457740112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.1457740112
Directory	/workspace/46.keymgr_sideload/latest

Test location	/workspace/coverage/default/46.keymgr_sideload_aes.3372182136
Short name	T668
Test name
Test status
Simulation time	183733074 ps
CPU time	2.72 seconds
Started	Apr 20 04:09:21 PM PDT 24
Finished	Apr 20 04:09:24 PM PDT 24
Peak memory	206768 kb
Host	smart-f36e74b3-0742-4bc5-bc40-ad5d1c2b6ecc
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372182136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.3372182136
Directory	/workspace/46.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/46.keymgr_sideload_kmac.732176661
Short name	T577
Test name
Test status
Simulation time	82088987 ps
CPU time	3.97 seconds
Started	Apr 20 04:09:16 PM PDT 24
Finished	Apr 20 04:09:20 PM PDT 24
Peak memory	208708 kb
Host	smart-9a02adef-d943-4c38-8883-a2d39810d7e8
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732176661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.732176661
Directory	/workspace/46.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/46.keymgr_sideload_otbn.1975381550
Short name	T687
Test name
Test status
Simulation time	1758435254 ps
CPU time	58.99 seconds
Started	Apr 20 04:09:18 PM PDT 24
Finished	Apr 20 04:10:18 PM PDT 24
Peak memory	208992 kb
Host	smart-5bff8b3c-aaae-4456-b658-3dd320374382
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975381550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.1975381550
Directory	/workspace/46.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/46.keymgr_sideload_protect.1389428709
Short name	T234
Test name
Test status
Simulation time	162727051 ps
CPU time	4.05 seconds
Started	Apr 20 04:09:18 PM PDT 24
Finished	Apr 20 04:09:22 PM PDT 24
Peak memory	209156 kb
Host	smart-f82aa088-1900-4458-9930-be6d44745533
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1389428709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.1389428709
Directory	/workspace/46.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/46.keymgr_smoke.1355904554
Short name	T784
Test name
Test status
Simulation time	101589765 ps
CPU time	2.59 seconds
Started	Apr 20 04:09:20 PM PDT 24
Finished	Apr 20 04:09:23 PM PDT 24
Peak memory	207140 kb
Host	smart-83167056-1355-4958-bbba-bc5bf7f3b017
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1355904554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.1355904554
Directory	/workspace/46.keymgr_smoke/latest

Test location	/workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.1814682243
Short name	T201
Test name
Test status
Simulation time	816182434 ps
CPU time	14.38 seconds
Started	Apr 20 04:09:19 PM PDT 24
Finished	Apr 20 04:09:34 PM PDT 24
Peak memory	222612 kb
Host	smart-e5f1f9f3-abd5-45e9-a754-cbe2889473e2
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814682243 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.1814682243
Directory	/workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/46.keymgr_sw_invalid_input.673728212
Short name	T940
Test name
Test status
Simulation time	390555388 ps
CPU time	5.19 seconds
Started	Apr 20 04:09:21 PM PDT 24
Finished	Apr 20 04:09:26 PM PDT 24
Peak memory	214236 kb
Host	smart-d10de085-9601-4389-9b09-813341ce7944
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=673728212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.673728212
Directory	/workspace/46.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/46.keymgr_sync_async_fault_cross.2481652678
Short name	T59
Test name
Test status
Simulation time	108346104 ps
CPU time	4.16 seconds
Started	Apr 20 04:09:20 PM PDT 24
Finished	Apr 20 04:09:24 PM PDT 24
Peak memory	210280 kb
Host	smart-f0a22f94-f6d1-4ce1-9810-e08b5af7be2e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2481652678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.2481652678
Directory	/workspace/46.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/47.keymgr_alert_test.2321609778
Short name	T100
Test name
Test status
Simulation time	20304848 ps
CPU time	0.92 seconds
Started	Apr 20 04:09:26 PM PDT 24
Finished	Apr 20 04:09:27 PM PDT 24
Peak memory	205880 kb
Host	smart-8d17e795-4e36-4274-bd2a-cbe0d7c8beb8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321609778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.2321609778
Directory	/workspace/47.keymgr_alert_test/latest

Test location	/workspace/coverage/default/47.keymgr_cfg_regwen.344828674
Short name	T223
Test name
Test status
Simulation time	1535764141 ps
CPU time	6.17 seconds
Started	Apr 20 04:09:21 PM PDT 24
Finished	Apr 20 04:09:28 PM PDT 24
Peak memory	222420 kb
Host	smart-a59b1690-f10b-40b0-86a7-aec2ecdd6ffd
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=344828674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.344828674
Directory	/workspace/47.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/47.keymgr_custom_cm.4195630858
Short name	T20
Test name
Test status
Simulation time	118118247 ps
CPU time	5.14 seconds
Started	Apr 20 04:09:22 PM PDT 24
Finished	Apr 20 04:09:28 PM PDT 24
Peak memory	222492 kb
Host	smart-5a263e81-0c72-47e8-bb02-a3397bbd4614
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4195630858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.4195630858
Directory	/workspace/47.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/47.keymgr_direct_to_disabled.1501299353
Short name	T934
Test name
Test status
Simulation time	117814429 ps
CPU time	2.42 seconds
Started	Apr 20 04:09:22 PM PDT 24
Finished	Apr 20 04:09:25 PM PDT 24
Peak memory	214220 kb
Host	smart-d04e273f-6be9-48b0-b503-60b4ec639ad5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1501299353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.1501299353
Directory	/workspace/47.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/47.keymgr_hwsw_invalid_input.3249166979
Short name	T963
Test name
Test status
Simulation time	119055211 ps
CPU time	3.58 seconds
Started	Apr 20 04:09:22 PM PDT 24
Finished	Apr 20 04:09:26 PM PDT 24
Peak memory	214272 kb
Host	smart-ffd3d808-8da5-4fe8-8efd-9dc25820e4a5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3249166979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.3249166979
Directory	/workspace/47.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/47.keymgr_kmac_rsp_err.4247665669
Short name	T198
Test name
Test status
Simulation time	924840856 ps
CPU time	8.26 seconds
Started	Apr 20 04:09:24 PM PDT 24
Finished	Apr 20 04:09:32 PM PDT 24
Peak memory	214272 kb
Host	smart-c2f0034b-119e-42e9-be59-5481d556c3c9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4247665669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.4247665669
Directory	/workspace/47.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/47.keymgr_lc_disable.2438782000
Short name	T987
Test name
Test status
Simulation time	339534068 ps
CPU time	4.44 seconds
Started	Apr 20 04:09:22 PM PDT 24
Finished	Apr 20 04:09:27 PM PDT 24
Peak memory	208812 kb
Host	smart-3878c997-400b-486f-87ce-0189e3460c2a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2438782000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.2438782000
Directory	/workspace/47.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/47.keymgr_sideload.2190389542
Short name	T804
Test name
Test status
Simulation time	94736379 ps
CPU time	2.86 seconds
Started	Apr 20 04:09:19 PM PDT 24
Finished	Apr 20 04:09:23 PM PDT 24
Peak memory	206796 kb
Host	smart-920e5090-96d3-4b81-b647-95cea790974f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2190389542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.2190389542
Directory	/workspace/47.keymgr_sideload/latest

Test location	/workspace/coverage/default/47.keymgr_sideload_aes.3590115675
Short name	T716
Test name
Test status
Simulation time	403255011 ps
CPU time	2.98 seconds
Started	Apr 20 04:09:23 PM PDT 24
Finished	Apr 20 04:09:26 PM PDT 24
Peak memory	208724 kb
Host	smart-4664994e-2c9a-4a36-9851-4cc499343f00
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590115675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.3590115675
Directory	/workspace/47.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/47.keymgr_sideload_kmac.2211117303
Short name	T1028
Test name
Test status
Simulation time	141752337 ps
CPU time	3.76 seconds
Started	Apr 20 04:09:20 PM PDT 24
Finished	Apr 20 04:09:24 PM PDT 24
Peak memory	208724 kb
Host	smart-fcff4505-6c72-4006-bfbe-91df48feb83e
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211117303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.2211117303
Directory	/workspace/47.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/47.keymgr_sideload_otbn.324525586
Short name	T241
Test name
Test status
Simulation time	153216481 ps
CPU time	2.5 seconds
Started	Apr 20 04:09:26 PM PDT 24
Finished	Apr 20 04:09:29 PM PDT 24
Peak memory	207256 kb
Host	smart-fe747694-42aa-4dd7-9625-5a4c678eb452
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324525586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.324525586
Directory	/workspace/47.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/47.keymgr_sideload_protect.1870468668
Short name	T714
Test name
Test status
Simulation time	65292640 ps
CPU time	2.15 seconds
Started	Apr 20 04:09:22 PM PDT 24
Finished	Apr 20 04:09:24 PM PDT 24
Peak memory	218364 kb
Host	smart-d7104687-caea-486a-86db-a9cbf3928d75
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1870468668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.1870468668
Directory	/workspace/47.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/47.keymgr_smoke.281062236
Short name	T191
Test name
Test status
Simulation time	128648493 ps
CPU time	3.94 seconds
Started	Apr 20 04:09:24 PM PDT 24
Finished	Apr 20 04:09:28 PM PDT 24
Peak memory	206760 kb
Host	smart-273dde8a-e626-4b0c-bf89-a191215a5ddf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=281062236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.281062236
Directory	/workspace/47.keymgr_smoke/latest

Test location	/workspace/coverage/default/47.keymgr_stress_all.523174189
Short name	T282
Test name
Test status
Simulation time	1661019763 ps
CPU time	7.91 seconds
Started	Apr 20 04:09:23 PM PDT 24
Finished	Apr 20 04:09:32 PM PDT 24
Peak memory	222084 kb
Host	smart-1cf4ad73-7dbd-45db-9f01-6d58a013a86c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523174189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.523174189
Directory	/workspace/47.keymgr_stress_all/latest

Test location	/workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.3392569603
Short name	T371
Test name
Test status
Simulation time	892631196 ps
CPU time	8.66 seconds
Started	Apr 20 04:09:27 PM PDT 24
Finished	Apr 20 04:09:36 PM PDT 24
Peak memory	222620 kb
Host	smart-971611b6-0298-44aa-a7fd-4f2dae80a42a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392569603 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.3392569603
Directory	/workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/47.keymgr_sw_invalid_input.3644590640
Short name	T959
Test name
Test status
Simulation time	39323637 ps
CPU time	2.98 seconds
Started	Apr 20 04:09:22 PM PDT 24
Finished	Apr 20 04:09:26 PM PDT 24
Peak memory	207464 kb
Host	smart-1373e119-37f5-41da-9c51-616754a3215f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3644590640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.3644590640
Directory	/workspace/47.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/47.keymgr_sync_async_fault_cross.2164329116
Short name	T580
Test name
Test status
Simulation time	128718080 ps
CPU time	1.89 seconds
Started	Apr 20 04:09:23 PM PDT 24
Finished	Apr 20 04:09:25 PM PDT 24
Peak memory	210240 kb
Host	smart-17b71848-da9d-4789-8c58-16470e8f1a88
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2164329116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.2164329116
Directory	/workspace/47.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/48.keymgr_alert_test.2955988545
Short name	T888
Test name
Test status
Simulation time	11972048 ps
CPU time	0.89 seconds
Started	Apr 20 04:09:29 PM PDT 24
Finished	Apr 20 04:09:30 PM PDT 24
Peak memory	205864 kb
Host	smart-72870dfc-8c64-4f76-b211-ddd1bd9662b1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955988545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.2955988545
Directory	/workspace/48.keymgr_alert_test/latest

Test location	/workspace/coverage/default/48.keymgr_custom_cm.912372698
Short name	T33
Test name
Test status
Simulation time	2000586625 ps
CPU time	56.72 seconds
Started	Apr 20 04:09:28 PM PDT 24
Finished	Apr 20 04:10:25 PM PDT 24
Peak memory	209540 kb
Host	smart-2fcfe873-7723-471d-b2e4-d4874b4ad6ef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=912372698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.912372698
Directory	/workspace/48.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/48.keymgr_direct_to_disabled.3393112896
Short name	T794
Test name
Test status
Simulation time	556822218 ps
CPU time	12.09 seconds
Started	Apr 20 04:09:23 PM PDT 24
Finished	Apr 20 04:09:36 PM PDT 24
Peak memory	209120 kb
Host	smart-69f90df0-9fa6-42da-a349-bd6ed8894d42
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3393112896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.3393112896
Directory	/workspace/48.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/48.keymgr_kmac_rsp_err.691873475
Short name	T294
Test name
Test status
Simulation time	64808495 ps
CPU time	2.57 seconds
Started	Apr 20 04:09:28 PM PDT 24
Finished	Apr 20 04:09:31 PM PDT 24
Peak memory	209280 kb
Host	smart-62992f70-cf22-4d81-b0da-6fbb05f0416e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=691873475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.691873475
Directory	/workspace/48.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/48.keymgr_lc_disable.3173775960
Short name	T969
Test name
Test status
Simulation time	106451626 ps
CPU time	5.62 seconds
Started	Apr 20 04:09:25 PM PDT 24
Finished	Apr 20 04:09:31 PM PDT 24
Peak memory	222356 kb
Host	smart-45a476ca-a807-4afc-968c-ba507b5ad1b2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3173775960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.3173775960
Directory	/workspace/48.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/48.keymgr_random.2431492447
Short name	T1052
Test name
Test status
Simulation time	351738735 ps
CPU time	4.45 seconds
Started	Apr 20 04:09:23 PM PDT 24
Finished	Apr 20 04:09:28 PM PDT 24
Peak memory	207332 kb
Host	smart-ba753050-5136-4977-9cfc-e39e23161ec0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2431492447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.2431492447
Directory	/workspace/48.keymgr_random/latest

Test location	/workspace/coverage/default/48.keymgr_sideload.4152269234
Short name	T131
Test name
Test status
Simulation time	368515496 ps
CPU time	7.24 seconds
Started	Apr 20 04:09:27 PM PDT 24
Finished	Apr 20 04:09:35 PM PDT 24
Peak memory	207812 kb
Host	smart-dc07a052-7928-4be6-b23a-89b0ae0d3e58
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4152269234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.4152269234
Directory	/workspace/48.keymgr_sideload/latest

Test location	/workspace/coverage/default/48.keymgr_sideload_aes.156872436
Short name	T573
Test name
Test status
Simulation time	130033166 ps
CPU time	4.58 seconds
Started	Apr 20 04:09:25 PM PDT 24
Finished	Apr 20 04:09:30 PM PDT 24
Peak memory	208332 kb
Host	smart-d5f5358d-5a96-4d22-a2d5-b44b822dc077
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156872436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.156872436
Directory	/workspace/48.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/48.keymgr_sideload_kmac.1990117027
Short name	T364
Test name
Test status
Simulation time	256167197 ps
CPU time	4.52 seconds
Started	Apr 20 04:09:27 PM PDT 24
Finished	Apr 20 04:09:32 PM PDT 24
Peak memory	207568 kb
Host	smart-e68f2eb9-02ab-4fd7-8f4f-9aba8df7e842
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990117027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.1990117027
Directory	/workspace/48.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/48.keymgr_sideload_otbn.1688913662
Short name	T635
Test name
Test status
Simulation time	1956783568 ps
CPU time	49.17 seconds
Started	Apr 20 04:09:25 PM PDT 24
Finished	Apr 20 04:10:15 PM PDT 24
Peak memory	208788 kb
Host	smart-ea355aa9-bed2-4b9f-a0aa-b490461f3a5d
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688913662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.1688913662
Directory	/workspace/48.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/48.keymgr_sideload_protect.3969451874
Short name	T756
Test name
Test status
Simulation time	449774563 ps
CPU time	2.76 seconds
Started	Apr 20 04:09:27 PM PDT 24
Finished	Apr 20 04:09:30 PM PDT 24
Peak memory	208392 kb
Host	smart-ffa8102f-6538-4796-8b4e-2814c5dec940
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3969451874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.3969451874
Directory	/workspace/48.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/48.keymgr_smoke.3775997778
Short name	T604
Test name
Test status
Simulation time	720249516 ps
CPU time	14.91 seconds
Started	Apr 20 04:09:23 PM PDT 24
Finished	Apr 20 04:09:39 PM PDT 24
Peak memory	208560 kb
Host	smart-7047d0ff-c151-4909-8eb4-1bb52fca08d4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3775997778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.3775997778
Directory	/workspace/48.keymgr_smoke/latest

Test location	/workspace/coverage/default/48.keymgr_stress_all.3447296101
Short name	T245
Test name
Test status
Simulation time	152736898 ps
CPU time	8.24 seconds
Started	Apr 20 04:09:26 PM PDT 24
Finished	Apr 20 04:09:35 PM PDT 24
Peak memory	220284 kb
Host	smart-256a9cf8-236a-422b-bf31-02c3a3ace493
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447296101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.3447296101
Directory	/workspace/48.keymgr_stress_all/latest

Test location	/workspace/coverage/default/48.keymgr_sw_invalid_input.2652134598
Short name	T871
Test name
Test status
Simulation time	144815686 ps
CPU time	5.62 seconds
Started	Apr 20 04:09:25 PM PDT 24
Finished	Apr 20 04:09:31 PM PDT 24
Peak memory	207248 kb
Host	smart-4b887a27-72ea-4286-b04c-1aec4f9531c6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2652134598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.2652134598
Directory	/workspace/48.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/48.keymgr_sync_async_fault_cross.1633891399
Short name	T581
Test name
Test status
Simulation time	697990872 ps
CPU time	2.6 seconds
Started	Apr 20 04:09:26 PM PDT 24
Finished	Apr 20 04:09:29 PM PDT 24
Peak memory	209952 kb
Host	smart-b74b2251-6c2a-4844-a5a7-60ddb1366f08
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1633891399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.1633891399
Directory	/workspace/48.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/49.keymgr_alert_test.2352848569
Short name	T427
Test name
Test status
Simulation time	15751667 ps
CPU time	0.74 seconds
Started	Apr 20 04:09:34 PM PDT 24
Finished	Apr 20 04:09:35 PM PDT 24
Peak memory	205888 kb
Host	smart-e9a4bdaa-ea0e-46d8-a962-0e7cdaed1bc8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352848569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.2352848569
Directory	/workspace/49.keymgr_alert_test/latest

Test location	/workspace/coverage/default/49.keymgr_custom_cm.2114694821
Short name	T38
Test name
Test status
Simulation time	152034554 ps
CPU time	5.14 seconds
Started	Apr 20 04:09:30 PM PDT 24
Finished	Apr 20 04:09:36 PM PDT 24
Peak memory	208920 kb
Host	smart-b6a4e5b7-f231-4342-a575-d54cac661711
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2114694821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.2114694821
Directory	/workspace/49.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/49.keymgr_direct_to_disabled.3191606071
Short name	T858
Test name
Test status
Simulation time	41334626 ps
CPU time	2.26 seconds
Started	Apr 20 04:09:33 PM PDT 24
Finished	Apr 20 04:09:36 PM PDT 24
Peak memory	208996 kb
Host	smart-d155a2f4-592b-40cf-808c-9510666ae3b7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3191606071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.3191606071
Directory	/workspace/49.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/49.keymgr_lc_disable.728059478
Short name	T667
Test name
Test status
Simulation time	59851751 ps
CPU time	3.11 seconds
Started	Apr 20 04:09:30 PM PDT 24
Finished	Apr 20 04:09:33 PM PDT 24
Peak memory	214308 kb
Host	smart-02429184-bafe-46b5-a9d3-e60719391e53
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=728059478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.728059478
Directory	/workspace/49.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/49.keymgr_random.1920325289
Short name	T931
Test name
Test status
Simulation time	861516511 ps
CPU time	6.17 seconds
Started	Apr 20 04:09:32 PM PDT 24
Finished	Apr 20 04:09:39 PM PDT 24
Peak memory	214316 kb
Host	smart-0119a461-8c66-40b9-998d-c8aa715e85c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1920325289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.1920325289
Directory	/workspace/49.keymgr_random/latest

Test location	/workspace/coverage/default/49.keymgr_sideload.2338853350
Short name	T925
Test name
Test status
Simulation time	736820539 ps
CPU time	3.4 seconds
Started	Apr 20 04:09:28 PM PDT 24
Finished	Apr 20 04:09:32 PM PDT 24
Peak memory	206648 kb
Host	smart-1ca6ddb9-3b3a-476c-a302-daac50200ef8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2338853350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.2338853350
Directory	/workspace/49.keymgr_sideload/latest

Test location	/workspace/coverage/default/49.keymgr_sideload_aes.3149731069
Short name	T1037
Test name
Test status
Simulation time	1281998045 ps
CPU time	4.19 seconds
Started	Apr 20 04:09:30 PM PDT 24
Finished	Apr 20 04:09:34 PM PDT 24
Peak memory	209056 kb
Host	smart-a2af6b2a-f17e-439b-8a7a-b50adb22fbeb
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149731069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.3149731069
Directory	/workspace/49.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/49.keymgr_sideload_kmac.1512824522
Short name	T375
Test name
Test status
Simulation time	68972308 ps
CPU time	3.01 seconds
Started	Apr 20 04:09:28 PM PDT 24
Finished	Apr 20 04:09:31 PM PDT 24
Peak memory	208028 kb
Host	smart-64a87028-d5f5-4b16-bcf0-24c97ceed7a8
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512824522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.1512824522
Directory	/workspace/49.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/49.keymgr_sideload_otbn.1120972602
Short name	T774
Test name
Test status
Simulation time	217073435 ps
CPU time	3.21 seconds
Started	Apr 20 04:09:27 PM PDT 24
Finished	Apr 20 04:09:31 PM PDT 24
Peak memory	206740 kb
Host	smart-fee55242-73fd-4ab0-9afb-ceac652598d5
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120972602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.1120972602
Directory	/workspace/49.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/49.keymgr_sideload_protect.4252647161
Short name	T339
Test name
Test status
Simulation time	226060202 ps
CPU time	2.82 seconds
Started	Apr 20 04:09:33 PM PDT 24
Finished	Apr 20 04:09:36 PM PDT 24
Peak memory	217792 kb
Host	smart-96591118-af68-4e16-82e1-e4d77e3f774a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4252647161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.4252647161
Directory	/workspace/49.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/49.keymgr_smoke.2348331150
Short name	T1042
Test name
Test status
Simulation time	523038205 ps
CPU time	12.32 seconds
Started	Apr 20 04:09:28 PM PDT 24
Finished	Apr 20 04:09:40 PM PDT 24
Peak memory	208056 kb
Host	smart-acce4a96-752a-4491-b62b-5dead2bcb402
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2348331150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.2348331150
Directory	/workspace/49.keymgr_smoke/latest

Test location	/workspace/coverage/default/49.keymgr_stress_all.4081660875
Short name	T212
Test name
Test status
Simulation time	12084353319 ps
CPU time	58.06 seconds
Started	Apr 20 04:09:32 PM PDT 24
Finished	Apr 20 04:10:31 PM PDT 24
Peak memory	222592 kb
Host	smart-ca284d5f-d7e0-4109-bcd9-32c065a8eb88
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081660875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.4081660875
Directory	/workspace/49.keymgr_stress_all/latest

Test location	/workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.248121873
Short name	T103
Test name
Test status
Simulation time	208485806 ps
CPU time	2.33 seconds
Started	Apr 20 04:09:29 PM PDT 24
Finished	Apr 20 04:09:32 PM PDT 24
Peak memory	222620 kb
Host	smart-a7169ed7-1e88-4c64-b9a2-460120660b45
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248121873 -assert nopost proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.248121873
Directory	/workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/49.keymgr_sw_invalid_input.1022299965
Short name	T334
Test name
Test status
Simulation time	2282690952 ps
CPU time	60.07 seconds
Started	Apr 20 04:09:30 PM PDT 24
Finished	Apr 20 04:10:30 PM PDT 24
Peak memory	214404 kb
Host	smart-fb5af132-0bdf-45d0-a8b5-eb0d8315f5b0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1022299965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.1022299965
Directory	/workspace/49.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/49.keymgr_sync_async_fault_cross.950443939
Short name	T840
Test name
Test status
Simulation time	216595160 ps
CPU time	2.4 seconds
Started	Apr 20 04:09:32 PM PDT 24
Finished	Apr 20 04:09:35 PM PDT 24
Peak memory	209712 kb
Host	smart-0f985298-ea29-4498-89a8-538f66dbb80a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=950443939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.950443939
Directory	/workspace/49.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/5.keymgr_alert_test.3773596548
Short name	T982
Test name
Test status
Simulation time	8624362 ps
CPU time	0.75 seconds
Started	Apr 20 04:05:17 PM PDT 24
Finished	Apr 20 04:05:18 PM PDT 24
Peak memory	205892 kb
Host	smart-0586949b-7abf-4a5d-ba76-fba263caa751
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773596548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.3773596548
Directory	/workspace/5.keymgr_alert_test/latest

Test location	/workspace/coverage/default/5.keymgr_cfg_regwen.2330401967
Short name	T421
Test name
Test status
Simulation time	129966662 ps
CPU time	2.66 seconds
Started	Apr 20 04:05:10 PM PDT 24
Finished	Apr 20 04:05:13 PM PDT 24
Peak memory	215348 kb
Host	smart-be2ce9e2-d922-4fb4-b03c-874dff2ae3d9
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2330401967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.2330401967
Directory	/workspace/5.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/5.keymgr_custom_cm.3543809374
Short name	T864
Test name
Test status
Simulation time	123793864 ps
CPU time	1.87 seconds
Started	Apr 20 04:05:13 PM PDT 24
Finished	Apr 20 04:05:15 PM PDT 24
Peak memory	215980 kb
Host	smart-5e304a40-ea4e-4e85-9d4d-9601aac4fd7f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3543809374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.3543809374
Directory	/workspace/5.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/5.keymgr_direct_to_disabled.2684307709
Short name	T738
Test name
Test status
Simulation time	43951288 ps
CPU time	1.71 seconds
Started	Apr 20 04:05:08 PM PDT 24
Finished	Apr 20 04:05:10 PM PDT 24
Peak memory	208720 kb
Host	smart-c611ab73-b50b-4461-a729-73dfdff6a997
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2684307709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.2684307709
Directory	/workspace/5.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/5.keymgr_hwsw_invalid_input.704628196
Short name	T962
Test name
Test status
Simulation time	2524885813 ps
CPU time	30.56 seconds
Started	Apr 20 04:05:13 PM PDT 24
Finished	Apr 20 04:05:44 PM PDT 24
Peak memory	214344 kb
Host	smart-620f0c5d-2181-4ab8-a982-94357b09d205
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=704628196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.704628196
Directory	/workspace/5.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/5.keymgr_kmac_rsp_err.1023724165
Short name	T291
Test name
Test status
Simulation time	51167650 ps
CPU time	3.71 seconds
Started	Apr 20 04:05:13 PM PDT 24
Finished	Apr 20 04:05:17 PM PDT 24
Peak memory	214248 kb
Host	smart-e94cd820-5841-4741-a52a-6e65b1c1d443
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1023724165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.1023724165
Directory	/workspace/5.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/5.keymgr_lc_disable.2466131668
Short name	T1016
Test name
Test status
Simulation time	684686404 ps
CPU time	4.13 seconds
Started	Apr 20 04:05:10 PM PDT 24
Finished	Apr 20 04:05:14 PM PDT 24
Peak memory	214228 kb
Host	smart-8a631100-dda0-44d5-bb90-f24e31a3f85d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2466131668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.2466131668
Directory	/workspace/5.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/5.keymgr_random.4282024080
Short name	T276
Test name
Test status
Simulation time	222297457 ps
CPU time	3.74 seconds
Started	Apr 20 04:05:09 PM PDT 24
Finished	Apr 20 04:05:13 PM PDT 24
Peak memory	218416 kb
Host	smart-522a645c-b928-4b2b-91aa-2bc74dcd7efc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4282024080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.4282024080
Directory	/workspace/5.keymgr_random/latest

Test location	/workspace/coverage/default/5.keymgr_sideload.4093377070
Short name	T609
Test name
Test status
Simulation time	456810175 ps
CPU time	15.45 seconds
Started	Apr 20 04:05:08 PM PDT 24
Finished	Apr 20 04:05:23 PM PDT 24
Peak memory	206788 kb
Host	smart-a438d77a-4bd2-4a1b-8f72-243a123d2cb4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4093377070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.4093377070
Directory	/workspace/5.keymgr_sideload/latest

Test location	/workspace/coverage/default/5.keymgr_sideload_aes.2936472662
Short name	T992
Test name
Test status
Simulation time	1064683877 ps
CPU time	7.88 seconds
Started	Apr 20 04:05:06 PM PDT 24
Finished	Apr 20 04:05:14 PM PDT 24
Peak memory	208532 kb
Host	smart-7c8370cf-5c6b-442e-ac74-2c96fc79a41e
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936472662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.2936472662
Directory	/workspace/5.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/5.keymgr_sideload_kmac.3671192086
Short name	T626
Test name
Test status
Simulation time	66839044 ps
CPU time	3.19 seconds
Started	Apr 20 04:05:06 PM PDT 24
Finished	Apr 20 04:05:09 PM PDT 24
Peak memory	208860 kb
Host	smart-f3b31d34-b8ed-4f91-96ee-4b8009bffa3a
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671192086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.3671192086
Directory	/workspace/5.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/5.keymgr_sideload_otbn.4271766811
Short name	T1014
Test name
Test status
Simulation time	447415107 ps
CPU time	12.11 seconds
Started	Apr 20 04:05:09 PM PDT 24
Finished	Apr 20 04:05:22 PM PDT 24
Peak memory	208640 kb
Host	smart-8008e3fa-7af2-455c-b808-dd820b64aaef
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271766811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.4271766811
Directory	/workspace/5.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/5.keymgr_sideload_protect.2023069718
Short name	T1038
Test name
Test status
Simulation time	394096550 ps
CPU time	10.21 seconds
Started	Apr 20 04:05:13 PM PDT 24
Finished	Apr 20 04:05:24 PM PDT 24
Peak memory	208100 kb
Host	smart-2419e961-8326-4872-9dff-83e60d0ec97d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2023069718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.2023069718
Directory	/workspace/5.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/5.keymgr_smoke.3727607948
Short name	T857
Test name
Test status
Simulation time	936983538 ps
CPU time	5.5 seconds
Started	Apr 20 04:05:07 PM PDT 24
Finished	Apr 20 04:05:13 PM PDT 24
Peak memory	206696 kb
Host	smart-abdc33b1-f7fe-4b79-92fb-c5512c6dddfc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3727607948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.3727607948
Directory	/workspace/5.keymgr_smoke/latest

Test location	/workspace/coverage/default/5.keymgr_stress_all.2876914816
Short name	T63
Test name
Test status
Simulation time	956394821 ps
CPU time	36.3 seconds
Started	Apr 20 04:05:13 PM PDT 24
Finished	Apr 20 04:05:50 PM PDT 24
Peak memory	222420 kb
Host	smart-cbb45590-c62d-4907-b52e-c9ef69c2a73c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876914816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.2876914816
Directory	/workspace/5.keymgr_stress_all/latest

Test location	/workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.508676321
Short name	T845
Test name
Test status
Simulation time	130770413 ps
CPU time	7.99 seconds
Started	Apr 20 04:05:12 PM PDT 24
Finished	Apr 20 04:05:20 PM PDT 24
Peak memory	221152 kb
Host	smart-e4971d75-43ce-4fd3-b6c4-1ce6dc67e5e4
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508676321 -assert nopost proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.508676321
Directory	/workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/5.keymgr_sw_invalid_input.433069334
Short name	T564
Test name
Test status
Simulation time	514794572 ps
CPU time	4.95 seconds
Started	Apr 20 04:05:09 PM PDT 24
Finished	Apr 20 04:05:14 PM PDT 24
Peak memory	214208 kb
Host	smart-8f853681-cfcd-4141-997a-48194219b13b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=433069334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.433069334
Directory	/workspace/5.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/5.keymgr_sync_async_fault_cross.1819267924
Short name	T889
Test name
Test status
Simulation time	205382509 ps
CPU time	2.43 seconds
Started	Apr 20 04:05:12 PM PDT 24
Finished	Apr 20 04:05:15 PM PDT 24
Peak memory	210484 kb
Host	smart-36b4ccae-81ff-45c0-929d-cd416398bc83
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1819267924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.1819267924
Directory	/workspace/5.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/6.keymgr_alert_test.3274323679
Short name	T855
Test name
Test status
Simulation time	43204274 ps
CPU time	0.8 seconds
Started	Apr 20 04:05:22 PM PDT 24
Finished	Apr 20 04:05:23 PM PDT 24
Peak memory	205872 kb
Host	smart-085971a7-93f8-4ad2-b52c-e6a00d3a0b43
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274323679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.3274323679
Directory	/workspace/6.keymgr_alert_test/latest

Test location	/workspace/coverage/default/6.keymgr_custom_cm.3652687719
Short name	T946
Test name
Test status
Simulation time	305764215 ps
CPU time	5.57 seconds
Started	Apr 20 04:05:19 PM PDT 24
Finished	Apr 20 04:05:25 PM PDT 24
Peak memory	218800 kb
Host	smart-893d74fb-7ec2-4c0f-ba09-c077c1ea822e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3652687719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.3652687719
Directory	/workspace/6.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/6.keymgr_direct_to_disabled.3272115395
Short name	T67
Test name
Test status
Simulation time	255220745 ps
CPU time	3.22 seconds
Started	Apr 20 04:05:20 PM PDT 24
Finished	Apr 20 04:05:24 PM PDT 24
Peak memory	218316 kb
Host	smart-3262e3b2-2c84-43a2-8a47-fc91233a828f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3272115395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.3272115395
Directory	/workspace/6.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/6.keymgr_hwsw_invalid_input.3269451175
Short name	T949
Test name
Test status
Simulation time	1228470941 ps
CPU time	32.75 seconds
Started	Apr 20 04:05:19 PM PDT 24
Finished	Apr 20 04:05:52 PM PDT 24
Peak memory	214396 kb
Host	smart-5418b0b7-e60a-4834-af43-fe3bf27f0d33
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3269451175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.3269451175
Directory	/workspace/6.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/6.keymgr_kmac_rsp_err.2731497056
Short name	T251
Test name
Test status
Simulation time	777714451 ps
CPU time	21 seconds
Started	Apr 20 04:05:20 PM PDT 24
Finished	Apr 20 04:05:41 PM PDT 24
Peak memory	210576 kb
Host	smart-7cfe324d-60e1-4dd4-8c00-83014ee2c4c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2731497056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.2731497056
Directory	/workspace/6.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/6.keymgr_lc_disable.2954309861
Short name	T915
Test name
Test status
Simulation time	599914602 ps
CPU time	6.73 seconds
Started	Apr 20 04:05:20 PM PDT 24
Finished	Apr 20 04:05:27 PM PDT 24
Peak memory	222436 kb
Host	smart-0c1ef043-fc32-400d-884b-ae81836191dd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2954309861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.2954309861
Directory	/workspace/6.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/6.keymgr_random.2753924866
Short name	T272
Test name
Test status
Simulation time	126909069 ps
CPU time	3.23 seconds
Started	Apr 20 04:05:17 PM PDT 24
Finished	Apr 20 04:05:20 PM PDT 24
Peak memory	214364 kb
Host	smart-c71a23cd-374f-42b6-b47d-90e4fb1400fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2753924866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.2753924866
Directory	/workspace/6.keymgr_random/latest

Test location	/workspace/coverage/default/6.keymgr_sideload.3884434482
Short name	T685
Test name
Test status
Simulation time	110228107 ps
CPU time	4.05 seconds
Started	Apr 20 04:05:15 PM PDT 24
Finished	Apr 20 04:05:19 PM PDT 24
Peak memory	208736 kb
Host	smart-7d55e00a-3073-4029-9463-15a574e72c5f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3884434482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.3884434482
Directory	/workspace/6.keymgr_sideload/latest

Test location	/workspace/coverage/default/6.keymgr_sideload_aes.2999680404
Short name	T1068
Test name
Test status
Simulation time	102714510 ps
CPU time	2.91 seconds
Started	Apr 20 04:05:16 PM PDT 24
Finished	Apr 20 04:05:20 PM PDT 24
Peak memory	206992 kb
Host	smart-bd0f6ac2-0149-4d92-9735-364896d36a00
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999680404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.2999680404
Directory	/workspace/6.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/6.keymgr_sideload_kmac.1128650782
Short name	T905
Test name
Test status
Simulation time	1834477629 ps
CPU time	25.76 seconds
Started	Apr 20 04:05:15 PM PDT 24
Finished	Apr 20 04:05:41 PM PDT 24
Peak memory	208816 kb
Host	smart-81ddbd92-f4d0-4269-add9-2048f766e5a0
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128650782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.1128650782
Directory	/workspace/6.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/6.keymgr_sideload_otbn.3700892788
Short name	T769
Test name
Test status
Simulation time	84913090 ps
CPU time	3.53 seconds
Started	Apr 20 04:05:17 PM PDT 24
Finished	Apr 20 04:05:21 PM PDT 24
Peak memory	208800 kb
Host	smart-ca713a69-44f4-471a-b51c-f39a17feaaa2
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700892788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.3700892788
Directory	/workspace/6.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/6.keymgr_sideload_protect.1379012595
Short name	T638
Test name
Test status
Simulation time	2083894804 ps
CPU time	5.37 seconds
Started	Apr 20 04:05:21 PM PDT 24
Finished	Apr 20 04:05:26 PM PDT 24
Peak memory	214300 kb
Host	smart-990323c0-9cfe-45f4-9b36-222a43c3ccdf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1379012595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.1379012595
Directory	/workspace/6.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/6.keymgr_smoke.953020724
Short name	T393
Test name
Test status
Simulation time	90262265 ps
CPU time	3.81 seconds
Started	Apr 20 04:05:14 PM PDT 24
Finished	Apr 20 04:05:18 PM PDT 24
Peak memory	208612 kb
Host	smart-288722a6-eba1-421d-81a9-f410bada2d5f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=953020724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.953020724
Directory	/workspace/6.keymgr_smoke/latest

Test location	/workspace/coverage/default/6.keymgr_stress_all.3224528955
Short name	T221
Test name
Test status
Simulation time	770634285 ps
CPU time	21.26 seconds
Started	Apr 20 04:05:19 PM PDT 24
Finished	Apr 20 04:05:41 PM PDT 24
Peak memory	210100 kb
Host	smart-6340c9f7-9cbe-40ed-80f5-fcb367779049
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224528955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.3224528955
Directory	/workspace/6.keymgr_stress_all/latest

Test location	/workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.419823868
Short name	T976
Test name
Test status
Simulation time	1070330752 ps
CPU time	13.35 seconds
Started	Apr 20 04:05:20 PM PDT 24
Finished	Apr 20 04:05:33 PM PDT 24
Peak memory	222604 kb
Host	smart-90944fd0-6b95-4bdb-8a37-40ad72f40ab1
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419823868 -assert nopost proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.419823868
Directory	/workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/6.keymgr_sw_invalid_input.1391422604
Short name	T224
Test name
Test status
Simulation time	300887991 ps
CPU time	9.92 seconds
Started	Apr 20 04:05:21 PM PDT 24
Finished	Apr 20 04:05:31 PM PDT 24
Peak memory	218536 kb
Host	smart-f2ddfbda-5c5b-4bed-b8fe-36bfb0d0dfa4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1391422604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.1391422604
Directory	/workspace/6.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/6.keymgr_sync_async_fault_cross.3392865882
Short name	T947
Test name
Test status
Simulation time	260504507 ps
CPU time	2.72 seconds
Started	Apr 20 04:05:19 PM PDT 24
Finished	Apr 20 04:05:22 PM PDT 24
Peak memory	210148 kb
Host	smart-85d9d5cd-8d79-4510-8902-030c1302da85
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3392865882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.3392865882
Directory	/workspace/6.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/7.keymgr_alert_test.4202950210
Short name	T718
Test name
Test status
Simulation time	30920894 ps
CPU time	0.76 seconds
Started	Apr 20 04:05:39 PM PDT 24
Finished	Apr 20 04:05:40 PM PDT 24
Peak memory	205836 kb
Host	smart-efafd3f9-0863-489d-ac2c-aad90b8cd39e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202950210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.4202950210
Directory	/workspace/7.keymgr_alert_test/latest

Test location	/workspace/coverage/default/7.keymgr_cfg_regwen.894624145
Short name	T411
Test name
Test status
Simulation time	274748520 ps
CPU time	14.84 seconds
Started	Apr 20 04:05:28 PM PDT 24
Finished	Apr 20 04:05:43 PM PDT 24
Peak memory	215864 kb
Host	smart-246fd6a4-93a0-423a-9148-e208c8136e6b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=894624145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.894624145
Directory	/workspace/7.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/7.keymgr_custom_cm.657539854
Short name	T19
Test name
Test status
Simulation time	278272984 ps
CPU time	4.69 seconds
Started	Apr 20 04:05:30 PM PDT 24
Finished	Apr 20 04:05:35 PM PDT 24
Peak memory	222736 kb
Host	smart-5c4f043a-fc66-4960-97a0-dcdb0e3f8ce4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=657539854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.657539854
Directory	/workspace/7.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/7.keymgr_direct_to_disabled.4133329283
Short name	T818
Test name
Test status
Simulation time	309284208 ps
CPU time	3.97 seconds
Started	Apr 20 04:05:25 PM PDT 24
Finished	Apr 20 04:05:30 PM PDT 24
Peak memory	209480 kb
Host	smart-282d34d0-ee8c-4e38-a89a-c7dc5cd7fe53
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4133329283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.4133329283
Directory	/workspace/7.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/7.keymgr_hwsw_invalid_input.1291737769
Short name	T284
Test name
Test status
Simulation time	961811865 ps
CPU time	5.84 seconds
Started	Apr 20 04:05:30 PM PDT 24
Finished	Apr 20 04:05:36 PM PDT 24
Peak memory	208420 kb
Host	smart-d928ce5f-c0ef-4c4a-ab65-de69e1e3b093
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1291737769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.1291737769
Directory	/workspace/7.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/7.keymgr_lc_disable.1146836377
Short name	T831
Test name
Test status
Simulation time	574190135 ps
CPU time	8.82 seconds
Started	Apr 20 04:05:27 PM PDT 24
Finished	Apr 20 04:05:36 PM PDT 24
Peak memory	214324 kb
Host	smart-8da3cf5a-ae8f-4a06-8c08-bd4a447e2d70
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1146836377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.1146836377
Directory	/workspace/7.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/7.keymgr_random.758495785
Short name	T110
Test name
Test status
Simulation time	457619419 ps
CPU time	5.52 seconds
Started	Apr 20 04:05:27 PM PDT 24
Finished	Apr 20 04:05:33 PM PDT 24
Peak memory	209332 kb
Host	smart-1d83708d-61c9-4276-b61b-8970ecf6a4b8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=758495785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.758495785
Directory	/workspace/7.keymgr_random/latest

Test location	/workspace/coverage/default/7.keymgr_sideload.1354951861
Short name	T624
Test name
Test status
Simulation time	37088451 ps
CPU time	1.98 seconds
Started	Apr 20 04:05:23 PM PDT 24
Finished	Apr 20 04:05:25 PM PDT 24
Peak memory	207820 kb
Host	smart-1de8ca99-1fd2-45ce-92e2-b815cfba3d51
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1354951861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.1354951861
Directory	/workspace/7.keymgr_sideload/latest

Test location	/workspace/coverage/default/7.keymgr_sideload_aes.1663142489
Short name	T275
Test name
Test status
Simulation time	1051942456 ps
CPU time	26.61 seconds
Started	Apr 20 04:05:27 PM PDT 24
Finished	Apr 20 04:05:54 PM PDT 24
Peak memory	207900 kb
Host	smart-5cb8ac75-d30b-43e1-9fbe-c34ce8517059
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663142489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.1663142489
Directory	/workspace/7.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/7.keymgr_sideload_kmac.2164243601
Short name	T869
Test name
Test status
Simulation time	6724102748 ps
CPU time	92.44 seconds
Started	Apr 20 04:05:26 PM PDT 24
Finished	Apr 20 04:06:59 PM PDT 24
Peak memory	208464 kb
Host	smart-8d360dd3-197b-40fd-be38-84bb8373f2eb
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164243601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.2164243601
Directory	/workspace/7.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/7.keymgr_sideload_otbn.2138123615
Short name	T195
Test name
Test status
Simulation time	32853008 ps
CPU time	2.48 seconds
Started	Apr 20 04:05:26 PM PDT 24
Finished	Apr 20 04:05:29 PM PDT 24
Peak memory	206792 kb
Host	smart-1bbf4881-f540-4c9b-888a-86f2b5ea9e85
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138123615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.2138123615
Directory	/workspace/7.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/7.keymgr_sideload_protect.333647914
Short name	T759
Test name
Test status
Simulation time	1321174866 ps
CPU time	14.36 seconds
Started	Apr 20 04:05:30 PM PDT 24
Finished	Apr 20 04:05:44 PM PDT 24
Peak memory	208592 kb
Host	smart-2d4b5155-0c02-4c06-8444-6879a6c921fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=333647914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.333647914
Directory	/workspace/7.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/7.keymgr_smoke.712702699
Short name	T425
Test name
Test status
Simulation time	326282706 ps
CPU time	3.13 seconds
Started	Apr 20 04:05:22 PM PDT 24
Finished	Apr 20 04:05:26 PM PDT 24
Peak memory	206596 kb
Host	smart-f8038972-c630-4b72-b4ee-17ce4ead991b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=712702699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.712702699
Directory	/workspace/7.keymgr_smoke/latest

Test location	/workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.2882120709
Short name	T207
Test name
Test status
Simulation time	530233538 ps
CPU time	2.93 seconds
Started	Apr 20 04:05:34 PM PDT 24
Finished	Apr 20 04:05:37 PM PDT 24
Peak memory	222588 kb
Host	smart-0b256ace-636a-4878-a224-48d6ecf723b0
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882120709 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.2882120709
Directory	/workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/7.keymgr_sw_invalid_input.2418117292
Short name	T746
Test name
Test status
Simulation time	89505115 ps
CPU time	3.16 seconds
Started	Apr 20 04:05:25 PM PDT 24
Finished	Apr 20 04:05:29 PM PDT 24
Peak memory	207380 kb
Host	smart-2a83ef11-a0bf-4197-b530-1483c7d28554
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2418117292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.2418117292
Directory	/workspace/7.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/7.keymgr_sync_async_fault_cross.3822232692
Short name	T854
Test name
Test status
Simulation time	39871068 ps
CPU time	2.47 seconds
Started	Apr 20 04:05:30 PM PDT 24
Finished	Apr 20 04:05:33 PM PDT 24
Peak memory	210168 kb
Host	smart-67257449-786a-4ca1-ad38-dc8a6dde13d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3822232692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.3822232692
Directory	/workspace/7.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/8.keymgr_alert_test.2797944847
Short name	T742
Test name
Test status
Simulation time	10335478 ps
CPU time	0.72 seconds
Started	Apr 20 04:05:38 PM PDT 24
Finished	Apr 20 04:05:39 PM PDT 24
Peak memory	205568 kb
Host	smart-efa7af9e-6f3f-49dd-be13-e49a10cdaff2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797944847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.2797944847
Directory	/workspace/8.keymgr_alert_test/latest

Test location	/workspace/coverage/default/8.keymgr_cfg_regwen.4220888783
Short name	T285
Test name
Test status
Simulation time	48507624 ps
CPU time	3.67 seconds
Started	Apr 20 04:05:40 PM PDT 24
Finished	Apr 20 04:05:44 PM PDT 24
Peak memory	215268 kb
Host	smart-69d2ddd5-0aab-4a35-a8f9-44a9e0991032
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4220888783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.4220888783
Directory	/workspace/8.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/8.keymgr_custom_cm.2099780498
Short name	T32
Test name
Test status
Simulation time	108007147 ps
CPU time	5.12 seconds
Started	Apr 20 04:05:36 PM PDT 24
Finished	Apr 20 04:05:41 PM PDT 24
Peak memory	209436 kb
Host	smart-53374ff3-f4ca-4296-b817-fce957d5ba0d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2099780498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.2099780498
Directory	/workspace/8.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/8.keymgr_direct_to_disabled.2314583900
Short name	T896
Test name
Test status
Simulation time	38080701 ps
CPU time	2.04 seconds
Started	Apr 20 04:05:32 PM PDT 24
Finished	Apr 20 04:05:34 PM PDT 24
Peak memory	207572 kb
Host	smart-e7833a5e-a76e-4e3e-9925-b7cef8bcad08
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2314583900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.2314583900
Directory	/workspace/8.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/8.keymgr_hwsw_invalid_input.3551238279
Short name	T1039
Test name
Test status
Simulation time	106560337 ps
CPU time	4.8 seconds
Started	Apr 20 04:05:35 PM PDT 24
Finished	Apr 20 04:05:40 PM PDT 24
Peak memory	209564 kb
Host	smart-110df838-41e4-422f-b7ae-d2abd420bc0c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3551238279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.3551238279
Directory	/workspace/8.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/8.keymgr_kmac_rsp_err.1627729751
Short name	T1062
Test name
Test status
Simulation time	1211097115 ps
CPU time	9.91 seconds
Started	Apr 20 04:05:39 PM PDT 24
Finished	Apr 20 04:05:50 PM PDT 24
Peak memory	210860 kb
Host	smart-1c942d51-113b-4d7a-a95e-9f66a591ad01
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1627729751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.1627729751
Directory	/workspace/8.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/8.keymgr_lc_disable.2612104101
Short name	T313
Test name
Test status
Simulation time	68456290 ps
CPU time	4.06 seconds
Started	Apr 20 04:05:33 PM PDT 24
Finished	Apr 20 04:05:37 PM PDT 24
Peak memory	214340 kb
Host	smart-7baa9d76-739c-4511-8bbc-971d5e1aee04
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2612104101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.2612104101
Directory	/workspace/8.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/8.keymgr_random.1878967004
Short name	T368
Test name
Test status
Simulation time	462244064 ps
CPU time	5.54 seconds
Started	Apr 20 04:05:33 PM PDT 24
Finished	Apr 20 04:05:39 PM PDT 24
Peak memory	209664 kb
Host	smart-d00490e4-51ad-45fc-a1cf-2c9ee5354844
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1878967004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.1878967004
Directory	/workspace/8.keymgr_random/latest

Test location	/workspace/coverage/default/8.keymgr_sideload.167677375
Short name	T999
Test name
Test status
Simulation time	1593989232 ps
CPU time	11.09 seconds
Started	Apr 20 04:05:39 PM PDT 24
Finished	Apr 20 04:05:51 PM PDT 24
Peak memory	208064 kb
Host	smart-a9ae0564-6ab4-4d92-ab41-e4488f44d863
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=167677375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.167677375
Directory	/workspace/8.keymgr_sideload/latest

Test location	/workspace/coverage/default/8.keymgr_sideload_aes.2234729829
Short name	T610
Test name
Test status
Simulation time	72370605 ps
CPU time	3.52 seconds
Started	Apr 20 04:05:40 PM PDT 24
Finished	Apr 20 04:05:44 PM PDT 24
Peak memory	208516 kb
Host	smart-1322e029-131f-496c-97f6-36d762a015db
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234729829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.2234729829
Directory	/workspace/8.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/8.keymgr_sideload_kmac.2687086445
Short name	T657
Test name
Test status
Simulation time	2028641910 ps
CPU time	38.6 seconds
Started	Apr 20 04:05:39 PM PDT 24
Finished	Apr 20 04:06:18 PM PDT 24
Peak memory	208548 kb
Host	smart-56334df2-8b7a-4a23-bef8-aba7f8094c4d
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687086445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.2687086445
Directory	/workspace/8.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/8.keymgr_sideload_otbn.3882310991
Short name	T782
Test name
Test status
Simulation time	237016209 ps
CPU time	3.32 seconds
Started	Apr 20 04:05:33 PM PDT 24
Finished	Apr 20 04:05:36 PM PDT 24
Peak memory	206876 kb
Host	smart-22e6e5a9-521f-4a41-aace-672791d20e81
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882310991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.3882310991
Directory	/workspace/8.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/8.keymgr_sideload_protect.2831951142
Short name	T370
Test name
Test status
Simulation time	331425828 ps
CPU time	2.98 seconds
Started	Apr 20 04:05:37 PM PDT 24
Finished	Apr 20 04:05:40 PM PDT 24
Peak memory	218068 kb
Host	smart-c08c7b35-95f4-4a0e-beec-5d5da3d2d465
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2831951142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.2831951142
Directory	/workspace/8.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/8.keymgr_smoke.3272233960
Short name	T743
Test name
Test status
Simulation time	307898259 ps
CPU time	4.46 seconds
Started	Apr 20 04:05:33 PM PDT 24
Finished	Apr 20 04:05:38 PM PDT 24
Peak memory	208548 kb
Host	smart-b01e21a8-1886-4260-98de-8f458a888059
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3272233960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.3272233960
Directory	/workspace/8.keymgr_smoke/latest

Test location	/workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.4199792321
Short name	T776
Test name
Test status
Simulation time	409783848 ps
CPU time	4.18 seconds
Started	Apr 20 04:05:38 PM PDT 24
Finished	Apr 20 04:05:43 PM PDT 24
Peak memory	222340 kb
Host	smart-9b534329-4ea2-4c15-9fe8-a36a67b163ed
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199792321 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.4199792321
Directory	/workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/8.keymgr_sw_invalid_input.2355705334
Short name	T385
Test name
Test status
Simulation time	107070076 ps
CPU time	4.12 seconds
Started	Apr 20 04:05:40 PM PDT 24
Finished	Apr 20 04:05:45 PM PDT 24
Peak memory	208688 kb
Host	smart-af58f9f8-5f49-4a40-878a-038f50f591e7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2355705334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.2355705334
Directory	/workspace/8.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/8.keymgr_sync_async_fault_cross.2869824635
Short name	T160
Test name
Test status
Simulation time	69365019 ps
CPU time	3.31 seconds
Started	Apr 20 04:05:38 PM PDT 24
Finished	Apr 20 04:05:42 PM PDT 24
Peak memory	210372 kb
Host	smart-ac4010ec-dd73-4698-9dfb-a156de9e63c8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2869824635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.2869824635
Directory	/workspace/8.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/9.keymgr_alert_test.3578403827
Short name	T1001
Test name
Test status
Simulation time	16875621 ps
CPU time	0.73 seconds
Started	Apr 20 04:05:42 PM PDT 24
Finished	Apr 20 04:05:43 PM PDT 24
Peak memory	205816 kb
Host	smart-662f9df5-7967-44a4-be10-5d6f33e0e8ad
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578403827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.3578403827
Directory	/workspace/9.keymgr_alert_test/latest

Test location	/workspace/coverage/default/9.keymgr_direct_to_disabled.683808971
Short name	T932
Test name
Test status
Simulation time	59598723 ps
CPU time	2.75 seconds
Started	Apr 20 04:05:39 PM PDT 24
Finished	Apr 20 04:05:42 PM PDT 24
Peak memory	218324 kb
Host	smart-dbebef77-12af-4bd3-9af3-192bc121002c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=683808971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.683808971
Directory	/workspace/9.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/9.keymgr_hwsw_invalid_input.1638222041
Short name	T356
Test name
Test status
Simulation time	76432715 ps
CPU time	4 seconds
Started	Apr 20 04:05:39 PM PDT 24
Finished	Apr 20 04:05:43 PM PDT 24
Peak memory	220188 kb
Host	smart-84217d50-5358-41a1-9c73-9fa6a6bcf4dc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1638222041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.1638222041
Directory	/workspace/9.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/9.keymgr_kmac_rsp_err.4092487164
Short name	T296
Test name
Test status
Simulation time	557156532 ps
CPU time	7.36 seconds
Started	Apr 20 04:05:44 PM PDT 24
Finished	Apr 20 04:05:52 PM PDT 24
Peak memory	211016 kb
Host	smart-bdd0e864-713f-4587-bb22-6a90a022a0fb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4092487164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.4092487164
Directory	/workspace/9.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/9.keymgr_lc_disable.79038343
Short name	T1007
Test name
Test status
Simulation time	609052267 ps
CPU time	6.52 seconds
Started	Apr 20 04:05:39 PM PDT 24
Finished	Apr 20 04:05:46 PM PDT 24
Peak memory	214256 kb
Host	smart-9284206e-777c-48cb-83dc-35106d3f5323
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=79038343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.79038343
Directory	/workspace/9.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/9.keymgr_random.2024907057
Short name	T259
Test name
Test status
Simulation time	604859018 ps
CPU time	7.09 seconds
Started	Apr 20 04:05:39 PM PDT 24
Finished	Apr 20 04:05:47 PM PDT 24
Peak memory	218540 kb
Host	smart-ca420ed5-f73c-4365-89e2-f226e3fb48b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2024907057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.2024907057
Directory	/workspace/9.keymgr_random/latest

Test location	/workspace/coverage/default/9.keymgr_sideload.3156066788
Short name	T770
Test name
Test status
Simulation time	253426818 ps
CPU time	2.79 seconds
Started	Apr 20 04:05:35 PM PDT 24
Finished	Apr 20 04:05:38 PM PDT 24
Peak memory	206708 kb
Host	smart-d33bed4a-9dbf-48a1-a47c-750e09050937
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3156066788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.3156066788
Directory	/workspace/9.keymgr_sideload/latest

Test location	/workspace/coverage/default/9.keymgr_sideload_aes.807899411
Short name	T678
Test name
Test status
Simulation time	65863525 ps
CPU time	2.46 seconds
Started	Apr 20 04:05:40 PM PDT 24
Finished	Apr 20 04:05:43 PM PDT 24
Peak memory	206876 kb
Host	smart-9fc3bce0-33b3-4434-a252-e126db500e71
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807899411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.807899411
Directory	/workspace/9.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/9.keymgr_sideload_kmac.645126351
Short name	T1006
Test name
Test status
Simulation time	35676081 ps
CPU time	2.39 seconds
Started	Apr 20 04:05:37 PM PDT 24
Finished	Apr 20 04:05:39 PM PDT 24
Peak memory	206760 kb
Host	smart-7f1fb061-ddf7-41c0-b987-abe9662d7f61
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645126351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.645126351
Directory	/workspace/9.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/9.keymgr_sideload_otbn.2041618929
Short name	T199
Test name
Test status
Simulation time	797323875 ps
CPU time	8.39 seconds
Started	Apr 20 04:05:39 PM PDT 24
Finished	Apr 20 04:05:48 PM PDT 24
Peak memory	207024 kb
Host	smart-8d0bde68-3ac8-4a0f-999b-24f6a35653b4
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041618929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.2041618929
Directory	/workspace/9.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/9.keymgr_sideload_protect.2853810192
Short name	T1044
Test name
Test status
Simulation time	641726196 ps
CPU time	5.15 seconds
Started	Apr 20 04:05:43 PM PDT 24
Finished	Apr 20 04:05:49 PM PDT 24
Peak memory	218244 kb
Host	smart-ebb52bec-e2b8-4e30-96c1-3f036ab336a8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2853810192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.2853810192
Directory	/workspace/9.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/9.keymgr_smoke.1884787349
Short name	T388
Test name
Test status
Simulation time	157137526 ps
CPU time	4 seconds
Started	Apr 20 04:05:37 PM PDT 24
Finished	Apr 20 04:05:41 PM PDT 24
Peak memory	206744 kb
Host	smart-9b51b93a-f5c9-40f1-b52e-8f9e9c3a861b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1884787349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.1884787349
Directory	/workspace/9.keymgr_smoke/latest

Test location	/workspace/coverage/default/9.keymgr_stress_all.1443851616
Short name	T215
Test name
Test status
Simulation time	687857449 ps
CPU time	10.43 seconds
Started	Apr 20 04:05:43 PM PDT 24
Finished	Apr 20 04:05:54 PM PDT 24
Peak memory	215032 kb
Host	smart-75108749-a367-4f96-8b52-42e5e865f9fb
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443851616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.1443851616
Directory	/workspace/9.keymgr_stress_all/latest

Test location	/workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.2475445270
Short name	T395
Test name
Test status
Simulation time	1885918767 ps
CPU time	20.86 seconds
Started	Apr 20 04:05:43 PM PDT 24
Finished	Apr 20 04:06:04 PM PDT 24
Peak memory	222544 kb
Host	smart-1d07b738-1485-441f-96d5-98c81e03bdeb
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475445270 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.2475445270
Directory	/workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/9.keymgr_sw_invalid_input.85296600
Short name	T249
Test name
Test status
Simulation time	331445632 ps
CPU time	4.63 seconds
Started	Apr 20 04:05:40 PM PDT 24
Finished	Apr 20 04:05:45 PM PDT 24
Peak memory	207904 kb
Host	smart-aeb3ab90-fba3-4f0c-b6ba-d1c83d0770a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=85296600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.85296600
Directory	/workspace/9.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/9.keymgr_sync_async_fault_cross.1585902690
Short name	T694
Test name
Test status
Simulation time	96972050 ps
CPU time	1.96 seconds
Started	Apr 20 04:05:42 PM PDT 24
Finished	Apr 20 04:05:45 PM PDT 24
Peak memory	210616 kb
Host	smart-e695d733-55d8-469e-b25b-ed72e68d134a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1585902690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.1585902690
Directory	/workspace/9.keymgr_sync_async_fault_cross/latest