Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5111883	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

585681

1

T1

172

T2

227

T3

199

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	5296353	1			T1	318		T2	560		T3	2293
values[0x0]	198362	1			T1	44		T2	88		T3	57
values[0x1]	202849	1			T1	45		T2	67		T3	50

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3462809	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2234755

1

T1

221

T2

369

T3

899

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16424	1			T3	6		T4	8		T15	1
valid_sources[0x01]	21192	1			T3	15		T4	5		T16	2
valid_sources[0x02]	20406	1			T3	7		T4	10		T19	6
valid_sources[0x03]	16085	1			T3	6		T4	8		T15	3
valid_sources[0x04]	19286	1			T1	5		T3	10		T4	5
valid_sources[0x05]	16207	1			T1	2		T3	10		T4	11
valid_sources[0x06]	16206	1			T1	1		T3	10		T4	7
valid_sources[0x07]	17774	1			T1	3		T3	15		T4	7
valid_sources[0x08]	16264	1			T1	6		T3	6		T4	5
valid_sources[0x09]	16590	1			T1	3		T3	9		T4	2
valid_sources[0x0a]	19694	1			T1	2		T3	6		T4	5
valid_sources[0x0b]	15920	1			T1	6		T3	14		T4	7
valid_sources[0x0c]	20662	1			T3	8		T4	11		T16	7
valid_sources[0x0d]	29727	1			T1	2		T3	13		T4	6
valid_sources[0x0e]	18526	1			T3	22		T4	6		T15	2
valid_sources[0x0f]	23494	1			T3	6		T4	5		T16	3
valid_sources[0x10]	17129	1			T3	7		T4	7		T19	3
valid_sources[0x11]	21070	1			T3	6		T4	8		T16	2
valid_sources[0x12]	17354	1			T3	12		T4	3		T16	5
valid_sources[0x13]	17593	1			T3	6		T4	7		T16	2
valid_sources[0x14]	21278	1			T1	3		T3	9		T4	9
valid_sources[0x15]	16649	1			T1	1		T3	8		T4	8
valid_sources[0x16]	15337	1			T1	1		T3	19		T4	3
valid_sources[0x17]	19360	1			T1	1		T3	9		T4	5
valid_sources[0x18]	25757	1			T1	8		T3	5		T4	3
valid_sources[0x19]	15987	1			T1	1		T3	4		T4	8
valid_sources[0x1a]	17024	1			T1	1		T3	11		T4	7
valid_sources[0x1b]	15993	1			T3	8		T4	10		T15	1
valid_sources[0x1c]	16609	1			T3	8		T4	6		T15	4
valid_sources[0x1d]	16332	1			T3	2		T4	7		T15	11
valid_sources[0x1e]	18622	1			T1	1		T3	8		T4	9
valid_sources[0x1f]	16021	1			T1	4		T3	9		T4	6
valid_sources[0x20]	15871	1			T1	2		T3	19		T4	9
valid_sources[0x21]	26596	1			T1	3		T3	9		T4	16
valid_sources[0x22]	49488	1			T3	17		T4	7		T16	1
valid_sources[0x23]	17077	1			T1	3		T3	9		T4	7
valid_sources[0x24]	20403	1			T3	5		T4	5		T16	1
valid_sources[0x25]	15501	1			T1	1		T3	8		T4	3
valid_sources[0x26]	18494	1			T1	3		T3	2		T4	7
valid_sources[0x27]	47870	1			T1	1		T3	20		T4	6
valid_sources[0x28]	18253	1			T3	7		T4	6		T16	4
valid_sources[0x29]	22897	1			T1	5		T3	10		T4	5
valid_sources[0x2a]	16796	1			T1	3		T3	6		T4	5
valid_sources[0x2b]	16625	1			T3	11		T4	11		T15	3
valid_sources[0x2c]	18852	1			T3	10		T4	3		T15	2
valid_sources[0x2d]	20335	1			T3	11		T4	5		T16	1
valid_sources[0x2e]	18531	1			T1	3		T3	8		T4	6
valid_sources[0x2f]	19899	1			T1	2		T3	22		T4	5
valid_sources[0x30]	15608	1			T3	6		T4	3		T16	3
valid_sources[0x31]	22618	1			T1	5		T3	7		T4	3
valid_sources[0x32]	16965	1			T1	2		T3	2		T4	5
valid_sources[0x33]	16680	1			T3	1		T4	6		T15	6
valid_sources[0x34]	16970	1			T1	1		T3	7		T4	2
valid_sources[0x35]	15835	1			T1	2		T3	5		T4	6
valid_sources[0x36]	16874	1			T1	1		T3	15		T4	7
valid_sources[0x37]	18171	1			T1	3		T3	20		T4	4
valid_sources[0x38]	18033	1			T1	7		T3	11		T4	7
valid_sources[0x39]	17193	1			T3	16		T4	6		T15	6
valid_sources[0x3a]	15874	1			T1	2		T3	5		T4	10
valid_sources[0x3b]	15970	1			T3	11		T4	5		T15	4
valid_sources[0x3c]	20992	1			T1	5		T3	9		T4	6
valid_sources[0x3d]	34766	1			T3	5		T4	10		T15	1
valid_sources[0x3e]	16685	1			T3	5		T4	2		T15	8
valid_sources[0x3f]	16580	1			T1	1		T3	9		T4	11
valid_sources[0x40]	36622	1			T1	1		T3	8		T4	7
valid_sources[0x41]	16651	1			T1	3		T3	14		T4	8
valid_sources[0x42]	16318	1			T3	3		T4	14		T16	1
valid_sources[0x43]	15961	1			T3	6		T4	9		T16	2
valid_sources[0x44]	16310	1			T1	11		T3	4		T4	9
valid_sources[0x45]	22540	1			T1	9		T3	9		T4	7
valid_sources[0x46]	16028	1			T1	2		T3	8		T4	10
valid_sources[0x47]	15861	1			T1	1		T3	11		T4	6
valid_sources[0x48]	16729	1			T1	1		T3	17		T4	7
valid_sources[0x49]	15948	1			T1	1		T3	7		T4	6
valid_sources[0x4a]	23232	1			T1	6		T3	4		T4	6
valid_sources[0x4b]	20149	1			T1	2		T3	10		T4	10
valid_sources[0x4c]	30108	1			T3	8		T4	5		T16	1
valid_sources[0x4d]	28065	1			T3	10		T4	9		T15	2
valid_sources[0x4e]	28315	1			T1	1		T3	15		T4	7
valid_sources[0x4f]	16896	1			T3	8		T4	5		T15	2
valid_sources[0x50]	17337	1			T3	15		T4	7		T16	1
valid_sources[0x51]	16773	1			T1	6		T3	3		T4	9
valid_sources[0x52]	30946	1			T3	12		T4	5		T15	2
valid_sources[0x53]	16109	1			T3	9		T4	5		T15	8
valid_sources[0x54]	17731	1			T1	1		T3	5		T4	4
valid_sources[0x55]	26402	1			T3	1		T4	7		T15	3
valid_sources[0x56]	19224	1			T1	3		T3	7		T4	5
valid_sources[0x57]	16740	1			T3	11		T4	9		T15	6
valid_sources[0x58]	17125	1			T3	16		T4	6		T15	2
valid_sources[0x59]	19345	1			T3	8		T4	3		T16	2
valid_sources[0x5a]	17407	1			T3	7		T4	12		T15	5
valid_sources[0x5b]	25724	1			T3	8		T4	8		T16	2
valid_sources[0x5c]	15852	1			T1	3		T3	12		T4	5
valid_sources[0x5d]	15473	1			T3	7		T4	4		T16	3
valid_sources[0x5e]	19294	1			T1	2		T3	11		T4	5
valid_sources[0x5f]	16596	1			T1	1		T3	2		T4	5
valid_sources[0x60]	19443	1			T1	2		T3	12		T4	3
valid_sources[0x61]	19698	1			T3	3		T4	7		T15	1
valid_sources[0x62]	17235	1			T3	13		T4	13		T19	7
valid_sources[0x63]	15142	1			T3	7		T4	10		T16	1
valid_sources[0x64]	33340	1			T3	16		T4	11		T15	1
valid_sources[0x65]	32998	1			T3	6		T4	8		T15	5
valid_sources[0x66]	19275	1			T3	10		T4	6		T15	2
valid_sources[0x67]	18769	1			T1	4		T3	8		T4	9
valid_sources[0x68]	17962	1			T1	2		T3	18		T4	8
valid_sources[0x69]	16176	1			T1	4		T3	9		T4	7
valid_sources[0x6a]	37298	1			T3	2		T4	5		T19	8
valid_sources[0x6b]	15598	1			T1	1		T3	10		T4	9
valid_sources[0x6c]	17349	1			T3	10		T4	9		T15	8
valid_sources[0x6d]	15855	1			T3	6		T4	7		T16	1
valid_sources[0x6e]	15532	1			T1	4		T3	2		T4	3
valid_sources[0x6f]	16170	1			T1	2		T3	7		T4	8
valid_sources[0x70]	31946	1			T1	3		T3	4		T4	5
valid_sources[0x71]	22899	1			T3	15		T4	3		T16	1
valid_sources[0x72]	19534	1			T3	5		T4	12		T16	1
valid_sources[0x73]	16870	1			T3	10		T4	7		T15	4
valid_sources[0x74]	17231	1			T3	12		T4	5		T19	2
valid_sources[0x75]	16509	1			T1	4		T3	7		T4	9
valid_sources[0x76]	21006	1			T3	5		T4	7		T15	1
valid_sources[0x77]	16287	1			T3	7		T4	7		T16	2
valid_sources[0x78]	38832	1			T1	2		T3	11		T4	7
valid_sources[0x79]	34719	1			T3	12		T4	14		T16	1
valid_sources[0x7a]	18454	1			T1	4		T3	10		T4	4
valid_sources[0x7b]	19209	1			T1	6		T3	10		T4	9
valid_sources[0x7c]	16773	1			T3	3		T4	4		T16	2
valid_sources[0x7d]	15571	1			T1	4		T3	11		T4	4
valid_sources[0x7e]	15892	1			T3	5		T4	8		T15	1
valid_sources[0x7f]	18688	1			T3	13		T4	9		T15	4
valid_sources[0x80]	18074	1			T3	11		T4	10		T16	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

314357

1

T1

141

T2

134

T3

161

values[0x0]

all_enables

biggest_size

142432

1

T1

22

T2

53

T3

26

values[0x1]

all_enables

biggest_size

128892

1

T1

9

T2

40

T3

12