Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3580043	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

584657

1

T1

143

T2

187

T3

733

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3773421	1			T1	392		T2	1011		T3	499
values[0x0]	194081	1			T1	51		T2	47		T3	219
values[0x1]	197198	1			T1	38		T2	44		T3	234

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2440979	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1723721

1

T1

221

T2

456

T3

793

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	14683	1			T1	1		T2	1		T3	6
valid_sources[0x01]	12569	1			T2	10		T3	3		T16	13
valid_sources[0x02]	13073	1			T2	11		T3	4		T4	20
valid_sources[0x03]	12492	1			T1	7		T3	4		T16	16
valid_sources[0x04]	12437	1			T1	4		T2	1		T3	3
valid_sources[0x05]	12164	1			T2	2		T3	5		T16	10
valid_sources[0x06]	13383	1			T1	3		T2	15		T3	2
valid_sources[0x07]	17827	1			T3	6		T16	10		T17	7
valid_sources[0x08]	12675	1			T1	9		T3	5		T16	10
valid_sources[0x09]	12210	1			T2	5		T3	4		T16	13
valid_sources[0x0a]	13903	1			T2	4		T3	1		T4	2
valid_sources[0x0b]	11253	1			T1	8		T3	7		T16	6
valid_sources[0x0c]	12156	1			T1	4		T3	5		T16	6
valid_sources[0x0d]	15187	1			T2	6		T3	3		T16	10
valid_sources[0x0e]	14368	1			T1	6		T2	6		T3	4
valid_sources[0x0f]	12371	1			T1	2		T2	5		T3	5
valid_sources[0x10]	27861	1			T1	4		T2	15		T3	4
valid_sources[0x11]	12018	1			T1	2		T2	1		T3	6
valid_sources[0x12]	15703	1			T2	22		T3	5		T16	10
valid_sources[0x13]	12000	1			T1	3		T2	1		T3	7
valid_sources[0x14]	14548	1			T3	4		T4	90		T16	3
valid_sources[0x15]	13491	1			T1	7		T2	6		T3	11
valid_sources[0x16]	13430	1			T1	1		T3	1		T16	8
valid_sources[0x17]	12189	1			T1	2		T2	3		T3	5
valid_sources[0x18]	13655	1			T1	1		T2	3		T3	4
valid_sources[0x19]	58717	1			T1	10		T3	3		T16	11
valid_sources[0x1a]	17555	1			T2	1		T3	3		T4	18
valid_sources[0x1b]	19661	1			T1	2		T2	5		T3	3
valid_sources[0x1c]	33570	1			T2	2		T16	12		T17	3
valid_sources[0x1d]	13703	1			T2	9		T3	3		T4	10
valid_sources[0x1e]	12097	1			T3	5		T16	8		T17	9
valid_sources[0x1f]	11777	1			T1	5		T3	5		T16	11
valid_sources[0x20]	12497	1			T1	8		T2	18		T3	3
valid_sources[0x21]	13298	1			T1	1		T2	8		T3	6
valid_sources[0x22]	22974	1			T2	3		T3	4		T16	6
valid_sources[0x23]	14273	1			T3	5		T16	12		T18	13
valid_sources[0x24]	11971	1			T1	1		T2	4		T3	5
valid_sources[0x25]	12083	1			T1	5		T2	4		T3	3
valid_sources[0x26]	13020	1			T1	1		T2	9		T3	5
valid_sources[0x27]	12121	1			T2	18		T3	3		T16	10
valid_sources[0x28]	13916	1			T1	2		T2	10		T3	6
valid_sources[0x29]	64238	1			T1	3		T3	2		T4	74
valid_sources[0x2a]	11804	1			T1	2		T2	2		T3	1
valid_sources[0x2b]	14101	1			T1	3		T2	1		T3	2
valid_sources[0x2c]	85509	1			T1	2		T2	8		T3	5
valid_sources[0x2d]	12325	1			T2	6		T3	4		T16	9
valid_sources[0x2e]	16854	1			T2	5		T3	4		T16	14
valid_sources[0x2f]	12958	1			T3	1		T16	7		T17	1
valid_sources[0x30]	23367	1			T1	1		T2	5		T3	4
valid_sources[0x31]	11831	1			T1	1		T2	9		T3	5
valid_sources[0x32]	12316	1			T3	1		T16	10		T17	6
valid_sources[0x33]	12719	1			T3	4		T16	7		T17	5
valid_sources[0x34]	12906	1			T2	3		T3	2		T16	8
valid_sources[0x35]	15211	1			T3	4		T16	11		T17	2
valid_sources[0x36]	12388	1			T2	11		T3	6		T16	9
valid_sources[0x37]	13167	1			T3	4		T16	9		T17	8
valid_sources[0x38]	12264	1			T1	4		T3	3		T16	16
valid_sources[0x39]	12465	1			T1	9		T3	2		T16	8
valid_sources[0x3a]	12613	1			T1	1		T2	11		T3	5
valid_sources[0x3b]	11990	1			T1	3		T2	3		T3	2
valid_sources[0x3c]	12281	1			T2	3		T3	1		T16	9
valid_sources[0x3d]	12270	1			T1	2		T2	9		T3	4
valid_sources[0x3e]	30830	1			T2	4		T3	3		T16	7
valid_sources[0x3f]	12410	1			T2	3		T3	1		T16	8
valid_sources[0x40]	23761	1			T1	2		T2	7		T3	2
valid_sources[0x41]	13561	1			T1	2		T3	4		T16	4
valid_sources[0x42]	12566	1			T1	3		T2	4		T3	5
valid_sources[0x43]	12065	1			T3	4		T16	8		T17	3
valid_sources[0x44]	38710	1			T3	1		T16	10		T17	1
valid_sources[0x45]	14890	1			T1	7		T2	11		T3	4
valid_sources[0x46]	12187	1			T1	1		T2	14		T16	11
valid_sources[0x47]	13274	1			T1	5		T2	2		T3	2
valid_sources[0x48]	12280	1			T1	2		T2	3		T3	8
valid_sources[0x49]	13445	1			T2	6		T3	3		T16	9
valid_sources[0x4a]	13760	1			T3	4		T16	2		T17	1
valid_sources[0x4b]	13628	1			T1	3		T3	5		T16	11
valid_sources[0x4c]	12381	1			T2	6		T3	6		T16	11
valid_sources[0x4d]	12595	1			T2	1		T3	4		T16	7
valid_sources[0x4e]	12363	1			T1	5		T2	7		T3	3
valid_sources[0x4f]	19094	1			T2	2		T3	7		T16	9
valid_sources[0x50]	12828	1			T1	1		T2	8		T3	1
valid_sources[0x51]	13608	1			T3	2		T16	14		T17	9
valid_sources[0x52]	12488	1			T2	7		T3	4		T16	9
valid_sources[0x53]	12007	1			T1	2		T2	20		T3	3
valid_sources[0x54]	17588	1			T2	2		T3	7		T16	13
valid_sources[0x55]	14109	1			T3	2		T16	12		T17	8
valid_sources[0x56]	24955	1			T1	1		T2	8		T3	3
valid_sources[0x57]	11986	1			T2	1		T3	5		T16	6
valid_sources[0x58]	12590	1			T1	8		T2	8		T3	4
valid_sources[0x59]	18779	1			T1	4		T2	7		T3	3
valid_sources[0x5a]	12587	1			T1	1		T2	2		T3	7
valid_sources[0x5b]	12742	1			T2	4		T3	2		T16	14
valid_sources[0x5c]	12021	1			T3	3		T4	19		T16	16
valid_sources[0x5d]	12548	1			T3	2		T16	11		T18	6
valid_sources[0x5e]	13264	1			T1	3		T3	4		T16	5
valid_sources[0x5f]	13457	1			T2	5		T3	1		T16	13
valid_sources[0x60]	16965	1			T3	4		T16	8		T18	17
valid_sources[0x61]	12859	1			T1	1		T3	6		T16	10
valid_sources[0x62]	11956	1			T3	2		T16	9		T18	5
valid_sources[0x63]	12363	1			T1	2		T2	4		T3	1
valid_sources[0x64]	12317	1			T2	6		T3	5		T16	17
valid_sources[0x65]	14111	1			T1	1		T3	4		T16	10
valid_sources[0x66]	12074	1			T2	10		T3	6		T16	11
valid_sources[0x67]	12707	1			T1	1		T2	5		T3	4
valid_sources[0x68]	13855	1			T2	3		T3	3		T16	4
valid_sources[0x69]	22103	1			T1	2		T2	1		T3	4
valid_sources[0x6a]	12028	1			T1	5		T3	3		T16	12
valid_sources[0x6b]	12386	1			T2	3		T3	5		T16	10
valid_sources[0x6c]	12221	1			T2	3		T3	7		T16	8
valid_sources[0x6d]	11943	1			T1	8		T2	1		T3	3
valid_sources[0x6e]	15979	1			T3	4		T16	10		T18	7
valid_sources[0x6f]	25783	1			T1	10		T2	8		T3	4
valid_sources[0x70]	12423	1			T3	7		T16	10		T17	1
valid_sources[0x71]	77580	1			T1	6		T3	1		T16	5
valid_sources[0x72]	24142	1			T3	5		T16	7		T17	2
valid_sources[0x73]	12110	1			T2	2		T3	7		T4	24
valid_sources[0x74]	20124	1			T2	10		T3	2		T4	10
valid_sources[0x75]	13323	1			T1	1		T2	5		T3	2
valid_sources[0x76]	12127	1			T2	16		T3	2		T16	13
valid_sources[0x77]	13336	1			T3	3		T16	13		T18	4
valid_sources[0x78]	12263	1			T1	4		T2	3		T3	3
valid_sources[0x79]	11695	1			T1	3		T3	6		T16	7
valid_sources[0x7a]	13705	1			T2	2		T3	6		T16	5
valid_sources[0x7b]	25497	1			T1	20		T3	6		T16	4
valid_sources[0x7c]	12737	1			T2	6		T3	3		T4	31
valid_sources[0x7d]	14835	1			T2	4		T3	7		T16	9
valid_sources[0x7e]	12524	1			T1	2		T2	8		T3	6
valid_sources[0x7f]	15003	1			T2	7		T3	6		T16	6
valid_sources[0x80]	13633	1			T1	4		T3	2		T16	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

316527

1

T1

114

T2

153

T3

310

values[0x0]

all_enables

biggest_size

140728

1

T1

14

T2

21

T3

211

values[0x1]

all_enables

biggest_size

127402

1

T1

15

T2

13

T3

212