Module Definition
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Module : keymgr_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.keymgr_csr_assert 100.00 100.00


Module Instance : tb.dut.keymgr_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.08 96.15 98.39 99.96 95.92 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : keymgr_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 32 32 100.00 32 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 32 32 100.00 32 100.00



Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
TlulOOBAddrErr_A 28615896 16326 0 0
attest_sw_binding_0_rd_A 28615896 562 0 0
attest_sw_binding_1_rd_A 28615896 578 0 0
attest_sw_binding_2_rd_A 28615896 666 0 0
attest_sw_binding_3_rd_A 28615896 561 0 0
attest_sw_binding_4_rd_A 28615896 612 0 0
attest_sw_binding_5_rd_A 28615896 482 0 0
attest_sw_binding_6_rd_A 28615896 533 0 0
attest_sw_binding_7_rd_A 28615896 563 0 0
intr_enable_rd_A 28615896 1174 0 0
key_version_rd_A 28615896 600 0 0
max_creator_key_ver_regwen_rd_A 28615896 639 0 0
max_owner_int_key_ver_regwen_rd_A 28615896 586 0 0
max_owner_key_ver_regwen_rd_A 28615896 588 0 0
reseed_interval_regwen_rd_A 28615896 640 0 0
salt_0_rd_A 28615896 588 0 0
salt_1_rd_A 28615896 625 0 0
salt_2_rd_A 28615896 499 0 0
salt_3_rd_A 28615896 630 0 0
salt_4_rd_A 28615896 526 0 0
salt_5_rd_A 28615896 609 0 0
salt_6_rd_A 28615896 570 0 0
salt_7_rd_A 28615896 655 0 0
sealing_sw_binding_0_rd_A 28615896 542 0 0
sealing_sw_binding_1_rd_A 28615896 665 0 0
sealing_sw_binding_2_rd_A 28615896 572 0 0
sealing_sw_binding_3_rd_A 28615896 472 0 0
sealing_sw_binding_4_rd_A 28615896 585 0 0
sealing_sw_binding_5_rd_A 28615896 678 0 0
sealing_sw_binding_6_rd_A 28615896 583 0 0
sealing_sw_binding_7_rd_A 28615896 560 0 0
sideload_clear_rd_A 28615896 578 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 28615896 16326 0 0
T3 6617 10 0 0
T4 3880 0 0 0
T5 3810 0 0 0
T12 1825 0 0 0
T16 30642 0 0 0
T17 2822 0 0 0
T18 6366 0 0 0
T19 2255 0 0 0
T40 4849 0 0 0
T42 3963 0 0 0
T102 0 238 0 0
T114 0 514 0 0
T115 0 134 0 0
T124 0 363 0 0
T125 0 48 0 0
T126 0 667 0 0
T127 0 189 0 0
T128 0 1 0 0
T130 0 88 0 0

attest_sw_binding_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 28615896 562 0 0
T26 7372 0 0 0
T115 18312 22 0 0
T124 27000 0 0 0
T125 15150 21 0 0
T126 0 13 0 0
T130 0 7 0 0
T137 0 7 0 0
T164 0 9 0 0
T176 0 38 0 0
T177 0 2 0 0
T178 0 5 0 0
T179 0 21 0 0
T180 9852 0 0 0
T181 4595 0 0 0
T182 111226 0 0 0
T183 11214 0 0 0
T184 17531 0 0 0
T185 29253 0 0 0

attest_sw_binding_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 28615896 578 0 0
T26 7372 0 0 0
T115 18312 29 0 0
T124 27000 0 0 0
T125 15150 27 0 0
T126 0 13 0 0
T137 0 10 0 0
T164 0 12 0 0
T176 0 22 0 0
T178 0 5 0 0
T179 0 23 0 0
T180 9852 0 0 0
T181 4595 0 0 0
T182 111226 0 0 0
T183 11214 0 0 0
T184 17531 0 0 0
T185 29253 0 0 0
T186 0 2 0 0
T187 0 16 0 0

attest_sw_binding_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 28615896 666 0 0
T26 7372 0 0 0
T115 18312 30 0 0
T124 27000 0 0 0
T125 15150 11 0 0
T126 0 9 0 0
T130 0 9 0 0
T176 0 20 0 0
T178 0 10 0 0
T179 0 29 0 0
T180 9852 0 0 0
T181 4595 0 0 0
T182 111226 0 0 0
T183 11214 0 0 0
T184 17531 0 0 0
T185 29253 0 0 0
T186 0 10 0 0
T187 0 9 0 0
T188 0 59 0 0

attest_sw_binding_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 28615896 561 0 0
T26 7372 0 0 0
T115 18312 18 0 0
T124 27000 0 0 0
T125 15150 16 0 0
T130 0 6 0 0
T137 0 11 0 0
T164 0 1 0 0
T176 0 28 0 0
T178 0 3 0 0
T179 0 41 0 0
T180 9852 0 0 0
T181 4595 0 0 0
T182 111226 0 0 0
T183 11214 0 0 0
T184 17531 0 0 0
T185 29253 0 0 0
T186 0 13 0 0
T187 0 8 0 0

attest_sw_binding_4_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 28615896 612 0 0
T26 7372 0 0 0
T115 18312 34 0 0
T124 27000 0 0 0
T125 15150 11 0 0
T126 0 1 0 0
T130 0 10 0 0
T137 0 12 0 0
T176 0 22 0 0
T177 0 11 0 0
T178 0 10 0 0
T179 0 25 0 0
T180 9852 0 0 0
T181 4595 0 0 0
T182 111226 0 0 0
T183 11214 0 0 0
T184 17531 0 0 0
T185 29253 0 0 0
T186 0 24 0 0

attest_sw_binding_5_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 28615896 482 0 0
T26 7372 0 0 0
T115 18312 27 0 0
T124 27000 0 0 0
T125 15150 7 0 0
T130 0 8 0 0
T137 0 10 0 0
T164 0 1 0 0
T176 0 26 0 0
T177 0 2 0 0
T178 0 7 0 0
T179 0 20 0 0
T180 9852 0 0 0
T181 4595 0 0 0
T182 111226 0 0 0
T183 11214 0 0 0
T184 17531 0 0 0
T185 29253 0 0 0
T186 0 11 0 0

attest_sw_binding_6_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 28615896 533 0 0
T26 7372 0 0 0
T115 18312 22 0 0
T124 27000 0 0 0
T125 15150 12 0 0
T126 0 9 0 0
T164 0 9 0 0
T176 0 18 0 0
T178 0 7 0 0
T179 0 22 0 0
T180 9852 0 0 0
T181 4595 0 0 0
T182 111226 0 0 0
T183 11214 0 0 0
T184 17531 0 0 0
T185 29253 0 0 0
T186 0 18 0 0
T187 0 8 0 0
T188 0 73 0 0

attest_sw_binding_7_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 28615896 563 0 0
T26 7372 0 0 0
T115 18312 18 0 0
T124 27000 0 0 0
T125 15150 20 0 0
T126 0 4 0 0
T130 0 10 0 0
T137 0 14 0 0
T164 0 5 0 0
T176 0 25 0 0
T178 0 3 0 0
T179 0 15 0 0
T180 9852 0 0 0
T181 4595 0 0 0
T182 111226 0 0 0
T183 11214 0 0 0
T184 17531 0 0 0
T185 29253 0 0 0
T186 0 7 0 0

intr_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 28615896 1174 0 0
T26 7372 0 0 0
T60 109734 18 0 0
T115 18312 37 0 0
T124 27000 0 0 0
T125 0 32 0 0
T126 0 10 0 0
T130 0 13 0 0
T176 0 22 0 0
T180 9852 0 0 0
T181 4595 0 0 0
T182 111226 0 0 0
T183 11214 0 0 0
T184 17531 0 0 0
T185 29253 0 0 0
T189 0 4 0 0
T190 0 17 0 0
T191 0 3 0 0
T192 0 11 0 0

key_version_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 28615896 600 0 0
T26 7372 0 0 0
T115 18312 56 0 0
T124 27000 0 0 0
T125 15150 14 0 0
T130 0 25 0 0
T176 0 29 0 0
T178 0 5 0 0
T179 0 31 0 0
T180 9852 0 0 0
T181 4595 0 0 0
T182 111226 0 0 0
T183 11214 0 0 0
T184 17531 0 0 0
T185 29253 0 0 0
T186 0 7 0 0
T187 0 1 0 0
T188 0 61 0 0
T193 0 6 0 0

max_creator_key_ver_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 28615896 639 0 0
T26 7372 0 0 0
T115 18312 46 0 0
T124 27000 0 0 0
T125 15150 9 0 0
T126 0 7 0 0
T130 0 12 0 0
T137 0 20 0 0
T164 0 14 0 0
T176 0 24 0 0
T177 0 4 0 0
T178 0 15 0 0
T179 0 20 0 0
T180 9852 0 0 0
T181 4595 0 0 0
T182 111226 0 0 0
T183 11214 0 0 0
T184 17531 0 0 0
T185 29253 0 0 0

max_owner_int_key_ver_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 28615896 586 0 0
T26 7372 0 0 0
T115 18312 25 0 0
T124 27000 0 0 0
T125 15150 29 0 0
T130 0 5 0 0
T137 0 16 0 0
T164 0 1 0 0
T176 0 21 0 0
T178 0 12 0 0
T179 0 29 0 0
T180 9852 0 0 0
T181 4595 0 0 0
T182 111226 0 0 0
T183 11214 0 0 0
T184 17531 0 0 0
T185 29253 0 0 0
T186 0 12 0 0
T187 0 7 0 0

max_owner_key_ver_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 28615896 588 0 0
T26 7372 0 0 0
T115 18312 41 0 0
T124 27000 0 0 0
T125 15150 17 0 0
T126 0 9 0 0
T130 0 12 0 0
T176 0 20 0 0
T178 0 11 0 0
T179 0 24 0 0
T180 9852 0 0 0
T181 4595 0 0 0
T182 111226 0 0 0
T183 11214 0 0 0
T184 17531 0 0 0
T185 29253 0 0 0
T186 0 22 0 0
T187 0 10 0 0
T188 0 65 0 0

reseed_interval_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 28615896 640 0 0
T26 7372 0 0 0
T115 18312 27 0 0
T124 27000 0 0 0
T125 15150 28 0 0
T126 0 11 0 0
T130 0 5 0 0
T137 0 1 0 0
T164 0 3 0 0
T176 0 29 0 0
T177 0 5 0 0
T178 0 5 0 0
T179 0 29 0 0
T180 9852 0 0 0
T181 4595 0 0 0
T182 111226 0 0 0
T183 11214 0 0 0
T184 17531 0 0 0
T185 29253 0 0 0

salt_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 28615896 588 0 0
T26 7372 0 0 0
T115 18312 51 0 0
T124 27000 0 0 0
T125 15150 24 0 0
T130 0 11 0 0
T137 0 11 0 0
T164 0 4 0 0
T176 0 15 0 0
T178 0 2 0 0
T179 0 26 0 0
T180 9852 0 0 0
T181 4595 0 0 0
T182 111226 0 0 0
T183 11214 0 0 0
T184 17531 0 0 0
T185 29253 0 0 0
T186 0 17 0 0
T187 0 6 0 0

salt_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 28615896 625 0 0
T26 7372 0 0 0
T115 18312 23 0 0
T124 27000 0 0 0
T125 15150 24 0 0
T126 0 13 0 0
T137 0 12 0 0
T176 0 31 0 0
T178 0 7 0 0
T179 0 25 0 0
T180 9852 0 0 0
T181 4595 0 0 0
T182 111226 0 0 0
T183 11214 0 0 0
T184 17531 0 0 0
T185 29253 0 0 0
T186 0 7 0 0
T187 0 14 0 0
T188 0 61 0 0

salt_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 28615896 499 0 0
T26 7372 0 0 0
T115 18312 21 0 0
T124 27000 0 0 0
T125 15150 18 0 0
T126 0 13 0 0
T137 0 4 0 0
T176 0 22 0 0
T178 0 12 0 0
T179 0 21 0 0
T180 9852 0 0 0
T181 4595 0 0 0
T182 111226 0 0 0
T183 11214 0 0 0
T184 17531 0 0 0
T185 29253 0 0 0
T186 0 12 0 0
T188 0 55 0 0
T193 0 15 0 0

salt_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 28615896 630 0 0
T26 7372 0 0 0
T115 18312 31 0 0
T124 27000 0 0 0
T125 15150 12 0 0
T130 0 9 0 0
T137 0 8 0 0
T176 0 16 0 0
T178 0 13 0 0
T179 0 30 0 0
T180 9852 0 0 0
T181 4595 0 0 0
T182 111226 0 0 0
T183 11214 0 0 0
T184 17531 0 0 0
T185 29253 0 0 0
T186 0 10 0 0
T187 0 2 0 0
T188 0 61 0 0

salt_4_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 28615896 526 0 0
T26 7372 0 0 0
T115 18312 44 0 0
T124 27000 0 0 0
T125 15150 19 0 0
T126 0 3 0 0
T130 0 9 0 0
T176 0 30 0 0
T178 0 5 0 0
T179 0 15 0 0
T180 9852 0 0 0
T181 4595 0 0 0
T182 111226 0 0 0
T183 11214 0 0 0
T184 17531 0 0 0
T185 29253 0 0 0
T186 0 4 0 0
T187 0 2 0 0
T188 0 57 0 0

salt_5_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 28615896 609 0 0
T26 7372 0 0 0
T115 18312 31 0 0
T124 27000 0 0 0
T125 15150 2 0 0
T126 0 16 0 0
T130 0 8 0 0
T137 0 10 0 0
T164 0 4 0 0
T176 0 22 0 0
T178 0 12 0 0
T179 0 37 0 0
T180 9852 0 0 0
T181 4595 0 0 0
T182 111226 0 0 0
T183 11214 0 0 0
T184 17531 0 0 0
T185 29253 0 0 0
T186 0 11 0 0

salt_6_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 28615896 570 0 0
T26 7372 0 0 0
T115 18312 58 0 0
T124 27000 0 0 0
T125 15150 19 0 0
T126 0 8 0 0
T130 0 6 0 0
T137 0 6 0 0
T164 0 5 0 0
T176 0 28 0 0
T178 0 7 0 0
T179 0 24 0 0
T180 9852 0 0 0
T181 4595 0 0 0
T182 111226 0 0 0
T183 11214 0 0 0
T184 17531 0 0 0
T185 29253 0 0 0
T186 0 19 0 0

salt_7_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 28615896 655 0 0
T26 7372 0 0 0
T115 18312 47 0 0
T124 27000 0 0 0
T125 15150 23 0 0
T126 0 12 0 0
T130 0 10 0 0
T164 0 4 0 0
T176 0 25 0 0
T177 0 10 0 0
T178 0 8 0 0
T179 0 33 0 0
T180 9852 0 0 0
T181 4595 0 0 0
T182 111226 0 0 0
T183 11214 0 0 0
T184 17531 0 0 0
T185 29253 0 0 0
T186 0 17 0 0

sealing_sw_binding_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 28615896 542 0 0
T26 7372 0 0 0
T115 18312 18 0 0
T124 27000 0 0 0
T125 15150 11 0 0
T126 0 3 0 0
T130 0 15 0 0
T176 0 23 0 0
T178 0 5 0 0
T179 0 28 0 0
T180 9852 0 0 0
T181 4595 0 0 0
T182 111226 0 0 0
T183 11214 0 0 0
T184 17531 0 0 0
T185 29253 0 0 0
T186 0 19 0 0
T188 0 70 0 0
T193 0 5 0 0

sealing_sw_binding_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 28615896 665 0 0
T26 7372 0 0 0
T115 18312 53 0 0
T124 27000 0 0 0
T125 15150 6 0 0
T126 0 10 0 0
T130 0 13 0 0
T137 0 6 0 0
T176 0 35 0 0
T177 0 7 0 0
T178 0 9 0 0
T179 0 26 0 0
T180 9852 0 0 0
T181 4595 0 0 0
T182 111226 0 0 0
T183 11214 0 0 0
T184 17531 0 0 0
T185 29253 0 0 0
T186 0 13 0 0

sealing_sw_binding_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 28615896 572 0 0
T26 7372 0 0 0
T115 18312 30 0 0
T124 27000 0 0 0
T125 15150 11 0 0
T126 0 6 0 0
T130 0 1 0 0
T137 0 15 0 0
T176 0 17 0 0
T178 0 10 0 0
T179 0 21 0 0
T180 9852 0 0 0
T181 4595 0 0 0
T182 111226 0 0 0
T183 11214 0 0 0
T184 17531 0 0 0
T185 29253 0 0 0
T186 0 5 0 0
T187 0 12 0 0

sealing_sw_binding_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 28615896 472 0 0
T26 7372 0 0 0
T115 18312 28 0 0
T124 27000 0 0 0
T125 15150 15 0 0
T130 0 12 0 0
T176 0 7 0 0
T177 0 8 0 0
T179 0 16 0 0
T180 9852 0 0 0
T181 4595 0 0 0
T182 111226 0 0 0
T183 11214 0 0 0
T184 17531 0 0 0
T185 29253 0 0 0
T186 0 2 0 0
T187 0 4 0 0
T188 0 39 0 0
T193 0 7 0 0

sealing_sw_binding_4_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 28615896 585 0 0
T26 7372 0 0 0
T115 18312 34 0 0
T124 27000 0 0 0
T125 15150 24 0 0
T126 0 6 0 0
T130 0 8 0 0
T137 0 7 0 0
T164 0 2 0 0
T176 0 28 0 0
T177 0 7 0 0
T178 0 8 0 0
T179 0 12 0 0
T180 9852 0 0 0
T181 4595 0 0 0
T182 111226 0 0 0
T183 11214 0 0 0
T184 17531 0 0 0
T185 29253 0 0 0

sealing_sw_binding_5_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 28615896 678 0 0
T26 7372 0 0 0
T115 18312 34 0 0
T124 27000 0 0 0
T125 15150 11 0 0
T126 0 15 0 0
T130 0 16 0 0
T137 0 7 0 0
T164 0 17 0 0
T176 0 23 0 0
T177 0 9 0 0
T178 0 13 0 0
T179 0 17 0 0
T180 9852 0 0 0
T181 4595 0 0 0
T182 111226 0 0 0
T183 11214 0 0 0
T184 17531 0 0 0
T185 29253 0 0 0

sealing_sw_binding_6_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 28615896 583 0 0
T26 7372 0 0 0
T115 18312 36 0 0
T124 27000 0 0 0
T125 15150 14 0 0
T126 0 7 0 0
T130 0 25 0 0
T164 0 3 0 0
T176 0 24 0 0
T178 0 11 0 0
T179 0 21 0 0
T180 9852 0 0 0
T181 4595 0 0 0
T182 111226 0 0 0
T183 11214 0 0 0
T184 17531 0 0 0
T185 29253 0 0 0
T186 0 7 0 0
T187 0 7 0 0

sealing_sw_binding_7_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 28615896 560 0 0
T26 7372 0 0 0
T115 18312 11 0 0
T124 27000 0 0 0
T125 15150 15 0 0
T126 0 4 0 0
T130 0 6 0 0
T137 0 6 0 0
T164 0 7 0 0
T176 0 17 0 0
T178 0 4 0 0
T179 0 20 0 0
T180 9852 0 0 0
T181 4595 0 0 0
T182 111226 0 0 0
T183 11214 0 0 0
T184 17531 0 0 0
T185 29253 0 0 0
T186 0 15 0 0

sideload_clear_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 28615896 578 0 0
T26 7372 0 0 0
T115 18312 28 0 0
T124 27000 0 0 0
T125 15150 30 0 0
T130 0 8 0 0
T137 0 3 0 0
T164 0 4 0 0
T176 0 27 0 0
T178 0 2 0 0
T179 0 23 0 0
T180 9852 0 0 0
T181 4595 0 0 0
T182 111226 0 0 0
T183 11214 0 0 0
T184 17531 0 0 0
T185 29253 0 0 0
T186 0 17 0 0
T188 0 53 0 0