Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3753511	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

564827

1

T1

131

T2

172

T3

9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3936176	1			T1	769		T2	319		T3	1
values[0x0]	189723	1			T1	40		T2	56		T3	17
values[0x1]	192439	1			T1	36		T2	68		T3	16

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2555024	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1763314

1

T1

323

T2

222

T3

12

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	12068	1			T1	6		T2	3		T4	16
valid_sources[0x01]	15151	1			T1	3		T2	3		T4	18
valid_sources[0x02]	11819	1			T1	5		T2	1		T4	15
valid_sources[0x03]	22833	1			T1	1		T4	26		T15	10
valid_sources[0x04]	11766	1			T1	6		T2	3		T4	2
valid_sources[0x05]	12394	1			T1	5		T2	1		T4	19
valid_sources[0x06]	12112	1			T1	2		T2	1		T4	33
valid_sources[0x07]	12681	1			T1	3		T4	27		T5	1
valid_sources[0x08]	22712	1			T4	19		T5	1		T15	5
valid_sources[0x09]	11673	1			T1	7		T2	5		T4	22
valid_sources[0x0a]	12332	1			T1	3		T4	11		T5	4
valid_sources[0x0b]	17371	1			T2	8		T4	19		T15	4
valid_sources[0x0c]	11676	1			T1	3		T2	1		T4	15
valid_sources[0x0d]	12728	1			T1	4		T2	1		T4	16
valid_sources[0x0e]	12665	1			T1	2		T4	7		T5	4
valid_sources[0x0f]	19208	1			T1	5		T2	3		T4	27
valid_sources[0x10]	11875	1			T4	10		T5	1		T15	4
valid_sources[0x11]	14986	1			T1	1		T4	15		T15	1
valid_sources[0x12]	11463	1			T2	1		T4	15		T5	1
valid_sources[0x13]	11501	1			T1	2		T2	2		T4	25
valid_sources[0x14]	11710	1			T1	2		T4	10		T5	3
valid_sources[0x15]	12840	1			T1	8		T2	1		T4	10
valid_sources[0x16]	11804	1			T1	4		T2	5		T4	8
valid_sources[0x17]	19780	1			T1	3		T2	2		T4	21
valid_sources[0x18]	11709	1			T1	2		T4	26		T5	2
valid_sources[0x19]	12282	1			T1	3		T2	1		T4	7
valid_sources[0x1a]	13137	1			T1	1		T2	1		T4	30
valid_sources[0x1b]	14721	1			T1	1		T2	1		T4	26
valid_sources[0x1c]	13166	1			T1	3		T4	21		T5	3
valid_sources[0x1d]	11843	1			T1	4		T2	2		T4	18
valid_sources[0x1e]	26473	1			T1	1		T4	15		T5	2
valid_sources[0x1f]	11985	1			T1	2		T2	1		T4	13
valid_sources[0x20]	11731	1			T1	7		T2	2		T4	16
valid_sources[0x21]	22143	1			T1	5		T4	22		T5	1
valid_sources[0x22]	27096	1			T1	7		T4	21		T5	2
valid_sources[0x23]	12710	1			T1	3		T2	2		T4	31
valid_sources[0x24]	47569	1			T1	3		T4	17		T5	3
valid_sources[0x25]	14700	1			T1	5		T2	5		T4	36
valid_sources[0x26]	11605	1			T1	1		T2	1		T4	16
valid_sources[0x27]	12060	1			T1	8		T2	2		T4	21
valid_sources[0x28]	12005	1			T4	16		T5	5		T15	1
valid_sources[0x29]	14144	1			T1	4		T2	2		T4	6
valid_sources[0x2a]	14460	1			T1	3		T4	24		T5	2
valid_sources[0x2b]	13223	1			T1	2		T2	2		T4	26
valid_sources[0x2c]	12692	1			T1	4		T2	3		T4	19
valid_sources[0x2d]	12211	1			T1	8		T4	18		T15	8
valid_sources[0x2e]	23728	1			T1	2		T4	11		T5	1
valid_sources[0x2f]	11949	1			T1	3		T4	11		T5	1
valid_sources[0x30]	11674	1			T1	1		T4	11		T15	5
valid_sources[0x31]	18702	1			T1	4		T4	11		T5	2
valid_sources[0x32]	16288	1			T1	1		T4	20		T5	1
valid_sources[0x33]	11961	1			T1	6		T4	39		T5	2
valid_sources[0x34]	12116	1			T1	1		T2	3		T4	22
valid_sources[0x35]	12283	1			T1	4		T2	4		T4	9
valid_sources[0x36]	11958	1			T1	2		T4	23		T16	4
valid_sources[0x37]	11765	1			T1	3		T2	2		T4	24
valid_sources[0x38]	11666	1			T1	4		T2	2		T4	18
valid_sources[0x39]	26591	1			T1	1		T2	5		T4	36
valid_sources[0x3a]	15556	1			T1	5		T4	25		T15	9
valid_sources[0x3b]	18266	1			T1	1		T2	1		T4	15
valid_sources[0x3c]	27173	1			T1	3		T2	3		T4	43
valid_sources[0x3d]	14667	1			T1	5		T2	2		T4	17
valid_sources[0x3e]	12496	1			T1	8		T2	2		T4	13
valid_sources[0x3f]	13832	1			T2	4		T4	12		T5	4
valid_sources[0x40]	20248	1			T1	6		T4	23		T5	3
valid_sources[0x41]	14341	1			T1	7		T4	17		T15	6
valid_sources[0x42]	12229	1			T1	1		T2	6		T3	6
valid_sources[0x43]	29719	1			T1	1		T4	21		T15	2
valid_sources[0x44]	14803	1			T1	6		T2	1		T4	17
valid_sources[0x45]	16505	1			T1	8		T4	11		T5	2
valid_sources[0x46]	15992	1			T1	3		T2	12		T4	22
valid_sources[0x47]	17979	1			T1	3		T2	9		T4	11
valid_sources[0x48]	18074	1			T4	31		T5	3		T15	6
valid_sources[0x49]	17032	1			T1	3		T4	13		T5	1
valid_sources[0x4a]	12534	1			T1	6		T2	3		T4	12
valid_sources[0x4b]	12221	1			T1	4		T2	3		T4	20
valid_sources[0x4c]	19558	1			T1	4		T2	7		T4	21
valid_sources[0x4d]	19364	1			T1	2		T4	16		T5	1
valid_sources[0x4e]	12138	1			T1	4		T2	2		T4	6
valid_sources[0x4f]	14282	1			T1	5		T2	3		T4	13
valid_sources[0x50]	14342	1			T1	4		T2	1		T4	19
valid_sources[0x51]	17031	1			T1	1		T3	4		T4	16
valid_sources[0x52]	13996	1			T4	15		T15	3		T16	2
valid_sources[0x53]	38551	1			T1	5		T2	5		T4	27
valid_sources[0x54]	39951	1			T1	3		T2	1		T4	29
valid_sources[0x55]	30710	1			T1	1		T4	18		T15	5
valid_sources[0x56]	14789	1			T1	1		T2	1		T4	16
valid_sources[0x57]	14160	1			T1	3		T4	20		T5	2
valid_sources[0x58]	42346	1			T1	1		T2	1		T3	5
valid_sources[0x59]	21022	1			T1	4		T2	7		T4	33
valid_sources[0x5a]	13581	1			T1	4		T2	2		T4	4
valid_sources[0x5b]	14635	1			T1	2		T2	4		T4	10
valid_sources[0x5c]	12056	1			T1	6		T4	8		T5	2
valid_sources[0x5d]	12717	1			T4	11		T5	1		T27	11
valid_sources[0x5e]	13556	1			T1	3		T4	25		T5	4
valid_sources[0x5f]	13676	1			T1	1		T2	2		T4	23
valid_sources[0x60]	11889	1			T1	3		T2	3		T4	28
valid_sources[0x61]	12220	1			T1	2		T4	16		T15	2
valid_sources[0x62]	12777	1			T1	2		T4	14		T5	2
valid_sources[0x63]	11934	1			T1	7		T4	18		T5	2
valid_sources[0x64]	12201	1			T2	5		T4	19		T5	1
valid_sources[0x65]	15444	1			T1	5		T2	2		T4	19
valid_sources[0x66]	16882	1			T2	3		T4	19		T5	1
valid_sources[0x67]	11365	1			T1	5		T2	7		T4	40
valid_sources[0x68]	11746	1			T1	1		T2	2		T4	15
valid_sources[0x69]	11701	1			T1	1		T2	5		T4	12
valid_sources[0x6a]	12012	1			T1	4		T2	1		T4	29
valid_sources[0x6b]	12773	1			T1	4		T4	29		T5	1
valid_sources[0x6c]	12173	1			T1	4		T2	4		T3	15
valid_sources[0x6d]	20450	1			T1	10		T2	1		T4	31
valid_sources[0x6e]	20157	1			T1	2		T4	15		T5	1
valid_sources[0x6f]	12600	1			T1	1		T2	11		T4	16
valid_sources[0x70]	38968	1			T1	5		T4	27		T5	2
valid_sources[0x71]	13297	1			T1	3		T2	2		T4	22
valid_sources[0x72]	16992	1			T1	2		T4	25		T15	5
valid_sources[0x73]	15472	1			T1	3		T2	4		T4	10
valid_sources[0x74]	12023	1			T1	4		T4	15		T15	3
valid_sources[0x75]	12390	1			T1	2		T4	11		T5	1
valid_sources[0x76]	12801	1			T1	2		T2	2		T4	11
valid_sources[0x77]	12806	1			T1	1		T2	5		T4	20
valid_sources[0x78]	13781	1			T1	6		T2	3		T4	4
valid_sources[0x79]	11747	1			T1	2		T2	4		T4	11
valid_sources[0x7a]	13291	1			T1	3		T2	2		T4	24
valid_sources[0x7b]	16008	1			T1	1		T2	1		T4	18
valid_sources[0x7c]	14101	1			T1	1		T2	1		T4	17
valid_sources[0x7d]	12795	1			T1	5		T4	3		T5	2
valid_sources[0x7e]	18786	1			T1	1		T4	12		T15	5
valid_sources[0x7f]	11671	1			T1	4		T2	2		T4	22
valid_sources[0x80]	15790	1			T1	5		T2	2		T4	21

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

302314

1

T1

110

T2

131

T3

1

values[0x0]

all_enables

biggest_size

138108

1

T1

14

T2

24

T3

8

values[0x1]

all_enables

biggest_size

124405

1

T1

7

T2

17

T4

9