Module Definition
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Module : keymgr_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.keymgr_csr_assert 100.00 100.00


Module Instance : tb.dut.keymgr_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.09 96.20 98.36 99.96 95.92 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : keymgr_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 32 32 100.00 32 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 32 32 100.00 32 100.00



Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
TlulOOBAddrErr_A 25766223 12640 0 0
attest_sw_binding_0_rd_A 25766223 955 0 0
attest_sw_binding_1_rd_A 25766223 964 0 0
attest_sw_binding_2_rd_A 25766223 968 0 0
attest_sw_binding_3_rd_A 25766223 996 0 0
attest_sw_binding_4_rd_A 25766223 1090 0 0
attest_sw_binding_5_rd_A 25766223 910 0 0
attest_sw_binding_6_rd_A 25766223 951 0 0
attest_sw_binding_7_rd_A 25766223 1005 0 0
intr_enable_rd_A 25766223 1766 0 0
key_version_rd_A 25766223 913 0 0
max_creator_key_ver_regwen_rd_A 25766223 950 0 0
max_owner_int_key_ver_regwen_rd_A 25766223 986 0 0
max_owner_key_ver_regwen_rd_A 25766223 936 0 0
reseed_interval_regwen_rd_A 25766223 1097 0 0
salt_0_rd_A 25766223 881 0 0
salt_1_rd_A 25766223 1022 0 0
salt_2_rd_A 25766223 906 0 0
salt_3_rd_A 25766223 1002 0 0
salt_4_rd_A 25766223 1044 0 0
salt_5_rd_A 25766223 980 0 0
salt_6_rd_A 25766223 917 0 0
salt_7_rd_A 25766223 1016 0 0
sealing_sw_binding_0_rd_A 25766223 948 0 0
sealing_sw_binding_1_rd_A 25766223 952 0 0
sealing_sw_binding_2_rd_A 25766223 979 0 0
sealing_sw_binding_3_rd_A 25766223 906 0 0
sealing_sw_binding_4_rd_A 25766223 988 0 0
sealing_sw_binding_5_rd_A 25766223 953 0 0
sealing_sw_binding_6_rd_A 25766223 931 0 0
sealing_sw_binding_7_rd_A 25766223 975 0 0
sideload_clear_rd_A 25766223 1000 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25766223 12640 0 0
T6 19029 0 0 0
T30 4663 0 0 0
T53 5909 0 0 0
T109 5969 4 0 0
T110 9828 717 0 0
T119 7379 7 0 0
T128 0 27 0 0
T129 0 268 0 0
T130 0 42 0 0
T131 0 1 0 0
T132 0 60 0 0
T135 4874 0 0 0
T136 228606 0 0 0
T137 3325 0 0 0
T138 204677 0 0 0
T153 0 1 0 0
T184 0 5 0 0

attest_sw_binding_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25766223 955 0 0
T122 0 76 0 0
T128 17419 27 0 0
T129 0 6 0 0
T144 175261 0 0 0
T146 0 15 0 0
T150 0 17 0 0
T159 10815 0 0 0
T170 0 15 0 0
T185 0 26 0 0
T186 0 11 0 0
T187 0 31 0 0
T188 0 16 0 0
T189 4459 0 0 0
T190 18575 0 0 0
T191 6433 0 0 0
T192 51040 0 0 0
T193 6924 0 0 0
T194 1516 0 0 0
T195 137164 0 0 0

attest_sw_binding_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25766223 964 0 0
T122 0 57 0 0
T128 17419 45 0 0
T129 0 6 0 0
T144 175261 0 0 0
T146 0 10 0 0
T150 0 35 0 0
T153 0 3 0 0
T159 10815 0 0 0
T167 0 3 0 0
T170 0 10 0 0
T185 0 37 0 0
T189 4459 0 0 0
T190 18575 0 0 0
T191 6433 0 0 0
T192 51040 0 0 0
T193 6924 0 0 0
T194 1516 0 0 0
T195 137164 0 0 0
T196 0 5 0 0

attest_sw_binding_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25766223 968 0 0
T122 0 70 0 0
T128 17419 33 0 0
T129 0 2 0 0
T144 175261 0 0 0
T146 0 12 0 0
T150 0 31 0 0
T159 10815 0 0 0
T167 0 6 0 0
T170 0 12 0 0
T185 0 18 0 0
T186 0 10 0 0
T189 4459 0 0 0
T190 18575 0 0 0
T191 6433 0 0 0
T192 51040 0 0 0
T193 6924 0 0 0
T194 1516 0 0 0
T195 137164 0 0 0
T196 0 6 0 0

attest_sw_binding_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25766223 996 0 0
T122 0 57 0 0
T128 17419 62 0 0
T129 0 13 0 0
T144 175261 0 0 0
T146 0 6 0 0
T150 0 30 0 0
T159 10815 0 0 0
T167 0 7 0 0
T170 0 3 0 0
T185 0 34 0 0
T186 0 13 0 0
T189 4459 0 0 0
T190 18575 0 0 0
T191 6433 0 0 0
T192 51040 0 0 0
T193 6924 0 0 0
T194 1516 0 0 0
T195 137164 0 0 0
T196 0 3 0 0

attest_sw_binding_4_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25766223 1090 0 0
T122 0 52 0 0
T128 17419 71 0 0
T144 175261 0 0 0
T146 0 5 0 0
T150 0 55 0 0
T159 10815 0 0 0
T167 0 5 0 0
T185 0 36 0 0
T186 0 14 0 0
T187 0 30 0 0
T188 0 16 0 0
T189 4459 0 0 0
T190 18575 0 0 0
T191 6433 0 0 0
T192 51040 0 0 0
T193 6924 0 0 0
T194 1516 0 0 0
T195 137164 0 0 0
T196 0 9 0 0

attest_sw_binding_5_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25766223 910 0 0
T122 0 71 0 0
T128 17419 68 0 0
T129 0 1 0 0
T144 175261 0 0 0
T146 0 16 0 0
T150 0 29 0 0
T159 10815 0 0 0
T170 0 9 0 0
T185 0 15 0 0
T186 0 11 0 0
T187 0 26 0 0
T189 4459 0 0 0
T190 18575 0 0 0
T191 6433 0 0 0
T192 51040 0 0 0
T193 6924 0 0 0
T194 1516 0 0 0
T195 137164 0 0 0
T196 0 10 0 0

attest_sw_binding_6_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25766223 951 0 0
T122 0 63 0 0
T128 17419 55 0 0
T129 0 9 0 0
T144 175261 0 0 0
T146 0 8 0 0
T150 0 28 0 0
T153 0 3 0 0
T159 10815 0 0 0
T167 0 14 0 0
T170 0 3 0 0
T185 0 29 0 0
T187 0 61 0 0
T189 4459 0 0 0
T190 18575 0 0 0
T191 6433 0 0 0
T192 51040 0 0 0
T193 6924 0 0 0
T194 1516 0 0 0
T195 137164 0 0 0

attest_sw_binding_7_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25766223 1005 0 0
T122 0 45 0 0
T128 17419 76 0 0
T144 175261 0 0 0
T146 0 4 0 0
T150 0 44 0 0
T153 0 4 0 0
T159 10815 0 0 0
T167 0 2 0 0
T170 0 1 0 0
T185 0 25 0 0
T186 0 8 0 0
T189 4459 0 0 0
T190 18575 0 0 0
T191 6433 0 0 0
T192 51040 0 0 0
T193 6924 0 0 0
T194 1516 0 0 0
T195 137164 0 0 0
T196 0 6 0 0

intr_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25766223 1766 0 0
T122 0 63 0 0
T128 17419 80 0 0
T144 175261 0 0 0
T146 0 8 0 0
T151 0 11 0 0
T153 0 10 0 0
T159 10815 0 0 0
T189 4459 0 0 0
T190 18575 0 0 0
T191 6433 0 0 0
T192 51040 0 0 0
T193 6924 0 0 0
T194 1516 0 0 0
T195 137164 0 0 0
T197 0 8 0 0
T198 0 22 0 0
T199 0 12 0 0
T200 0 20 0 0
T201 0 13 0 0

key_version_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25766223 913 0 0
T122 0 59 0 0
T128 17419 43 0 0
T129 0 2 0 0
T144 175261 0 0 0
T146 0 4 0 0
T150 0 38 0 0
T153 0 4 0 0
T159 10815 0 0 0
T167 0 5 0 0
T170 0 10 0 0
T185 0 39 0 0
T189 4459 0 0 0
T190 18575 0 0 0
T191 6433 0 0 0
T192 51040 0 0 0
T193 6924 0 0 0
T194 1516 0 0 0
T195 137164 0 0 0
T196 0 6 0 0

max_creator_key_ver_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25766223 950 0 0
T122 0 73 0 0
T128 17419 52 0 0
T144 175261 0 0 0
T146 0 14 0 0
T150 0 34 0 0
T153 0 5 0 0
T159 10815 0 0 0
T167 0 2 0 0
T185 0 33 0 0
T186 0 3 0 0
T187 0 36 0 0
T189 4459 0 0 0
T190 18575 0 0 0
T191 6433 0 0 0
T192 51040 0 0 0
T193 6924 0 0 0
T194 1516 0 0 0
T195 137164 0 0 0
T196 0 8 0 0

max_owner_int_key_ver_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25766223 986 0 0
T122 0 66 0 0
T128 17419 63 0 0
T129 0 3 0 0
T144 175261 0 0 0
T146 0 4 0 0
T150 0 41 0 0
T159 10815 0 0 0
T167 0 5 0 0
T170 0 3 0 0
T185 0 27 0 0
T186 0 12 0 0
T189 4459 0 0 0
T190 18575 0 0 0
T191 6433 0 0 0
T192 51040 0 0 0
T193 6924 0 0 0
T194 1516 0 0 0
T195 137164 0 0 0
T196 0 2 0 0

max_owner_key_ver_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25766223 936 0 0
T122 0 61 0 0
T128 17419 50 0 0
T144 175261 0 0 0
T146 0 8 0 0
T150 0 23 0 0
T159 10815 0 0 0
T167 0 9 0 0
T170 0 2 0 0
T185 0 12 0 0
T186 0 2 0 0
T187 0 29 0 0
T189 4459 0 0 0
T190 18575 0 0 0
T191 6433 0 0 0
T192 51040 0 0 0
T193 6924 0 0 0
T194 1516 0 0 0
T195 137164 0 0 0
T196 0 12 0 0

reseed_interval_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25766223 1097 0 0
T122 0 51 0 0
T128 17419 51 0 0
T129 0 6 0 0
T144 175261 0 0 0
T146 0 1 0 0
T150 0 55 0 0
T159 10815 0 0 0
T167 0 10 0 0
T170 0 21 0 0
T185 0 32 0 0
T186 0 3 0 0
T189 4459 0 0 0
T190 18575 0 0 0
T191 6433 0 0 0
T192 51040 0 0 0
T193 6924 0 0 0
T194 1516 0 0 0
T195 137164 0 0 0
T196 0 2 0 0

salt_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25766223 881 0 0
T122 0 55 0 0
T128 17419 29 0 0
T129 0 5 0 0
T144 175261 0 0 0
T146 0 8 0 0
T150 0 37 0 0
T159 10815 0 0 0
T170 0 11 0 0
T185 0 38 0 0
T186 0 10 0 0
T187 0 50 0 0
T189 4459 0 0 0
T190 18575 0 0 0
T191 6433 0 0 0
T192 51040 0 0 0
T193 6924 0 0 0
T194 1516 0 0 0
T195 137164 0 0 0
T196 0 2 0 0

salt_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25766223 1022 0 0
T122 0 52 0 0
T128 17419 35 0 0
T129 0 7 0 0
T144 175261 0 0 0
T146 0 5 0 0
T150 0 28 0 0
T153 0 5 0 0
T159 10815 0 0 0
T167 0 3 0 0
T170 0 20 0 0
T185 0 43 0 0
T189 4459 0 0 0
T190 18575 0 0 0
T191 6433 0 0 0
T192 51040 0 0 0
T193 6924 0 0 0
T194 1516 0 0 0
T195 137164 0 0 0
T196 0 9 0 0

salt_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25766223 906 0 0
T122 0 64 0 0
T128 17419 67 0 0
T144 175261 0 0 0
T146 0 8 0 0
T150 0 43 0 0
T159 10815 0 0 0
T170 0 9 0 0
T185 0 21 0 0
T186 0 8 0 0
T187 0 20 0 0
T188 0 6 0 0
T189 4459 0 0 0
T190 18575 0 0 0
T191 6433 0 0 0
T192 51040 0 0 0
T193 6924 0 0 0
T194 1516 0 0 0
T195 137164 0 0 0
T196 0 1 0 0

salt_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25766223 1002 0 0
T122 0 64 0 0
T128 17419 48 0 0
T129 0 6 0 0
T144 175261 0 0 0
T146 0 6 0 0
T150 0 29 0 0
T153 0 1 0 0
T159 10815 0 0 0
T170 0 20 0 0
T185 0 31 0 0
T186 0 14 0 0
T187 0 39 0 0
T189 4459 0 0 0
T190 18575 0 0 0
T191 6433 0 0 0
T192 51040 0 0 0
T193 6924 0 0 0
T194 1516 0 0 0
T195 137164 0 0 0

salt_4_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25766223 1044 0 0
T122 0 70 0 0
T128 17419 55 0 0
T129 0 11 0 0
T144 175261 0 0 0
T146 0 11 0 0
T150 0 51 0 0
T153 0 7 0 0
T159 10815 0 0 0
T170 0 9 0 0
T185 0 26 0 0
T186 0 4 0 0
T189 4459 0 0 0
T190 18575 0 0 0
T191 6433 0 0 0
T192 51040 0 0 0
T193 6924 0 0 0
T194 1516 0 0 0
T195 137164 0 0 0
T196 0 4 0 0

salt_5_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25766223 980 0 0
T122 0 48 0 0
T128 17419 61 0 0
T144 175261 0 0 0
T146 0 13 0 0
T150 0 50 0 0
T153 0 2 0 0
T159 10815 0 0 0
T170 0 3 0 0
T185 0 33 0 0
T186 0 8 0 0
T187 0 21 0 0
T189 4459 0 0 0
T190 18575 0 0 0
T191 6433 0 0 0
T192 51040 0 0 0
T193 6924 0 0 0
T194 1516 0 0 0
T195 137164 0 0 0
T196 0 11 0 0

salt_6_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25766223 917 0 0
T122 0 90 0 0
T128 17419 85 0 0
T129 0 10 0 0
T144 175261 0 0 0
T146 0 4 0 0
T150 0 34 0 0
T153 0 6 0 0
T159 10815 0 0 0
T170 0 13 0 0
T185 0 36 0 0
T186 0 6 0 0
T189 4459 0 0 0
T190 18575 0 0 0
T191 6433 0 0 0
T192 51040 0 0 0
T193 6924 0 0 0
T194 1516 0 0 0
T195 137164 0 0 0
T196 0 2 0 0

salt_7_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25766223 1016 0 0
T4 69769 5 0 0
T5 6667 0 0 0
T9 4160 0 0 0
T15 12632 0 0 0
T16 2725 0 0 0
T17 2903 0 0 0
T18 5732 0 0 0
T23 20960 0 0 0
T27 11619 0 0 0
T28 15750 0 0 0
T122 0 56 0 0
T128 0 38 0 0
T129 0 1 0 0
T146 0 2 0 0
T150 0 45 0 0
T167 0 9 0 0
T170 0 1 0 0
T185 0 28 0 0
T196 0 12 0 0

sealing_sw_binding_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25766223 948 0 0
T122 0 71 0 0
T128 17419 34 0 0
T144 175261 0 0 0
T146 0 10 0 0
T150 0 39 0 0
T159 10815 0 0 0
T167 0 12 0 0
T170 0 9 0 0
T185 0 30 0 0
T186 0 15 0 0
T187 0 37 0 0
T189 4459 0 0 0
T190 18575 0 0 0
T191 6433 0 0 0
T192 51040 0 0 0
T193 6924 0 0 0
T194 1516 0 0 0
T195 137164 0 0 0
T196 0 6 0 0

sealing_sw_binding_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25766223 952 0 0
T122 0 85 0 0
T128 17419 31 0 0
T144 175261 0 0 0
T146 0 12 0 0
T150 0 20 0 0
T153 0 3 0 0
T159 10815 0 0 0
T167 0 4 0 0
T170 0 11 0 0
T185 0 17 0 0
T186 0 12 0 0
T189 4459 0 0 0
T190 18575 0 0 0
T191 6433 0 0 0
T192 51040 0 0 0
T193 6924 0 0 0
T194 1516 0 0 0
T195 137164 0 0 0
T196 0 2 0 0

sealing_sw_binding_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25766223 979 0 0
T122 0 70 0 0
T128 17419 55 0 0
T129 0 7 0 0
T144 175261 0 0 0
T146 0 9 0 0
T150 0 19 0 0
T159 10815 0 0 0
T167 0 13 0 0
T170 0 15 0 0
T185 0 30 0 0
T186 0 12 0 0
T189 4459 0 0 0
T190 18575 0 0 0
T191 6433 0 0 0
T192 51040 0 0 0
T193 6924 0 0 0
T194 1516 0 0 0
T195 137164 0 0 0
T196 0 15 0 0

sealing_sw_binding_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25766223 906 0 0
T122 0 41 0 0
T128 17419 26 0 0
T129 0 7 0 0
T144 175261 0 0 0
T146 0 13 0 0
T150 0 24 0 0
T159 10815 0 0 0
T167 0 11 0 0
T170 0 9 0 0
T185 0 32 0 0
T186 0 2 0 0
T189 4459 0 0 0
T190 18575 0 0 0
T191 6433 0 0 0
T192 51040 0 0 0
T193 6924 0 0 0
T194 1516 0 0 0
T195 137164 0 0 0
T196 0 1 0 0

sealing_sw_binding_4_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25766223 988 0 0
T122 0 62 0 0
T128 17419 57 0 0
T129 0 5 0 0
T144 175261 0 0 0
T146 0 12 0 0
T150 0 33 0 0
T159 10815 0 0 0
T167 0 8 0 0
T185 0 20 0 0
T186 0 11 0 0
T187 0 25 0 0
T189 4459 0 0 0
T190 18575 0 0 0
T191 6433 0 0 0
T192 51040 0 0 0
T193 6924 0 0 0
T194 1516 0 0 0
T195 137164 0 0 0
T196 0 1 0 0

sealing_sw_binding_5_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25766223 953 0 0
T122 0 69 0 0
T128 17419 45 0 0
T129 0 3 0 0
T144 175261 0 0 0
T146 0 6 0 0
T150 0 37 0 0
T153 0 4 0 0
T159 10815 0 0 0
T167 0 1 0 0
T170 0 13 0 0
T185 0 31 0 0
T189 4459 0 0 0
T190 18575 0 0 0
T191 6433 0 0 0
T192 51040 0 0 0
T193 6924 0 0 0
T194 1516 0 0 0
T195 137164 0 0 0
T196 0 8 0 0

sealing_sw_binding_6_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25766223 931 0 0
T122 0 66 0 0
T128 17419 43 0 0
T144 175261 0 0 0
T146 0 11 0 0
T150 0 58 0 0
T159 10815 0 0 0
T185 0 31 0 0
T186 0 9 0 0
T187 0 41 0 0
T188 0 16 0 0
T189 4459 0 0 0
T190 18575 0 0 0
T191 6433 0 0 0
T192 51040 0 0 0
T193 6924 0 0 0
T194 1516 0 0 0
T195 137164 0 0 0
T196 0 1 0 0
T202 0 7 0 0

sealing_sw_binding_7_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25766223 975 0 0
T122 0 62 0 0
T128 17419 53 0 0
T129 0 3 0 0
T144 175261 0 0 0
T146 0 3 0 0
T150 0 51 0 0
T159 10815 0 0 0
T167 0 9 0 0
T185 0 31 0 0
T186 0 8 0 0
T187 0 22 0 0
T189 4459 0 0 0
T190 18575 0 0 0
T191 6433 0 0 0
T192 51040 0 0 0
T193 6924 0 0 0
T194 1516 0 0 0
T195 137164 0 0 0
T196 0 5 0 0

sideload_clear_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25766223 1000 0 0
T122 0 65 0 0
T128 17419 58 0 0
T144 175261 0 0 0
T146 0 2 0 0
T150 0 27 0 0
T153 0 5 0 0
T159 10815 0 0 0
T170 0 10 0 0
T185 0 30 0 0
T186 0 1 0 0
T187 0 41 0 0
T189 4459 0 0 0
T190 18575 0 0 0
T191 6433 0 0 0
T192 51040 0 0 0
T193 6924 0 0 0
T194 1516 0 0 0
T195 137164 0 0 0
T196 0 3 0 0