Unified Coverage Report :: Module :: keymgr_reseed_ctrl

Module : keymgr_reseed_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.78	100.00	93.33			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_reseed_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reseed_ctrl	97.78	100.00	93.33			100.00

---

Module Instance : tb.dut.u_reseed_ctrl

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.78	100.00	93.33			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.44	100.00	92.19	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.09	96.20	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_edn_req	97.96	100.00	91.84			100.00	100.00
u_reseed_cnt	100.00			100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : keymgr_reseed_ctrl

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	42	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
ALWAYS	48	6	6	100.00
CONT_ASSIGN	58	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
ALWAYS	84	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_reseed_ctrl.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_reseed_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
45	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
54	1	1
			MISSING_ELSE
58	1	1
59	1	1
84	1	1
85	1	1
86	1	1
87	1	1
			MISSING_ELSE

---

Cond Coverage for Module : keymgr_reseed_ctrl

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (edn_req & edn_ack)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       52
 EXPRESSION (((!edn_req)) && (reseed_req_i || local_req))
             ------1-----    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       52
 SUB-EXPRESSION (reseed_req_i || local_req)
                 ------1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       59
 EXPRESSION (reseed_req_i & edn_ack)
             ------1-----   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       95
 EXPRESSION (cnt_en & lfsr_en_i)
             ---1--   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T9,T18
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

---

Branch Coverage for Module : keymgr_reseed_ctrl

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
IF	48	4	4	100.00
IF	84	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_reseed_ctrl.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_reseed_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	48	if ((!rst_ni))
-2-:	50	if (edn_done)
-3-:	52	if (((!edn_req) && (reseed_req_i || local_req)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	84	if ((!rst_ni))
-2-:	86	if (edn_done)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3