Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4121628	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

551987

1

T1

152

T2

480

T3

235

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4304761	1			T1	6780		T2	654		T3	963
values[0x0]	182806	1			T1	51		T2	177		T3	47
values[0x1]	186048	1			T1	40		T2	182		T3	61

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2798920	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1874695

1

T1

2398

T2

614

T3

469

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	59828	1			T1	23		T3	3		T16	10
valid_sources[0x01]	15403	1			T1	25		T3	8		T16	9
valid_sources[0x02]	23052	1			T1	28		T3	2		T16	7
valid_sources[0x03]	17947	1			T1	22		T2	1		T3	9
valid_sources[0x04]	14879	1			T1	31		T3	5		T16	8
valid_sources[0x05]	21384	1			T1	19		T3	13		T16	20
valid_sources[0x06]	15711	1			T1	25		T3	1		T16	10
valid_sources[0x07]	16529	1			T1	35		T16	11		T17	7
valid_sources[0x08]	16598	1			T1	30		T3	9		T16	12
valid_sources[0x09]	14031	1			T1	36		T3	6		T16	6
valid_sources[0x0a]	33139	1			T1	27		T16	13		T17	1
valid_sources[0x0b]	13639	1			T1	29		T3	1		T16	12
valid_sources[0x0c]	26324	1			T1	25		T3	1		T16	17
valid_sources[0x0d]	14019	1			T1	24		T3	9		T16	10
valid_sources[0x0e]	13677	1			T1	25		T3	6		T4	7
valid_sources[0x0f]	17574	1			T1	30		T3	2		T16	11
valid_sources[0x10]	21434	1			T1	35		T3	3		T16	6
valid_sources[0x11]	14460	1			T1	24		T3	4		T16	10
valid_sources[0x12]	16758	1			T1	19		T3	15		T16	15
valid_sources[0x13]	14581	1			T1	31		T3	5		T16	13
valid_sources[0x14]	15276	1			T1	21		T3	4		T15	10
valid_sources[0x15]	17400	1			T1	34		T3	1		T16	9
valid_sources[0x16]	15118	1			T1	23		T2	119		T3	6
valid_sources[0x17]	20816	1			T1	31		T3	1		T16	11
valid_sources[0x18]	14946	1			T1	27		T3	1		T16	8
valid_sources[0x19]	14452	1			T1	26		T3	6		T16	10
valid_sources[0x1a]	14395	1			T1	31		T3	3		T16	11
valid_sources[0x1b]	20532	1			T1	22		T3	8		T16	8
valid_sources[0x1c]	23091	1			T1	24		T3	5		T4	29
valid_sources[0x1d]	39937	1			T1	30		T3	8		T15	13660
valid_sources[0x1e]	14853	1			T1	25		T2	3		T3	4
valid_sources[0x1f]	18918	1			T1	26		T3	1		T16	4
valid_sources[0x20]	14805	1			T1	28		T3	1		T16	16
valid_sources[0x21]	27283	1			T1	25		T15	40		T16	14
valid_sources[0x22]	16684	1			T1	29		T3	18		T16	7
valid_sources[0x23]	14638	1			T1	21		T3	1		T16	13
valid_sources[0x24]	14975	1			T1	25		T3	6		T16	9
valid_sources[0x25]	15897	1			T1	25		T3	3		T4	28
valid_sources[0x26]	14157	1			T1	25		T3	5		T16	16
valid_sources[0x27]	14747	1			T1	25		T3	6		T4	76
valid_sources[0x28]	15254	1			T1	29		T3	2		T16	7
valid_sources[0x29]	53629	1			T1	27		T3	2		T15	43
valid_sources[0x2a]	16374	1			T1	27		T3	6		T16	10
valid_sources[0x2b]	17424	1			T1	35		T3	6		T16	14
valid_sources[0x2c]	20470	1			T1	14		T3	2		T16	10
valid_sources[0x2d]	13189	1			T1	29		T2	1		T3	4
valid_sources[0x2e]	13776	1			T1	21		T15	34		T16	10
valid_sources[0x2f]	15159	1			T1	23		T3	2		T16	5
valid_sources[0x30]	13161	1			T1	32		T16	10		T17	7
valid_sources[0x31]	14457	1			T1	27		T2	3		T3	7
valid_sources[0x32]	28398	1			T1	26		T3	5		T16	7
valid_sources[0x33]	15849	1			T1	23		T3	4		T16	12
valid_sources[0x34]	25652	1			T1	27		T3	7		T16	10
valid_sources[0x35]	19734	1			T1	26		T16	8		T17	2
valid_sources[0x36]	19358	1			T1	27		T3	5		T16	12
valid_sources[0x37]	13875	1			T1	25		T3	2		T16	13
valid_sources[0x38]	14436	1			T1	26		T2	32		T3	2
valid_sources[0x39]	13587	1			T1	36		T2	11		T3	3
valid_sources[0x3a]	15553	1			T1	20		T3	8		T16	14
valid_sources[0x3b]	15198	1			T1	29		T3	7		T16	12
valid_sources[0x3c]	36211	1			T1	29		T3	2		T4	39
valid_sources[0x3d]	17859	1			T1	33		T3	2		T16	11
valid_sources[0x3e]	24860	1			T1	27		T3	8		T16	12
valid_sources[0x3f]	23151	1			T1	29		T3	4		T16	8
valid_sources[0x40]	20138	1			T1	24		T3	1		T16	7
valid_sources[0x41]	17625	1			T1	35		T3	4		T16	8
valid_sources[0x42]	15907	1			T1	23		T3	6		T16	11
valid_sources[0x43]	17898	1			T1	27		T3	3		T16	8
valid_sources[0x44]	21368	1			T1	32		T2	14		T3	5
valid_sources[0x45]	16635	1			T1	23		T3	3		T16	13
valid_sources[0x46]	20865	1			T1	25		T2	1		T3	3
valid_sources[0x47]	15099	1			T1	33		T3	7		T16	17
valid_sources[0x48]	14259	1			T1	32		T3	8		T16	7
valid_sources[0x49]	15997	1			T1	35		T3	7		T16	7
valid_sources[0x4a]	15006	1			T1	21		T3	3		T16	8
valid_sources[0x4b]	14483	1			T1	21		T3	12		T16	13
valid_sources[0x4c]	15052	1			T1	25		T3	5		T16	11
valid_sources[0x4d]	28609	1			T1	18		T3	5		T16	9
valid_sources[0x4e]	14494	1			T1	30		T3	3		T16	14
valid_sources[0x4f]	14564	1			T1	25		T3	7		T16	10
valid_sources[0x50]	14254	1			T1	19		T3	2		T16	9
valid_sources[0x51]	14557	1			T1	41		T3	1		T16	8
valid_sources[0x52]	17829	1			T1	22		T16	10		T17	12
valid_sources[0x53]	15930	1			T1	21		T16	10		T17	1
valid_sources[0x54]	13762	1			T1	23		T3	5		T16	9
valid_sources[0x55]	18262	1			T1	24		T3	12		T16	11
valid_sources[0x56]	25211	1			T1	22		T3	1		T16	19
valid_sources[0x57]	53611	1			T1	29		T2	1		T16	18
valid_sources[0x58]	15272	1			T1	20		T3	6		T16	9
valid_sources[0x59]	14647	1			T1	17		T3	2		T16	13
valid_sources[0x5a]	19534	1			T1	31		T3	4		T15	194
valid_sources[0x5b]	15933	1			T1	30		T3	5		T16	5
valid_sources[0x5c]	19594	1			T1	23		T2	1		T3	3
valid_sources[0x5d]	14980	1			T1	20		T3	6		T16	9
valid_sources[0x5e]	14050	1			T1	26		T3	3		T16	10
valid_sources[0x5f]	14485	1			T1	32		T16	11		T17	5
valid_sources[0x60]	18607	1			T1	27		T3	4		T15	30
valid_sources[0x61]	21355	1			T1	22		T2	51		T3	5
valid_sources[0x62]	13771	1			T1	27		T3	4		T16	8
valid_sources[0x63]	14216	1			T1	27		T3	1		T16	10
valid_sources[0x64]	13946	1			T1	28		T3	2		T16	9
valid_sources[0x65]	14524	1			T1	23		T2	1		T3	6
valid_sources[0x66]	21999	1			T1	25		T3	5		T15	41
valid_sources[0x67]	16573	1			T1	17		T3	8		T16	24
valid_sources[0x68]	14922	1			T1	22		T3	7		T4	35
valid_sources[0x69]	14217	1			T1	24		T3	6		T16	10
valid_sources[0x6a]	14805	1			T1	26		T3	3		T16	8
valid_sources[0x6b]	16320	1			T1	28		T2	91		T3	15
valid_sources[0x6c]	13870	1			T1	28		T3	7		T15	11
valid_sources[0x6d]	14084	1			T1	28		T3	5		T16	14
valid_sources[0x6e]	20453	1			T1	21		T3	3		T16	16
valid_sources[0x6f]	22779	1			T1	28		T3	1		T4	103
valid_sources[0x70]	24251	1			T1	26		T4	124		T15	49
valid_sources[0x71]	23905	1			T1	25		T2	133		T3	3
valid_sources[0x72]	14842	1			T1	30		T2	1		T3	1
valid_sources[0x73]	15756	1			T1	31		T3	10		T16	9
valid_sources[0x74]	14409	1			T1	29		T3	2		T16	13
valid_sources[0x75]	14684	1			T1	35		T3	3		T4	6
valid_sources[0x76]	17955	1			T1	21		T2	76		T3	1
valid_sources[0x77]	16955	1			T1	26		T3	3		T15	8
valid_sources[0x78]	22582	1			T1	26		T2	47		T3	3
valid_sources[0x79]	18227	1			T1	29		T3	3		T16	10
valid_sources[0x7a]	14231	1			T1	34		T16	18		T17	3
valid_sources[0x7b]	14952	1			T1	32		T2	1		T3	3
valid_sources[0x7c]	14857	1			T1	24		T3	3		T16	7
valid_sources[0x7d]	28340	1			T1	25		T2	27		T3	8
valid_sources[0x7e]	26337	1			T1	20		T3	5		T15	7593
valid_sources[0x7f]	13536	1			T1	27		T3	5		T16	9
valid_sources[0x80]	14343	1			T1	31		T3	4		T16	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

300210

1

T1

119

T2

235

T3

201

values[0x0]

all_enables

biggest_size

132475

1

T1

21

T2

122

T3

19

values[0x1]

all_enables

biggest_size

119302

1

T1

12

T2

123

T3

15