Unified Coverage Report :: Module :: keymgr_reg_top

Module : keymgr_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.74	100.00	98.96			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg	99.74	100.00	98.96			100.00	100.00

---

Module Instance : tb.dut.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.74	100.00	98.96			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.47	98.86	98.91	100.00		99.61	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.09	96.20	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test_fatal_fault_err	100.00	100.00
u_alert_test_recov_operation_err	100.00	100.00
u_attest_sw_binding_0	100.00	100.00	100.00			100.00
u_attest_sw_binding_1	100.00	100.00	100.00			100.00
u_attest_sw_binding_2	100.00	100.00	100.00			100.00
u_attest_sw_binding_3	100.00	100.00	100.00			100.00
u_attest_sw_binding_4	100.00	100.00	100.00			100.00
u_attest_sw_binding_5	100.00	100.00	100.00			100.00
u_attest_sw_binding_6	100.00	100.00	100.00			100.00
u_attest_sw_binding_7	100.00	100.00	100.00			100.00
u_cfg_regwen	100.00	100.00
u_chk	100.00	100.00		100.00			100.00
u_control_shadowed_cdi_sel	99.55	100.00	98.21			100.00	100.00
u_control_shadowed_dest_sel	99.55	100.00	98.21			100.00	100.00
u_control_shadowed_operation	99.55	100.00	98.21			100.00	100.00
u_debug_invalid_creator_seed	100.00	100.00	100.00			100.00
u_debug_invalid_dev_id	100.00	100.00	100.00			100.00
u_debug_invalid_digest	100.00	100.00	100.00			100.00
u_debug_invalid_health_state	100.00	100.00	100.00			100.00
u_debug_invalid_key	100.00	100.00	100.00			100.00
u_debug_invalid_key_version	100.00	100.00	100.00			100.00
u_debug_invalid_owner_seed	100.00	100.00	100.00			100.00
u_err_code_invalid_kmac_input	100.00	100.00	100.00			100.00
u_err_code_invalid_op	100.00	100.00	100.00			100.00
u_err_code_invalid_shadow_update	97.22	100.00	91.67			100.00
u_fault_status_cmd	96.67	90.00	100.00			100.00
u_fault_status_ctrl_fsm_chk	96.67	90.00	100.00			100.00
u_fault_status_ctrl_fsm_cnt	96.67	90.00	100.00			100.00
u_fault_status_ctrl_fsm_intg	96.67	90.00	100.00			100.00
u_fault_status_key_ecc	96.67	90.00	100.00			100.00
u_fault_status_kmac_done	96.67	90.00	100.00			100.00
u_fault_status_kmac_fsm	96.67	90.00	100.00			100.00
u_fault_status_kmac_op	96.67	90.00	100.00			100.00
u_fault_status_kmac_out	73.33	90.00	50.00			80.00
u_fault_status_regfile_intg	96.67	90.00	100.00			100.00
u_fault_status_reseed_cnt	96.67	90.00	100.00			100.00
u_fault_status_shadow	96.67	90.00	100.00			100.00
u_fault_status_side_ctrl_fsm	96.67	90.00	100.00			100.00
u_fault_status_side_ctrl_sel	96.67	90.00	100.00			100.00
u_intr_enable	100.00	100.00	100.00			100.00
u_intr_state	100.00	100.00	100.00			100.00
u_intr_test	100.00	100.00
u_key_version	100.00	100.00	100.00			100.00
u_max_creator_key_ver_regwen	100.00	100.00	100.00			100.00
u_max_creator_key_ver_shadowed	99.55	100.00	98.21			100.00	100.00
u_max_owner_int_key_ver_regwen	100.00	100.00	100.00			100.00
u_max_owner_int_key_ver_shadowed	99.55	100.00	98.21			100.00	100.00
u_max_owner_key_ver_regwen	100.00	100.00	100.00			100.00
u_max_owner_key_ver_shadowed	99.55	100.00	98.21			100.00	100.00
u_op_status	100.00	100.00	100.00			100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	98.69	97.14	97.62			100.00	100.00
u_reseed_interval_regwen	100.00	100.00	100.00			100.00
u_reseed_interval_shadowed	99.55	100.00	98.21			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_salt_0	100.00	100.00	100.00			100.00
u_salt_1	100.00	100.00	100.00			100.00
u_salt_2	100.00	100.00	100.00			100.00
u_salt_3	100.00	100.00	100.00			100.00
u_salt_4	100.00	100.00	100.00			100.00
u_salt_5	100.00	100.00	100.00			100.00
u_salt_6	100.00	100.00	100.00			100.00
u_salt_7	100.00	100.00	100.00			100.00
u_sealing_sw_binding_0	100.00	100.00	100.00			100.00
u_sealing_sw_binding_1	100.00	100.00	100.00			100.00
u_sealing_sw_binding_2	100.00	100.00	100.00			100.00
u_sealing_sw_binding_3	100.00	100.00	100.00			100.00
u_sealing_sw_binding_4	100.00	100.00	100.00			100.00
u_sealing_sw_binding_5	100.00	100.00	100.00			100.00
u_sealing_sw_binding_6	100.00	100.00	100.00			100.00
u_sealing_sw_binding_7	100.00	100.00	100.00			100.00
u_sideload_clear	100.00	100.00	100.00			100.00
u_start	100.00	100.00	100.00			100.00
u_sw_binding_regwen	100.00	100.00
u_sw_share0_output_0	100.00	100.00	100.00			100.00
u_sw_share0_output_1	100.00	100.00	100.00			100.00
u_sw_share0_output_2	100.00	100.00	100.00			100.00
u_sw_share0_output_3	100.00	100.00	100.00			100.00
u_sw_share0_output_4	100.00	100.00	100.00			100.00
u_sw_share0_output_5	100.00	100.00	100.00			100.00
u_sw_share0_output_6	100.00	100.00	100.00			100.00
u_sw_share0_output_7	100.00	100.00	100.00			100.00
u_sw_share1_output_0	100.00	100.00	100.00			100.00
u_sw_share1_output_1	100.00	100.00	100.00			100.00
u_sw_share1_output_2	100.00	100.00	100.00			100.00
u_sw_share1_output_3	100.00	100.00	100.00			100.00
u_sw_share1_output_4	100.00	100.00	100.00			100.00
u_sw_share1_output_5	100.00	100.00	100.00			100.00
u_sw_share1_output_6	100.00	100.00	100.00			100.00
u_sw_share1_output_7	100.00	100.00	100.00			100.00
u_working_state	63.33	80.00	50.00			60.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : keymgr_reg_top

	Line No.	Total	Covered	Percent
TOTAL		401	401	100.00
ALWAYS	75	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	97	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	442	1	1	100.00
CONT_ASSIGN	448	1	1	100.00
CONT_ASSIGN	463	1	1	100.00
CONT_ASSIGN	479	1	1	100.00
CONT_ASSIGN	501	1	1	100.00
CONT_ASSIGN	532	1	1	100.00
CONT_ASSIGN	645	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	745	1	1	100.00
CONT_ASSIGN	759	1	1	100.00
CONT_ASSIGN	766	1	1	100.00
CONT_ASSIGN	798	1	1	100.00
CONT_ASSIGN	830	1	1	100.00
CONT_ASSIGN	862	1	1	100.00
CONT_ASSIGN	894	1	1	100.00
CONT_ASSIGN	926	1	1	100.00
CONT_ASSIGN	958	1	1	100.00
CONT_ASSIGN	990	1	1	100.00
CONT_ASSIGN	1022	1	1	100.00
CONT_ASSIGN	1054	1	1	100.00
CONT_ASSIGN	1086	1	1	100.00
CONT_ASSIGN	1118	1	1	100.00
CONT_ASSIGN	1150	1	1	100.00
CONT_ASSIGN	1182	1	1	100.00
CONT_ASSIGN	1214	1	1	100.00
CONT_ASSIGN	1246	1	1	100.00
CONT_ASSIGN	1278	1	1	100.00
CONT_ASSIGN	1310	1	1	100.00
CONT_ASSIGN	1342	1	1	100.00
CONT_ASSIGN	1374	1	1	100.00
CONT_ASSIGN	1406	1	1	100.00
CONT_ASSIGN	1438	1	1	100.00
CONT_ASSIGN	1470	1	1	100.00
CONT_ASSIGN	1502	1	1	100.00
CONT_ASSIGN	1534	1	1	100.00
CONT_ASSIGN	1593	1	1	100.00
CONT_ASSIGN	1662	1	1	100.00
CONT_ASSIGN	1731	1	1	100.00
ALWAYS	2946	64	64	100.00
CONT_ASSIGN	3012	1	1	100.00
ALWAYS	3016	1	1	100.00
CONT_ASSIGN	3083	1	1	100.00
CONT_ASSIGN	3085	1	1	100.00
CONT_ASSIGN	3086	1	1	100.00
CONT_ASSIGN	3088	1	1	100.00
CONT_ASSIGN	3089	1	1	100.00
CONT_ASSIGN	3091	1	1	100.00
CONT_ASSIGN	3092	1	1	100.00
CONT_ASSIGN	3094	1	1	100.00
CONT_ASSIGN	3096	1	1	100.00
CONT_ASSIGN	3097	1	1	100.00
CONT_ASSIGN	3098	1	1	100.00
CONT_ASSIGN	3100	1	1	100.00
CONT_ASSIGN	3101	1	1	100.00
CONT_ASSIGN	3102	1	1	100.00
CONT_ASSIGN	3104	1	1	100.00
CONT_ASSIGN	3106	1	1	100.00
CONT_ASSIGN	3108	1	1	100.00
CONT_ASSIGN	3109	1	1	100.00
CONT_ASSIGN	3111	1	1	100.00
CONT_ASSIGN	3112	1	1	100.00
CONT_ASSIGN	3114	1	1	100.00
CONT_ASSIGN	3115	1	1	100.00
CONT_ASSIGN	3116	1	1	100.00
CONT_ASSIGN	3118	1	1	100.00
CONT_ASSIGN	3119	1	1	100.00
CONT_ASSIGN	3120	1	1	100.00
CONT_ASSIGN	3122	1	1	100.00
CONT_ASSIGN	3123	1	1	100.00
CONT_ASSIGN	3125	1	1	100.00
CONT_ASSIGN	3126	1	1	100.00
CONT_ASSIGN	3128	1	1	100.00
CONT_ASSIGN	3129	1	1	100.00
CONT_ASSIGN	3131	1	1	100.00
CONT_ASSIGN	3132	1	1	100.00
CONT_ASSIGN	3134	1	1	100.00
CONT_ASSIGN	3135	1	1	100.00
CONT_ASSIGN	3137	1	1	100.00
CONT_ASSIGN	3138	1	1	100.00
CONT_ASSIGN	3140	1	1	100.00
CONT_ASSIGN	3141	1	1	100.00
CONT_ASSIGN	3143	1	1	100.00
CONT_ASSIGN	3144	1	1	100.00
CONT_ASSIGN	3146	1	1	100.00
CONT_ASSIGN	3147	1	1	100.00
CONT_ASSIGN	3149	1	1	100.00
CONT_ASSIGN	3150	1	1	100.00
CONT_ASSIGN	3152	1	1	100.00
CONT_ASSIGN	3153	1	1	100.00
CONT_ASSIGN	3155	1	1	100.00
CONT_ASSIGN	3156	1	1	100.00
CONT_ASSIGN	3158	1	1	100.00
CONT_ASSIGN	3159	1	1	100.00
CONT_ASSIGN	3161	1	1	100.00
CONT_ASSIGN	3162	1	1	100.00
CONT_ASSIGN	3164	1	1	100.00
CONT_ASSIGN	3165	1	1	100.00
CONT_ASSIGN	3167	1	1	100.00
CONT_ASSIGN	3168	1	1	100.00
CONT_ASSIGN	3170	1	1	100.00
CONT_ASSIGN	3171	1	1	100.00
CONT_ASSIGN	3173	1	1	100.00
CONT_ASSIGN	3174	1	1	100.00
CONT_ASSIGN	3176	1	1	100.00
CONT_ASSIGN	3177	1	1	100.00
CONT_ASSIGN	3179	1	1	100.00
CONT_ASSIGN	3180	1	1	100.00
CONT_ASSIGN	3182	1	1	100.00
CONT_ASSIGN	3183	1	1	100.00
CONT_ASSIGN	3185	1	1	100.00
CONT_ASSIGN	3186	1	1	100.00
CONT_ASSIGN	3188	1	1	100.00
CONT_ASSIGN	3189	1	1	100.00
CONT_ASSIGN	3191	1	1	100.00
CONT_ASSIGN	3192	1	1	100.00
CONT_ASSIGN	3194	1	1	100.00
CONT_ASSIGN	3195	1	1	100.00
CONT_ASSIGN	3197	1	1	100.00
CONT_ASSIGN	3198	1	1	100.00
CONT_ASSIGN	3200	1	1	100.00
CONT_ASSIGN	3201	1	1	100.00
CONT_ASSIGN	3202	1	1	100.00
CONT_ASSIGN	3204	1	1	100.00
CONT_ASSIGN	3205	1	1	100.00
CONT_ASSIGN	3207	1	1	100.00
CONT_ASSIGN	3208	1	1	100.00
CONT_ASSIGN	3209	1	1	100.00
CONT_ASSIGN	3211	1	1	100.00
CONT_ASSIGN	3212	1	1	100.00
CONT_ASSIGN	3214	1	1	100.00
CONT_ASSIGN	3215	1	1	100.00
CONT_ASSIGN	3216	1	1	100.00
CONT_ASSIGN	3218	1	1	100.00
CONT_ASSIGN	3219	1	1	100.00
CONT_ASSIGN	3222	1	1	100.00
CONT_ASSIGN	3225	1	1	100.00
CONT_ASSIGN	3228	1	1	100.00
CONT_ASSIGN	3231	1	1	100.00
CONT_ASSIGN	3234	1	1	100.00
CONT_ASSIGN	3237	1	1	100.00
CONT_ASSIGN	3240	1	1	100.00
CONT_ASSIGN	3243	1	1	100.00
CONT_ASSIGN	3246	1	1	100.00
CONT_ASSIGN	3249	1	1	100.00
CONT_ASSIGN	3252	1	1	100.00
CONT_ASSIGN	3255	1	1	100.00
CONT_ASSIGN	3258	1	1	100.00
CONT_ASSIGN	3261	1	1	100.00
CONT_ASSIGN	3264	1	1	100.00
CONT_ASSIGN	3267	1	1	100.00
CONT_ASSIGN	3269	1	1	100.00
CONT_ASSIGN	3270	1	1	100.00
CONT_ASSIGN	3272	1	1	100.00
CONT_ASSIGN	3274	1	1	100.00
CONT_ASSIGN	3276	1	1	100.00
CONT_ASSIGN	3277	1	1	100.00
CONT_ASSIGN	3279	1	1	100.00
CONT_ASSIGN	3281	1	1	100.00
CONT_ASSIGN	3283	1	1	100.00
CONT_ASSIGN	3285	1	1	100.00
CONT_ASSIGN	3287	1	1	100.00
CONT_ASSIGN	3289	1	1	100.00
CONT_ASSIGN	3291	1	1	100.00
ALWAYS	3295	64	64	100.00
ALWAYS	3363	89	89	100.00
ALWAYS	3652	3	3	100.00
ALWAYS	3660	3	3	100.00
CONT_ASSIGN	3668	1	1	100.00
CONT_ASSIGN	3671	1	1	100.00
CONT_ASSIGN	3680	1	1	100.00
CONT_ASSIGN	3691	1	1	100.00
CONT_ASSIGN	3699	1	1	100.00
CONT_ASSIGN	3700	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_reg_top.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
75	1	1
76	1	1
77	1	1
78	1	1
			MISSING_ELSE
84	1	1
96	1	1
97	1	1
125	1	1
126	1	1
428	1	1
442	1	1
448	1	1
463	1	1
479	1	1
501	1	1
532	1	1
645	1	1
704	1	1
745	1	1
759	1	1
766	1	1
798	1	1
830	1	1
862	1	1
894	1	1
926	1	1
958	1	1
990	1	1
1022	1	1
1054	1	1
1086	1	1
1118	1	1
1150	1	1
1182	1	1
1214	1	1
1246	1	1
1278	1	1
1310	1	1
1342	1	1
1374	1	1
1406	1	1
1438	1	1
1470	1	1
1502	1	1
1534	1	1
1593	1	1
1662	1	1
1731	1	1
2946	1	1
2947	1	1
2948	1	1
2949	1	1
2950	1	1
2951	1	1
2952	1	1
2953	1	1
2954	1	1
2955	1	1
2956	1	1
2957	1	1
2958	1	1
2959	1	1
2960	1	1
2961	1	1
2962	1	1
2963	1	1
2964	1	1
2965	1	1
2966	1	1
2967	1	1
2968	1	1
2969	1	1
2970	1	1
2971	1	1
2972	1	1
2973	1	1
2974	1	1
2975	1	1
2976	1	1
2977	1	1
2978	1	1
2979	1	1
2980	1	1
2981	1	1
2982	1	1
2983	1	1
2984	1	1
2985	1	1
2986	1	1
2987	1	1
2988	1	1
2989	1	1
2990	1	1
2991	1	1
2992	1	1
2993	1	1
2994	1	1
2995	1	1
2996	1	1
2997	1	1
2998	1	1
2999	1	1
3000	1	1
3001	1	1
3002	1	1
3003	1	1
3004	1	1
3005	1	1
3006	1	1
3007	1	1
3008	1	1
3009	1	1
3012	1	1
3016	1	1
3083	1	1
3085	1	1
3086	1	1
3088	1	1
3089	1	1
3091	1	1
3092	1	1
3094	1	1
3096	1	1
3097	1	1
3098	1	1
3100	1	1
3101	1	1
3102	1	1
3104	1	1
3106	1	1
3108	1	1
3109	1	1
3111	1	1
3112	1	1
3114	1	1
3115	1	1
3116	1	1
3118	1	1
3119	1	1
3120	1	1
3122	1	1
3123	1	1
3125	1	1
3126	1	1
3128	1	1
3129	1	1
3131	1	1
3132	1	1
3134	1	1
3135	1	1
3137	1	1
3138	1	1
3140	1	1
3141	1	1
3143	1	1
3144	1	1
3146	1	1
3147	1	1
3149	1	1
3150	1	1
3152	1	1
3153	1	1
3155	1	1
3156	1	1
3158	1	1
3159	1	1
3161	1	1
3162	1	1
3164	1	1
3165	1	1
3167	1	1
3168	1	1
3170	1	1
3171	1	1
3173	1	1
3174	1	1
3176	1	1
3177	1	1
3179	1	1
3180	1	1
3182	1	1
3183	1	1
3185	1	1
3186	1	1
3188	1	1
3189	1	1
3191	1	1
3192	1	1
3194	1	1
3195	1	1
3197	1	1
3198	1	1
3200	1	1
3201	1	1
3202	1	1
3204	1	1
3205	1	1
3207	1	1
3208	1	1
3209	1	1
3211	1	1
3212	1	1
3214	1	1
3215	1	1
3216	1	1
3218	1	1
3219	1	1
3222	1	1
3225	1	1
3228	1	1
3231	1	1
3234	1	1
3237	1	1
3240	1	1
3243	1	1
3246	1	1
3249	1	1
3252	1	1
3255	1	1
3258	1	1
3261	1	1
3264	1	1
3267	1	1
3269	1	1
3270	1	1
3272	1	1
3274	1	1
3276	1	1
3277	1	1
3279	1	1
3281	1	1
3283	1	1
3285	1	1
3287	1	1
3289	1	1
3291	1	1
3295	1	1
3296	1	1
3297	1	1
3298	1	1
3299	1	1
3300	1	1
3301	1	1
3302	1	1
3303	1	1
3304	1	1
3305	1	1
3306	1	1
3307	1	1
3308	1	1
3309	1	1
3310	1	1
3311	1	1
3312	1	1
3313	1	1
3314	1	1
3315	1	1
3316	1	1
3317	1	1
3318	1	1
3319	1	1
3320	1	1
3321	1	1
3322	1	1
3323	1	1
3324	1	1
3325	1	1
3326	1	1
3327	1	1
3328	1	1
3329	1	1
3330	1	1
3331	1	1
3332	1	1
3333	1	1
3334	1	1
3335	1	1
3336	1	1
3337	1	1
3338	1	1
3339	1	1
3340	1	1
3341	1	1
3342	1	1
3343	1	1
3344	1	1
3345	1	1
3346	1	1
3347	1	1
3348	1	1
3349	1	1
3350	1	1
3351	1	1
3352	1	1
3353	1	1
3354	1	1
3355	1	1
3356	1	1
3357	1	1
3358	1	1
3363	1	1
3364	1	1
3366	1	1
3370	1	1
3374	1	1
3378	1	1
3379	1	1
3383	1	1
3387	1	1
3391	1	1
3392	1	1
3393	1	1
3397	1	1
3401	1	1
3405	1	1
3409	1	1
3413	1	1
3417	1	1
3421	1	1
3425	1	1
3429	1	1
3433	1	1
3437	1	1
3441	1	1
3445	1	1
3449	1	1
3453	1	1
3457	1	1
3461	1	1
3465	1	1
3469	1	1
3473	1	1
3477	1	1
3481	1	1
3485	1	1
3489	1	1
3493	1	1
3497	1	1
3501	1	1
3505	1	1
3509	1	1
3513	1	1
3517	1	1
3521	1	1
3525	1	1
3529	1	1
3533	1	1
3537	1	1
3541	1	1
3545	1	1
3549	1	1
3553	1	1
3557	1	1
3561	1	1
3565	1	1
3569	1	1
3573	1	1
3577	1	1
3581	1	1
3585	1	1
3589	1	1
3593	1	1
3597	1	1
3601	1	1
3605	1	1
3609	1	1
3610	1	1
3611	1	1
3615	1	1
3616	1	1
3617	1	1
3618	1	1
3619	1	1
3620	1	1
3621	1	1
3622	1	1
3623	1	1
3624	1	1
3625	1	1
3626	1	1
3627	1	1
3628	1	1
3632	1	1
3633	1	1
3634	1	1
3635	1	1
3636	1	1
3637	1	1
3638	1	1
3652	1	1
3653	1	1
3655	1	1
3660	1	1
3661	1	1
3663	1	1
3668	1	1
3671	1	1
3680	1	1
3691	1	1
3699	1	1
3700	1	1

---

Cond Coverage for Module : keymgr_reg_top

	Total	Covered	Percent
Conditions	770	762	98.96
Logical	770	762	98.96
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
65-3016	100.00
3016-3668	97.73

---

Branch Coverage for Module : keymgr_reg_top

	Line No.	Total	Covered	Percent
Branches		73	73	100.00
TERNARY	3012	2	2	100.00
IF	75	3	3	100.00
CASE	3364	64	64	100.00
IF	3652	2	2	100.00
IF	3660	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_reg_top.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	3012	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	75	if ((!rst_ni))
-2-:	77	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T33,T53,T36
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	3364	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T1,T2,T3
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T3
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T3
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T1,T2,T3
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T1,T2,T3
addr_hit[14]	Covered	T1,T2,T3
addr_hit[15]	Covered	T1,T2,T3
addr_hit[16]	Covered	T1,T2,T3
addr_hit[17]	Covered	T1,T2,T3
addr_hit[18]	Covered	T1,T2,T3
addr_hit[19]	Covered	T1,T2,T3
addr_hit[20]	Covered	T1,T2,T3
addr_hit[21]	Covered	T1,T2,T3
addr_hit[22]	Covered	T1,T2,T3
addr_hit[23]	Covered	T1,T2,T3
addr_hit[24]	Covered	T1,T2,T3
addr_hit[25]	Covered	T1,T2,T3
addr_hit[26]	Covered	T1,T2,T3
addr_hit[27]	Covered	T1,T2,T3
addr_hit[28]	Covered	T1,T2,T3
addr_hit[29]	Covered	T1,T2,T3
addr_hit[30]	Covered	T1,T2,T3
addr_hit[31]	Covered	T1,T2,T3
addr_hit[32]	Covered	T1,T2,T3
addr_hit[33]	Covered	T1,T2,T3
addr_hit[34]	Covered	T1,T2,T3
addr_hit[35]	Covered	T1,T2,T3
addr_hit[36]	Covered	T1,T2,T3
addr_hit[37]	Covered	T1,T2,T3
addr_hit[38]	Covered	T1,T2,T3
addr_hit[39]	Covered	T1,T2,T3
addr_hit[40]	Covered	T1,T2,T3
addr_hit[41]	Covered	T1,T2,T3
addr_hit[42]	Covered	T1,T2,T3
addr_hit[43]	Covered	T1,T2,T3
addr_hit[44]	Covered	T1,T2,T3
addr_hit[45]	Covered	T1,T2,T3
addr_hit[46]	Covered	T1,T2,T3
addr_hit[47]	Covered	T1,T2,T3
addr_hit[48]	Covered	T1,T2,T3
addr_hit[49]	Covered	T1,T2,T3
addr_hit[50]	Covered	T1,T2,T3
addr_hit[51]	Covered	T1,T2,T3
addr_hit[52]	Covered	T1,T2,T3
addr_hit[53]	Covered	T1,T2,T3
addr_hit[54]	Covered	T1,T2,T3
addr_hit[55]	Covered	T1,T2,T3
addr_hit[56]	Covered	T1,T2,T3
addr_hit[57]	Covered	T1,T2,T3
addr_hit[58]	Covered	T1,T2,T3
addr_hit[59]	Covered	T1,T2,T3
addr_hit[60]	Covered	T1,T2,T3
addr_hit[61]	Covered	T1,T2,T3
addr_hit[62]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	3652	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	3660	if ((!rst_shadowed_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : keymgr_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	30391715	4625111	0	0
reAfterRv	30391715	4625087	0	0
rePulse	30391715	4292798	0	0
wePulse	30391715	332289	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	30391715	4625111	0	0
T1	24777	6871	0	0
T2	13532	1013	0	0
T3	12979	1071	0	0
T4	12390	1393	0	0
T5	75243	6440	0	0
T6	155395	29501	0	0
T15	195450	22134	0	0
T16	13207	2808	0	0
T17	9878	581	0	0
T18	34155	15753	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	30391715	4625087	0	0
T1	24777	6871	0	0
T2	13532	1013	0	0
T3	12979	1071	0	0
T4	12390	1393	0	0
T5	75243	6440	0	0
T6	155395	29501	0	0
T15	195450	22134	0	0
T16	13207	2808	0	0
T17	9878	581	0	0
T18	34155	15753	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	30391715	4292798	0	0
T1	24777	6780	0	0
T2	13532	654	0	0
T3	12979	963	0	0
T4	12390	1305	0	0
T5	75243	6268	0	0
T6	155395	27786	0	0
T15	195450	19080	0	0
T16	13207	2524	0	0
T17	9878	448	0	0
T18	34155	15081	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	30391715	332289	0	0
T1	24777	91	0	0
T2	13532	359	0	0
T3	12979	108	0	0
T4	12390	88	0	0
T5	75243	172	0	0
T6	155395	1715	0	0
T15	195450	3054	0	0
T16	13207	284	0	0
T17	9878	133	0	0
T18	34155	672	0	0