Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.09	96.20	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	30391715	20525	0	0
attest_sw_binding_0_rd_A	30391715	776	0	0
attest_sw_binding_1_rd_A	30391715	774	0	0
attest_sw_binding_2_rd_A	30391715	826	0	0
attest_sw_binding_3_rd_A	30391715	767	0	0
attest_sw_binding_4_rd_A	30391715	816	0	0
attest_sw_binding_5_rd_A	30391715	862	0	0
attest_sw_binding_6_rd_A	30391715	819	0	0
attest_sw_binding_7_rd_A	30391715	817	0	0
intr_enable_rd_A	30391715	1413	0	0
key_version_rd_A	30391715	776	0	0
max_creator_key_ver_regwen_rd_A	30391715	828	0	0
max_owner_int_key_ver_regwen_rd_A	30391715	824	0	0
max_owner_key_ver_regwen_rd_A	30391715	826	0	0
reseed_interval_regwen_rd_A	30391715	799	0	0
salt_0_rd_A	30391715	787	0	0
salt_1_rd_A	30391715	848	0	0
salt_2_rd_A	30391715	856	0	0
salt_3_rd_A	30391715	839	0	0
salt_4_rd_A	30391715	777	0	0
salt_5_rd_A	30391715	867	0	0
salt_6_rd_A	30391715	796	0	0
salt_7_rd_A	30391715	843	0	0
sealing_sw_binding_0_rd_A	30391715	882	0	0
sealing_sw_binding_1_rd_A	30391715	770	0	0
sealing_sw_binding_2_rd_A	30391715	830	0	0
sealing_sw_binding_3_rd_A	30391715	944	0	0
sealing_sw_binding_4_rd_A	30391715	872	0	0
sealing_sw_binding_5_rd_A	30391715	780	0	0
sealing_sw_binding_6_rd_A	30391715	801	0	0
sealing_sw_binding_7_rd_A	30391715	768	0	0
sideload_clear_rd_A	30391715	937	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30391715	20525	0	0
T7	5237	0	0	0
T22	13598	0	0	0
T30	103022	0	0	0
T32	4884	0	0	0
T38	144221	0	0	0
T41	57228	0	0	0
T52	5594	0	0	0
T61	0	417	0	0
T82	6525	8	0	0
T92	2857	0	0	0
T106	0	181	0	0
T107	0	466	0	0
T113	0	192	0	0
T117	0	146	0	0
T119	0	48	0	0
T120	0	79	0	0
T121	9279	0	0	0
T122	0	416	0	0
T131	0	1	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30391715	776	0	0
T7	5237	0	0	0
T22	13598	0	0	0
T30	103022	0	0	0
T32	4884	0	0	0
T38	144221	0	0	0
T41	57228	0	0	0
T52	5594	0	0	0
T82	6525	8	0	0
T92	2857	0	0	0
T113	0	32	0	0
T114	0	68	0	0
T116	0	51	0	0
T121	9279	0	0	0
T141	0	1	0	0
T143	0	3	0	0
T167	0	7	0	0
T168	0	8	0	0
T169	0	31	0	0
T170	0	9	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30391715	774	0	0
T7	5237	0	0	0
T22	13598	0	0	0
T30	103022	0	0	0
T32	4884	0	0	0
T38	144221	0	0	0
T41	57228	0	0	0
T52	5594	0	0	0
T82	6525	41	0	0
T92	2857	0	0	0
T113	0	25	0	0
T114	0	85	0	0
T116	0	52	0	0
T121	9279	0	0	0
T135	0	14	0	0
T167	0	3	0	0
T168	0	7	0	0
T169	0	35	0	0
T170	0	3	0	0
T171	0	25	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30391715	826	0	0
T7	5237	0	0	0
T22	13598	0	0	0
T30	103022	0	0	0
T32	4884	0	0	0
T38	144221	0	0	0
T41	57228	0	0	0
T52	5594	0	0	0
T82	6525	19	0	0
T92	2857	0	0	0
T113	0	26	0	0
T114	0	92	0	0
T116	0	58	0	0
T121	9279	0	0	0
T122	0	5	0	0
T135	0	1	0	0
T143	0	1	0	0
T167	0	18	0	0
T168	0	14	0	0
T169	0	19	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30391715	767	0	0
T7	5237	0	0	0
T22	13598	0	0	0
T30	103022	0	0	0
T32	4884	0	0	0
T38	144221	0	0	0
T41	57228	0	0	0
T52	5594	0	0	0
T82	6525	7	0	0
T92	2857	0	0	0
T113	0	2	0	0
T114	0	94	0	0
T116	0	37	0	0
T121	9279	0	0	0
T122	0	11	0	0
T135	0	3	0	0
T143	0	15	0	0
T167	0	6	0	0
T168	0	17	0	0
T169	0	31	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30391715	816	0	0
T7	5237	0	0	0
T22	13598	0	0	0
T30	103022	0	0	0
T32	4884	0	0	0
T38	144221	0	0	0
T41	57228	0	0	0
T52	5594	0	0	0
T82	6525	10	0	0
T92	2857	0	0	0
T113	0	17	0	0
T114	0	94	0	0
T116	0	40	0	0
T121	9279	0	0	0
T122	0	5	0	0
T141	0	5	0	0
T143	0	1	0	0
T167	0	1	0	0
T168	0	4	0	0
T169	0	28	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30391715	862	0	0
T7	5237	0	0	0
T22	13598	0	0	0
T30	103022	0	0	0
T32	4884	0	0	0
T38	144221	0	0	0
T41	57228	0	0	0
T52	5594	0	0	0
T82	6525	18	0	0
T92	2857	0	0	0
T113	0	5	0	0
T114	0	84	0	0
T116	0	38	0	0
T121	9279	0	0	0
T135	0	5	0	0
T141	0	1	0	0
T167	0	6	0	0
T168	0	4	0	0
T169	0	24	0	0
T170	0	16	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30391715	819	0	0
T7	5237	0	0	0
T22	13598	0	0	0
T30	103022	0	0	0
T32	4884	0	0	0
T38	144221	0	0	0
T41	57228	0	0	0
T52	5594	0	0	0
T82	6525	11	0	0
T92	2857	0	0	0
T113	0	2	0	0
T114	0	84	0	0
T116	0	56	0	0
T121	9279	0	0	0
T122	0	3	0	0
T135	0	10	0	0
T141	0	9	0	0
T143	0	1	0	0
T167	0	8	0	0
T168	0	8	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30391715	817	0	0
T7	5237	0	0	0
T22	13598	0	0	0
T30	103022	0	0	0
T32	4884	0	0	0
T38	144221	0	0	0
T41	57228	0	0	0
T52	5594	0	0	0
T82	6525	32	0	0
T92	2857	0	0	0
T113	0	1	0	0
T114	0	85	0	0
T116	0	51	0	0
T121	9279	0	0	0
T122	0	4	0	0
T143	0	7	0	0
T167	0	7	0	0
T168	0	15	0	0
T169	0	18	0	0
T170	0	13	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30391715	1413	0	0
T7	5237	0	0	0
T22	13598	0	0	0
T30	103022	0	0	0
T32	4884	0	0	0
T38	144221	0	0	0
T41	57228	0	0	0
T52	5594	0	0	0
T82	6525	19	0	0
T92	2857	0	0	0
T113	0	9	0	0
T114	0	88	0	0
T116	0	42	0	0
T121	9279	0	0	0
T122	0	2	0	0
T167	0	14	0	0
T172	0	27	0	0
T173	0	11	0	0
T174	0	2	0	0
T175	0	16	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30391715	776	0	0
T7	5237	0	0	0
T22	13598	0	0	0
T30	103022	0	0	0
T32	4884	0	0	0
T38	144221	0	0	0
T41	57228	0	0	0
T52	5594	0	0	0
T82	6525	12	0	0
T92	2857	0	0	0
T113	0	6	0	0
T114	0	76	0	0
T116	0	48	0	0
T121	9279	0	0	0
T122	0	17	0	0
T141	0	9	0	0
T143	0	7	0	0
T167	0	15	0	0
T168	0	9	0	0
T169	0	12	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30391715	828	0	0
T7	5237	0	0	0
T22	13598	0	0	0
T30	103022	0	0	0
T32	4884	0	0	0
T38	144221	0	0	0
T41	57228	0	0	0
T52	5594	0	0	0
T82	6525	19	0	0
T92	2857	0	0	0
T113	0	18	0	0
T114	0	70	0	0
T116	0	65	0	0
T121	9279	0	0	0
T122	0	4	0	0
T167	0	8	0	0
T168	0	14	0	0
T169	0	33	0	0
T170	0	6	0	0
T171	0	7	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30391715	824	0	0
T7	5237	0	0	0
T22	13598	0	0	0
T30	103022	0	0	0
T32	4884	0	0	0
T38	144221	0	0	0
T41	57228	0	0	0
T52	5594	0	0	0
T82	6525	16	0	0
T92	2857	0	0	0
T113	0	3	0	0
T114	0	83	0	0
T116	0	54	0	0
T121	9279	0	0	0
T143	0	7	0	0
T167	0	8	0	0
T168	0	10	0	0
T169	0	29	0	0
T170	0	15	0	0
T171	0	20	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30391715	826	0	0
T7	5237	0	0	0
T22	13598	0	0	0
T30	103022	0	0	0
T32	4884	0	0	0
T38	144221	0	0	0
T41	57228	0	0	0
T52	5594	0	0	0
T82	6525	25	0	0
T92	2857	0	0	0
T113	0	20	0	0
T114	0	84	0	0
T116	0	48	0	0
T121	9279	0	0	0
T122	0	7	0	0
T135	0	3	0	0
T167	0	3	0	0
T168	0	13	0	0
T169	0	22	0	0
T170	0	11	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30391715	799	0	0
T7	5237	0	0	0
T22	13598	0	0	0
T30	103022	0	0	0
T32	4884	0	0	0
T38	144221	0	0	0
T41	57228	0	0	0
T52	5594	0	0	0
T82	6525	18	0	0
T92	2857	0	0	0
T113	0	1	0	0
T114	0	95	0	0
T116	0	58	0	0
T121	9279	0	0	0
T122	0	12	0	0
T135	0	6	0	0
T143	0	5	0	0
T167	0	8	0	0
T168	0	11	0	0
T169	0	23	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30391715	787	0	0
T7	5237	0	0	0
T22	13598	0	0	0
T30	103022	0	0	0
T32	4884	0	0	0
T38	144221	0	0	0
T41	57228	0	0	0
T52	5594	0	0	0
T82	6525	17	0	0
T92	2857	0	0	0
T113	0	16	0	0
T114	0	92	0	0
T116	0	58	0	0
T121	9279	0	0	0
T135	0	7	0	0
T141	0	5	0	0
T143	0	1	0	0
T167	0	10	0	0
T168	0	8	0	0
T169	0	20	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30391715	848	0	0
T7	5237	0	0	0
T22	13598	0	0	0
T30	103022	0	0	0
T32	4884	0	0	0
T38	144221	0	0	0
T41	57228	0	0	0
T52	5594	0	0	0
T82	6525	11	0	0
T92	2857	0	0	0
T113	0	9	0	0
T114	0	85	0	0
T116	0	64	0	0
T121	9279	0	0	0
T135	0	14	0	0
T141	0	1	0	0
T167	0	2	0	0
T168	0	3	0	0
T169	0	23	0	0
T171	0	22	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30391715	856	0	0
T7	5237	0	0	0
T22	13598	0	0	0
T30	103022	0	0	0
T32	4884	0	0	0
T38	144221	0	0	0
T41	57228	0	0	0
T52	5594	0	0	0
T82	6525	8	0	0
T92	2857	0	0	0
T113	0	10	0	0
T114	0	61	0	0
T116	0	67	0	0
T121	9279	0	0	0
T141	0	7	0	0
T143	0	17	0	0
T167	0	16	0	0
T168	0	10	0	0
T169	0	16	0	0
T170	0	4	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30391715	839	0	0
T7	5237	0	0	0
T22	13598	0	0	0
T30	103022	0	0	0
T32	4884	0	0	0
T38	144221	0	0	0
T41	57228	0	0	0
T52	5594	0	0	0
T82	6525	12	0	0
T92	2857	0	0	0
T113	0	11	0	0
T114	0	90	0	0
T116	0	67	0	0
T121	9279	0	0	0
T122	0	5	0	0
T135	0	8	0	0
T143	0	3	0	0
T167	0	12	0	0
T168	0	7	0	0
T169	0	34	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30391715	777	0	0
T7	5237	0	0	0
T22	13598	0	0	0
T30	103022	0	0	0
T32	4884	0	0	0
T38	144221	0	0	0
T41	57228	0	0	0
T52	5594	0	0	0
T82	6525	9	0	0
T92	2857	0	0	0
T114	0	80	0	0
T116	0	43	0	0
T121	9279	0	0	0
T122	0	14	0	0
T135	0	7	0	0
T167	0	12	0	0
T168	0	10	0	0
T169	0	16	0	0
T170	0	7	0	0
T171	0	34	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30391715	867	0	0
T7	5237	0	0	0
T22	13598	0	0	0
T30	103022	0	0	0
T32	4884	0	0	0
T38	144221	0	0	0
T41	57228	0	0	0
T52	5594	0	0	0
T82	6525	20	0	0
T92	2857	0	0	0
T113	0	29	0	0
T114	0	85	0	0
T116	0	58	0	0
T121	9279	0	0	0
T122	0	9	0	0
T135	0	10	0	0
T167	0	1	0	0
T168	0	12	0	0
T169	0	41	0	0
T170	0	8	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30391715	796	0	0
T7	5237	0	0	0
T22	13598	0	0	0
T30	103022	0	0	0
T32	4884	0	0	0
T38	144221	0	0	0
T41	57228	0	0	0
T52	5594	0	0	0
T82	6525	19	0	0
T92	2857	0	0	0
T114	0	66	0	0
T116	0	42	0	0
T121	9279	0	0	0
T122	0	3	0	0
T135	0	9	0	0
T141	0	2	0	0
T143	0	1	0	0
T167	0	4	0	0
T168	0	7	0	0
T169	0	30	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30391715	843	0	0
T7	5237	0	0	0
T22	13598	0	0	0
T30	103022	0	0	0
T32	4884	0	0	0
T38	144221	0	0	0
T41	57228	0	0	0
T52	5594	0	0	0
T82	6525	21	0	0
T92	2857	0	0	0
T113	0	16	0	0
T114	0	70	0	0
T116	0	55	0	0
T121	9279	0	0	0
T122	0	4	0	0
T135	0	3	0	0
T167	0	16	0	0
T168	0	13	0	0
T169	0	32	0	0
T170	0	5	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30391715	882	0	0
T7	5237	0	0	0
T22	13598	0	0	0
T30	103022	0	0	0
T32	4884	0	0	0
T38	144221	0	0	0
T41	57228	0	0	0
T52	5594	0	0	0
T82	6525	32	0	0
T92	2857	0	0	0
T113	0	9	0	0
T114	0	93	0	0
T116	0	63	0	0
T121	9279	0	0	0
T135	0	2	0	0
T141	0	7	0	0
T167	0	16	0	0
T168	0	12	0	0
T169	0	24	0	0
T170	0	5	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30391715	770	0	0
T7	5237	0	0	0
T22	13598	0	0	0
T30	103022	0	0	0
T32	4884	0	0	0
T38	144221	0	0	0
T41	57228	0	0	0
T52	5594	0	0	0
T82	6525	11	0	0
T92	2857	0	0	0
T113	0	8	0	0
T114	0	80	0	0
T116	0	36	0	0
T121	9279	0	0	0
T135	0	11	0	0
T143	0	6	0	0
T167	0	1	0	0
T168	0	2	0	0
T169	0	21	0	0
T170	0	5	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30391715	830	0	0
T7	5237	0	0	0
T22	13598	0	0	0
T30	103022	0	0	0
T32	4884	0	0	0
T38	144221	0	0	0
T41	57228	0	0	0
T52	5594	0	0	0
T82	6525	6	0	0
T92	2857	0	0	0
T113	0	23	0	0
T114	0	65	0	0
T116	0	21	0	0
T121	9279	0	0	0
T135	0	3	0	0
T143	0	17	0	0
T167	0	8	0	0
T168	0	14	0	0
T169	0	13	0	0
T171	0	9	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30391715	944	0	0
T7	5237	0	0	0
T22	13598	0	0	0
T30	103022	0	0	0
T32	4884	0	0	0
T38	144221	0	0	0
T41	57228	0	0	0
T52	5594	0	0	0
T82	6525	29	0	0
T92	2857	0	0	0
T113	0	33	0	0
T114	0	85	0	0
T116	0	55	0	0
T121	9279	0	0	0
T122	0	9	0	0
T135	0	10	0	0
T143	0	1	0	0
T167	0	14	0	0
T168	0	7	0	0
T169	0	35	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30391715	872	0	0
T7	5237	0	0	0
T22	13598	0	0	0
T30	103022	0	0	0
T32	4884	0	0	0
T38	144221	0	0	0
T41	57228	0	0	0
T52	5594	0	0	0
T82	6525	13	0	0
T92	2857	0	0	0
T113	0	8	0	0
T114	0	106	0	0
T116	0	56	0	0
T121	9279	0	0	0
T135	0	20	0	0
T143	0	1	0	0
T167	0	10	0	0
T168	0	6	0	0
T169	0	23	0	0
T170	0	3	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30391715	780	0	0
T7	5237	0	0	0
T22	13598	0	0	0
T30	103022	0	0	0
T32	4884	0	0	0
T38	144221	0	0	0
T41	57228	0	0	0
T52	5594	0	0	0
T82	6525	10	0	0
T92	2857	0	0	0
T114	0	70	0	0
T116	0	38	0	0
T121	9279	0	0	0
T122	0	5	0	0
T167	0	9	0	0
T168	0	13	0	0
T169	0	41	0	0
T170	0	2	0	0
T171	0	30	0	0
T176	0	36	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30391715	801	0	0
T7	5237	0	0	0
T22	13598	0	0	0
T30	103022	0	0	0
T32	4884	0	0	0
T38	144221	0	0	0
T41	57228	0	0	0
T52	5594	0	0	0
T82	6525	18	0	0
T92	2857	0	0	0
T114	0	83	0	0
T116	0	30	0	0
T121	9279	0	0	0
T141	0	4	0	0
T143	0	1	0	0
T167	0	10	0	0
T168	0	14	0	0
T169	0	25	0	0
T170	0	12	0	0
T171	0	20	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30391715	768	0	0
T7	5237	0	0	0
T22	13598	0	0	0
T30	103022	0	0	0
T32	4884	0	0	0
T38	144221	0	0	0
T41	57228	0	0	0
T52	5594	0	0	0
T82	6525	11	0	0
T92	2857	0	0	0
T113	0	19	0	0
T114	0	88	0	0
T116	0	52	0	0
T121	9279	0	0	0
T135	0	8	0	0
T143	0	6	0	0
T167	0	13	0	0
T168	0	6	0	0
T169	0	35	0	0
T170	0	15	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30391715	937	0	0
T7	5237	0	0	0
T22	13598	0	0	0
T30	103022	0	0	0
T32	4884	0	0	0
T38	144221	0	0	0
T41	57228	0	0	0
T52	5594	0	0	0
T82	6525	21	0	0
T92	2857	0	0	0
T113	0	11	0	0
T114	0	82	0	0
T116	0	47	0	0
T121	9279	0	0	0
T122	0	10	0	0
T135	0	13	0	0
T141	0	2	0	0
T167	0	2	0	0
T168	0	11	0	0
T169	0	36	0	0