Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4041174	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

610852

1

T1

486

T2

261

T3

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4247050	1			T1	1938		T2	1718		T3	1
values[0x0]	200803	1			T1	193		T2	82		T3	8
values[0x1]	204173	1			T1	171		T2	94		T3	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2751651	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1900375

1

T1

1073

T2

766

T3

6

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16599	1			T1	7		T2	5		T5	5
valid_sources[0x01]	18332	1			T1	18		T2	3		T5	6
valid_sources[0x02]	14320	1			T1	6		T2	1		T5	6
valid_sources[0x03]	16186	1			T1	7		T2	24		T5	5
valid_sources[0x04]	13871	1			T1	18		T2	13		T5	6
valid_sources[0x05]	13581	1			T1	11		T2	8		T5	7
valid_sources[0x06]	15160	1			T1	17		T2	19		T5	7
valid_sources[0x07]	15263	1			T1	6		T2	4		T5	6
valid_sources[0x08]	15801	1			T1	3		T2	2		T5	3
valid_sources[0x09]	14376	1			T1	11		T2	6		T5	3
valid_sources[0x0a]	13598	1			T1	10		T5	4		T6	3
valid_sources[0x0b]	17241	1			T1	10		T2	7		T5	4
valid_sources[0x0c]	14705	1			T1	19		T2	6		T5	3
valid_sources[0x0d]	23918	1			T1	5		T2	9		T5	5
valid_sources[0x0e]	13882	1			T1	15		T2	9		T5	6
valid_sources[0x0f]	15612	1			T1	18		T2	4		T5	1
valid_sources[0x10]	15172	1			T1	15		T2	3		T5	4
valid_sources[0x11]	15712	1			T1	6		T5	2		T6	17
valid_sources[0x12]	18830	1			T1	12		T2	12		T5	2
valid_sources[0x13]	13404	1			T1	11		T2	13		T5	2
valid_sources[0x14]	13477	1			T1	7		T2	3		T5	7
valid_sources[0x15]	16507	1			T1	9		T2	1		T5	4
valid_sources[0x16]	16842	1			T1	3		T2	10		T5	3
valid_sources[0x17]	24442	1			T1	13		T2	11		T5	9
valid_sources[0x18]	12796	1			T1	3		T2	26		T5	4
valid_sources[0x19]	13957	1			T1	11		T2	8		T5	3
valid_sources[0x1a]	12862	1			T1	13		T2	3		T5	5
valid_sources[0x1b]	14243	1			T1	2		T5	2		T6	26
valid_sources[0x1c]	13468	1			T1	3		T2	5		T5	6
valid_sources[0x1d]	14205	1			T1	10		T2	11		T5	2
valid_sources[0x1e]	32493	1			T1	5		T2	7		T5	2
valid_sources[0x1f]	13870	1			T1	12		T2	2		T3	20
valid_sources[0x20]	13105	1			T1	11		T2	16		T5	4
valid_sources[0x21]	13362	1			T1	8		T2	8		T5	9
valid_sources[0x22]	17392	1			T1	10		T2	1		T5	3
valid_sources[0x23]	13327	1			T1	14		T5	6		T6	4
valid_sources[0x24]	16059	1			T1	10		T2	13		T5	5
valid_sources[0x25]	14008	1			T1	9		T2	6		T5	5
valid_sources[0x26]	37465	1			T1	14		T2	13		T5	2
valid_sources[0x27]	17375	1			T1	18		T2	4		T5	5
valid_sources[0x28]	13118	1			T1	12		T2	19		T5	3
valid_sources[0x29]	19409	1			T1	5		T2	4		T5	3
valid_sources[0x2a]	18788	1			T1	6		T2	6		T5	2
valid_sources[0x2b]	12938	1			T1	3		T2	4		T5	4
valid_sources[0x2c]	13296	1			T1	7		T2	14		T5	2
valid_sources[0x2d]	16416	1			T1	6		T2	5		T5	8
valid_sources[0x2e]	49342	1			T1	13		T2	13		T5	2
valid_sources[0x2f]	13983	1			T1	10		T2	13		T5	4
valid_sources[0x30]	18159	1			T1	7		T2	13		T5	10
valid_sources[0x31]	13227	1			T1	4		T2	8		T5	3
valid_sources[0x32]	16144	1			T1	5		T2	3		T5	9
valid_sources[0x33]	14205	1			T1	5		T2	11		T5	4
valid_sources[0x34]	17399	1			T1	10		T2	16		T5	4
valid_sources[0x35]	15060	1			T1	3		T2	4		T5	6
valid_sources[0x36]	19743	1			T1	12		T2	20		T5	3
valid_sources[0x37]	16258	1			T1	10		T5	2		T6	3
valid_sources[0x38]	13905	1			T1	9		T2	14		T5	5
valid_sources[0x39]	13451	1			T1	6		T2	1		T5	9
valid_sources[0x3a]	13287	1			T1	9		T2	11		T5	5
valid_sources[0x3b]	14893	1			T1	8		T2	5		T5	6
valid_sources[0x3c]	18613	1			T1	14		T5	5		T6	36
valid_sources[0x3d]	13019	1			T1	13		T5	2		T6	26
valid_sources[0x3e]	15312	1			T1	10		T2	19		T5	1
valid_sources[0x3f]	18487	1			T1	7		T5	5		T6	18
valid_sources[0x40]	15092	1			T1	13		T2	1		T5	3
valid_sources[0x41]	18988	1			T1	15		T2	5		T5	2
valid_sources[0x42]	19309	1			T1	10		T5	3		T6	18
valid_sources[0x43]	14090	1			T1	18		T2	1		T5	5
valid_sources[0x44]	15263	1			T1	7		T2	16		T5	6
valid_sources[0x45]	15554	1			T1	3		T2	3		T5	4
valid_sources[0x46]	15700	1			T1	8		T2	5		T5	10
valid_sources[0x47]	39454	1			T1	14		T2	14		T5	6
valid_sources[0x48]	13767	1			T1	25		T2	7		T5	7
valid_sources[0x49]	15342	1			T1	7		T2	8		T5	2
valid_sources[0x4a]	15199	1			T1	3		T2	11		T5	9
valid_sources[0x4b]	14373	1			T1	11		T2	10		T5	4
valid_sources[0x4c]	13550	1			T1	14		T2	6		T5	5
valid_sources[0x4d]	13081	1			T1	13		T2	20		T5	3
valid_sources[0x4e]	13397	1			T1	16		T2	21		T5	7
valid_sources[0x4f]	65511	1			T1	10		T2	4		T5	4
valid_sources[0x50]	13702	1			T1	5		T2	8		T5	5
valid_sources[0x51]	15817	1			T1	9		T2	1		T5	4
valid_sources[0x52]	13386	1			T1	6		T6	7		T15	37
valid_sources[0x53]	14132	1			T1	6		T2	16		T5	5
valid_sources[0x54]	18058	1			T1	11		T2	1		T5	4
valid_sources[0x55]	15951	1			T1	5		T2	15		T5	5
valid_sources[0x56]	15840	1			T1	4		T5	2		T6	13
valid_sources[0x57]	23423	1			T1	10		T2	20		T5	5
valid_sources[0x58]	16294	1			T1	12		T4	2285		T5	2
valid_sources[0x59]	20188	1			T1	7		T2	5		T5	7
valid_sources[0x5a]	17914	1			T1	8		T2	10		T5	2
valid_sources[0x5b]	14222	1			T1	6		T2	9		T5	3
valid_sources[0x5c]	13422	1			T1	10		T2	10		T5	6
valid_sources[0x5d]	21034	1			T1	14		T2	5		T5	6
valid_sources[0x5e]	17067	1			T1	10		T5	4		T6	16
valid_sources[0x5f]	13015	1			T1	12		T2	29		T5	1
valid_sources[0x60]	13810	1			T1	10		T2	12		T5	2
valid_sources[0x61]	13253	1			T1	6		T2	1		T5	7
valid_sources[0x62]	13792	1			T1	14		T2	12		T5	4
valid_sources[0x63]	23694	1			T1	9		T2	11		T5	7
valid_sources[0x64]	15554	1			T1	15		T5	3		T6	7
valid_sources[0x65]	12880	1			T1	8		T5	5		T6	12
valid_sources[0x66]	15177	1			T1	10		T2	5		T5	4
valid_sources[0x67]	132777	1			T1	7		T2	9		T5	2
valid_sources[0x68]	16068	1			T1	9		T2	3		T5	5
valid_sources[0x69]	15245	1			T1	9		T2	3		T5	4
valid_sources[0x6a]	13331	1			T1	10		T5	9		T6	17
valid_sources[0x6b]	13287	1			T1	5		T2	1		T5	3
valid_sources[0x6c]	13419	1			T1	9		T2	6		T6	10
valid_sources[0x6d]	26702	1			T1	10		T2	11		T5	5
valid_sources[0x6e]	18921	1			T1	8		T2	8		T5	4
valid_sources[0x6f]	14969	1			T1	8		T2	7		T5	1
valid_sources[0x70]	18322	1			T1	6		T2	1		T5	6
valid_sources[0x71]	17046	1			T1	5		T2	3		T5	6
valid_sources[0x72]	13563	1			T1	4		T2	15		T5	8
valid_sources[0x73]	12945	1			T1	13		T2	17		T5	4
valid_sources[0x74]	15523	1			T1	9		T2	4		T5	4
valid_sources[0x75]	35958	1			T1	12		T2	11		T5	2
valid_sources[0x76]	13856	1			T1	7		T2	12		T5	1
valid_sources[0x77]	16066	1			T1	3		T2	6		T5	5
valid_sources[0x78]	38939	1			T1	4		T5	4		T6	21
valid_sources[0x79]	13271	1			T1	11		T5	5		T6	15
valid_sources[0x7a]	13488	1			T1	11		T2	7		T5	5
valid_sources[0x7b]	13424	1			T1	13		T2	11		T5	1
valid_sources[0x7c]	14708	1			T1	8		T2	2		T5	5
valid_sources[0x7d]	13651	1			T1	5		T2	1		T5	3
valid_sources[0x7e]	15325	1			T1	11		T5	14		T6	36
valid_sources[0x7f]	17092	1			T1	9		T2	1		T5	3
valid_sources[0x80]	14603	1			T1	4		T2	8		T5	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

332663

1

T1

214

T2

212

T3

1

values[0x0]

all_enables

biggest_size

145850

1

T1

149

T2

36

T3

1

values[0x1]

all_enables

biggest_size

132339

1

T1

123

T2

13

T3

4