Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.09	96.20	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	30266892	19540	0	0
attest_sw_binding_0_rd_A	30266892	1141	0	0
attest_sw_binding_1_rd_A	30266892	1167	0	0
attest_sw_binding_2_rd_A	30266892	1236	0	0
attest_sw_binding_3_rd_A	30266892	1191	0	0
attest_sw_binding_4_rd_A	30266892	1308	0	0
attest_sw_binding_5_rd_A	30266892	1246	0	0
attest_sw_binding_6_rd_A	30266892	1099	0	0
attest_sw_binding_7_rd_A	30266892	1270	0	0
intr_enable_rd_A	30266892	2148	0	0
key_version_rd_A	30266892	1046	0	0
max_creator_key_ver_regwen_rd_A	30266892	1143	0	0
max_owner_int_key_ver_regwen_rd_A	30266892	1159	0	0
max_owner_key_ver_regwen_rd_A	30266892	1389	0	0
reseed_interval_regwen_rd_A	30266892	1259	0	0
salt_0_rd_A	30266892	1160	0	0
salt_1_rd_A	30266892	1227	0	0
salt_2_rd_A	30266892	1214	0	0
salt_3_rd_A	30266892	1276	0	0
salt_4_rd_A	30266892	1144	0	0
salt_5_rd_A	30266892	1155	0	0
salt_6_rd_A	30266892	1273	0	0
salt_7_rd_A	30266892	1225	0	0
sealing_sw_binding_0_rd_A	30266892	1254	0	0
sealing_sw_binding_1_rd_A	30266892	1246	0	0
sealing_sw_binding_2_rd_A	30266892	1159	0	0
sealing_sw_binding_3_rd_A	30266892	1250	0	0
sealing_sw_binding_4_rd_A	30266892	1267	0	0
sealing_sw_binding_5_rd_A	30266892	1177	0	0
sealing_sw_binding_6_rd_A	30266892	1385	0	0
sealing_sw_binding_7_rd_A	30266892	1125	0	0
sideload_clear_rd_A	30266892	1081	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30266892	19540	0	0
T50	3875	0	0	0
T70	4598	0	0	0
T81	25321	175	0	0
T82	15444	0	0	0
T83	2283	0	0	0
T118	9420	457	0	0
T119	0	477	0	0
T123	0	1	0	0
T135	0	17	0	0
T136	0	365	0	0
T137	0	176	0	0
T139	0	36	0	0
T141	5872	0	0	0
T142	16960	0	0	0
T143	24805	0	0	0
T144	9614	0	0	0
T145	0	265	0	0
T184	0	1	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30266892	1141	0	0
T23	104040	0	0	0
T55	8652	0	0	0
T81	25321	23	0	0
T82	15444	0	0	0
T83	2283	0	0	0
T84	6160	0	0	0
T85	3814	0	0	0
T86	5187	0	0	0
T87	86213	0	0	0
T145	0	2	0	0
T156	0	1	0	0
T184	0	7	0	0
T185	3297	10	0	0
T186	0	4	0	0
T187	0	36	0	0
T188	0	60	0	0
T189	0	19	0	0
T190	0	32	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30266892	1167	0	0
T23	104040	0	0	0
T55	8652	0	0	0
T81	25321	78	0	0
T82	15444	0	0	0
T83	2283	0	0	0
T84	6160	0	0	0
T85	3814	0	0	0
T86	5187	0	0	0
T87	86213	0	0	0
T145	0	12	0	0
T156	0	2	0	0
T184	0	7	0	0
T185	3297	5	0	0
T186	0	18	0	0
T187	0	14	0	0
T188	0	57	0	0
T189	0	37	0	0
T191	0	15	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30266892	1236	0	0
T23	104040	0	0	0
T55	8652	0	0	0
T81	25321	30	0	0
T82	15444	0	0	0
T83	2283	0	0	0
T84	6160	0	0	0
T85	3814	0	0	0
T86	5187	0	0	0
T87	86213	0	0	0
T145	0	3	0	0
T156	0	5	0	0
T184	0	16	0	0
T185	3297	12	0	0
T186	0	38	0	0
T187	0	30	0	0
T188	0	66	0	0
T191	0	4	0	0
T192	0	6	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30266892	1191	0	0
T23	104040	0	0	0
T55	8652	0	0	0
T81	25321	34	0	0
T82	15444	0	0	0
T83	2283	0	0	0
T84	6160	0	0	0
T85	3814	0	0	0
T86	5187	0	0	0
T87	86213	0	0	0
T145	0	15	0	0
T184	0	4	0	0
T185	3297	9	0	0
T187	0	50	0	0
T188	0	73	0	0
T189	0	43	0	0
T190	0	31	0	0
T191	0	15	0	0
T193	0	13	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30266892	1308	0	0
T23	104040	0	0	0
T55	8652	0	0	0
T81	25321	44	0	0
T82	15444	0	0	0
T83	2283	0	0	0
T84	6160	0	0	0
T85	3814	0	0	0
T86	5187	0	0	0
T87	86213	0	0	0
T145	0	5	0	0
T156	0	5	0	0
T184	0	14	0	0
T185	3297	7	0	0
T186	0	49	0	0
T187	0	45	0	0
T188	0	66	0	0
T189	0	44	0	0
T191	0	9	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30266892	1246	0	0
T23	104040	0	0	0
T55	8652	0	0	0
T81	25321	54	0	0
T82	15444	0	0	0
T83	2283	0	0	0
T84	6160	0	0	0
T85	3814	0	0	0
T86	5187	0	0	0
T87	86213	0	0	0
T145	0	10	0	0
T156	0	2	0	0
T184	0	14	0	0
T185	3297	7	0	0
T186	0	21	0	0
T187	0	12	0	0
T188	0	74	0	0
T191	0	3	0	0
T192	0	5	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30266892	1099	0	0
T23	104040	0	0	0
T55	8652	0	0	0
T81	25321	39	0	0
T82	15444	0	0	0
T83	2283	0	0	0
T84	6160	0	0	0
T85	3814	0	0	0
T86	5187	0	0	0
T87	86213	0	0	0
T145	0	3	0	0
T156	0	4	0	0
T184	0	10	0	0
T185	3297	6	0	0
T186	0	13	0	0
T187	0	27	0	0
T188	0	86	0	0
T189	0	46	0	0
T190	0	22	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30266892	1270	0	0
T23	104040	0	0	0
T55	8652	0	0	0
T81	25321	38	0	0
T82	15444	0	0	0
T83	2283	0	0	0
T84	6160	0	0	0
T85	3814	0	0	0
T86	5187	0	0	0
T87	86213	0	0	0
T145	0	2	0	0
T156	0	7	0	0
T184	0	11	0	0
T185	3297	5	0	0
T186	0	40	0	0
T187	0	58	0	0
T188	0	60	0	0
T189	0	30	0	0
T191	0	12	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30266892	2148	0	0
T25	71824	51	0	0
T34	15215	0	0	0
T39	3203	0	0	0
T40	17614	0	0	0
T44	3506	0	0	0
T49	12908	0	0	0
T53	0	23	0	0
T59	0	12	0	0
T68	0	47	0	0
T81	0	65	0	0
T88	5067	0	0	0
T148	8199	0	0	0
T149	20521	0	0	0
T150	188775	0	0	0
T152	0	10	0	0
T154	0	7	0	0
T194	0	24	0	0
T195	0	4	0	0
T196	0	22	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30266892	1046	0	0
T23	104040	0	0	0
T55	8652	0	0	0
T81	25321	29	0	0
T82	15444	0	0	0
T83	2283	0	0	0
T84	6160	0	0	0
T85	3814	0	0	0
T86	5187	0	0	0
T87	86213	0	0	0
T145	0	7	0	0
T184	0	10	0	0
T185	3297	4	0	0
T186	0	11	0	0
T187	0	27	0	0
T188	0	68	0	0
T189	0	32	0	0
T191	0	7	0	0
T192	0	4	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30266892	1143	0	0
T23	104040	0	0	0
T55	8652	0	0	0
T81	25321	30	0	0
T82	15444	0	0	0
T83	2283	0	0	0
T84	6160	0	0	0
T85	3814	0	0	0
T86	5187	0	0	0
T87	86213	0	0	0
T145	0	9	0	0
T156	0	5	0	0
T184	0	2	0	0
T185	3297	3	0	0
T186	0	6	0	0
T187	0	34	0	0
T188	0	68	0	0
T189	0	39	0	0
T192	0	6	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30266892	1159	0	0
T23	104040	0	0	0
T55	8652	0	0	0
T81	25321	12	0	0
T82	15444	0	0	0
T83	2283	0	0	0
T84	6160	0	0	0
T85	3814	0	0	0
T86	5187	0	0	0
T87	86213	0	0	0
T145	0	9	0	0
T156	0	9	0	0
T184	2818	9	0	0
T186	0	38	0	0
T187	0	28	0	0
T188	0	68	0	0
T189	0	31	0	0
T190	0	23	0	0
T191	0	2	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30266892	1389	0	0
T23	104040	0	0	0
T55	8652	0	0	0
T81	25321	29	0	0
T82	15444	0	0	0
T83	2283	0	0	0
T84	6160	0	0	0
T85	3814	0	0	0
T86	5187	0	0	0
T87	86213	0	0	0
T145	0	6	0	0
T156	0	6	0	0
T184	0	10	0	0
T185	3297	7	0	0
T186	0	27	0	0
T187	0	32	0	0
T188	0	71	0	0
T191	0	10	0	0
T192	0	3	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30266892	1259	0	0
T23	104040	0	0	0
T55	8652	0	0	0
T81	25321	32	0	0
T82	15444	0	0	0
T83	2283	0	0	0
T84	6160	0	0	0
T85	3814	0	0	0
T86	5187	0	0	0
T87	86213	0	0	0
T184	0	24	0	0
T185	3297	10	0	0
T186	0	8	0	0
T187	0	33	0	0
T188	0	76	0	0
T189	0	27	0	0
T190	0	10	0	0
T191	0	9	0	0
T192	0	9	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30266892	1160	0	0
T23	104040	0	0	0
T55	8652	0	0	0
T81	25321	24	0	0
T82	15444	0	0	0
T83	2283	0	0	0
T84	6160	0	0	0
T85	3814	0	0	0
T86	5187	0	0	0
T87	86213	0	0	0
T145	0	1	0	0
T156	0	4	0	0
T184	0	18	0	0
T185	3297	6	0	0
T186	0	32	0	0
T187	0	33	0	0
T188	0	50	0	0
T191	0	2	0	0
T192	0	7	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30266892	1227	0	0
T23	104040	0	0	0
T55	8652	0	0	0
T81	25321	21	0	0
T82	15444	0	0	0
T83	2283	0	0	0
T84	6160	0	0	0
T85	3814	0	0	0
T86	5187	0	0	0
T87	86213	0	0	0
T145	0	9	0	0
T156	0	6	0	0
T184	0	6	0	0
T185	3297	18	0	0
T186	0	6	0	0
T187	0	40	0	0
T188	0	47	0	0
T191	0	11	0	0
T192	0	8	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30266892	1214	0	0
T23	104040	0	0	0
T55	8652	0	0	0
T81	25321	40	0	0
T82	15444	0	0	0
T83	2283	0	0	0
T84	6160	0	0	0
T85	3814	0	0	0
T86	5187	0	0	0
T87	86213	0	0	0
T145	0	16	0	0
T156	0	6	0	0
T184	0	14	0	0
T185	3297	2	0	0
T186	0	9	0	0
T187	0	36	0	0
T188	0	63	0	0
T191	0	4	0	0
T192	0	9	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30266892	1276	0	0
T23	104040	0	0	0
T55	8652	0	0	0
T81	25321	42	0	0
T82	15444	0	0	0
T83	2283	0	0	0
T84	6160	0	0	0
T85	3814	0	0	0
T86	5187	0	0	0
T87	86213	0	0	0
T145	0	12	0	0
T156	0	2	0	0
T184	0	4	0	0
T185	3297	1	0	0
T186	0	47	0	0
T187	0	41	0	0
T188	0	74	0	0
T189	0	35	0	0
T190	0	39	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30266892	1144	0	0
T23	104040	0	0	0
T55	8652	0	0	0
T81	25321	40	0	0
T82	15444	0	0	0
T83	2283	0	0	0
T84	6160	0	0	0
T85	3814	0	0	0
T86	5187	0	0	0
T87	86213	0	0	0
T145	0	7	0	0
T184	0	5	0	0
T185	3297	5	0	0
T186	0	25	0	0
T187	0	19	0	0
T188	0	86	0	0
T189	0	33	0	0
T191	0	19	0	0
T192	0	4	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30266892	1155	0	0
T23	104040	0	0	0
T55	8652	0	0	0
T81	25321	28	0	0
T82	15444	0	0	0
T83	2283	0	0	0
T84	6160	0	0	0
T85	3814	0	0	0
T86	5187	0	0	0
T87	86213	0	0	0
T156	0	6	0	0
T184	0	9	0	0
T185	3297	8	0	0
T186	0	9	0	0
T187	0	20	0	0
T188	0	57	0	0
T189	0	42	0	0
T191	0	1	0	0
T192	0	10	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30266892	1273	0	0
T23	104040	0	0	0
T55	8652	0	0	0
T81	25321	26	0	0
T82	15444	0	0	0
T83	2283	0	0	0
T84	6160	0	0	0
T85	3814	0	0	0
T86	5187	0	0	0
T87	86213	0	0	0
T145	0	1	0	0
T184	0	6	0	0
T185	3297	5	0	0
T186	0	12	0	0
T187	0	40	0	0
T188	0	60	0	0
T189	0	33	0	0
T191	0	4	0	0
T192	0	2	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30266892	1225	0	0
T23	104040	0	0	0
T55	8652	0	0	0
T81	25321	69	0	0
T82	15444	0	0	0
T83	2283	0	0	0
T84	6160	0	0	0
T85	3814	0	0	0
T86	5187	0	0	0
T87	86213	0	0	0
T145	0	13	0	0
T156	0	2	0	0
T184	0	10	0	0
T185	3297	11	0	0
T186	0	39	0	0
T187	0	39	0	0
T188	0	50	0	0
T191	0	30	0	0
T192	0	4	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30266892	1254	0	0
T23	104040	0	0	0
T55	8652	0	0	0
T81	25321	38	0	0
T82	15444	0	0	0
T83	2283	0	0	0
T84	6160	0	0	0
T85	3814	0	0	0
T86	5187	0	0	0
T87	86213	0	0	0
T145	0	4	0	0
T156	0	6	0	0
T184	0	10	0	0
T185	3297	1	0	0
T186	0	27	0	0
T187	0	45	0	0
T188	0	69	0	0
T189	0	39	0	0
T191	0	8	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30266892	1246	0	0
T23	104040	0	0	0
T55	8652	0	0	0
T81	25321	39	0	0
T82	15444	0	0	0
T83	2283	0	0	0
T84	6160	0	0	0
T85	3814	0	0	0
T86	5187	0	0	0
T87	86213	0	0	0
T145	0	8	0	0
T156	0	6	0	0
T184	0	11	0	0
T185	3297	7	0	0
T186	0	17	0	0
T187	0	10	0	0
T188	0	88	0	0
T189	0	39	0	0
T192	0	4	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30266892	1159	0	0
T23	104040	0	0	0
T55	8652	0	0	0
T81	25321	39	0	0
T82	15444	0	0	0
T83	2283	0	0	0
T84	6160	0	0	0
T85	3814	0	0	0
T86	5187	0	0	0
T87	86213	0	0	0
T156	0	2	0	0
T184	0	5	0	0
T185	3297	10	0	0
T186	0	8	0	0
T187	0	32	0	0
T188	0	54	0	0
T189	0	43	0	0
T190	0	20	0	0
T191	0	7	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30266892	1250	0	0
T23	104040	0	0	0
T55	8652	0	0	0
T81	25321	23	0	0
T82	15444	0	0	0
T83	2283	0	0	0
T84	6160	0	0	0
T85	3814	0	0	0
T86	5187	0	0	0
T87	86213	0	0	0
T145	0	5	0	0
T156	0	3	0	0
T184	0	12	0	0
T185	3297	6	0	0
T186	0	24	0	0
T187	0	33	0	0
T188	0	46	0	0
T189	0	42	0	0
T191	0	3	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30266892	1267	0	0
T23	104040	0	0	0
T55	8652	0	0	0
T81	25321	25	0	0
T82	15444	0	0	0
T83	2283	0	0	0
T84	6160	0	0	0
T85	3814	0	0	0
T86	5187	0	0	0
T87	86213	0	0	0
T145	0	1	0	0
T156	0	3	0	0
T184	0	2	0	0
T185	3297	11	0	0
T186	0	21	0	0
T187	0	55	0	0
T188	0	48	0	0
T189	0	25	0	0
T191	0	4	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30266892	1177	0	0
T23	104040	0	0	0
T55	8652	0	0	0
T81	25321	45	0	0
T82	15444	0	0	0
T83	2283	0	0	0
T84	6160	0	0	0
T85	3814	0	0	0
T86	5187	0	0	0
T87	86213	0	0	0
T145	0	7	0	0
T156	0	2	0	0
T184	0	6	0	0
T185	3297	6	0	0
T186	0	16	0	0
T187	0	38	0	0
T188	0	71	0	0
T189	0	34	0	0
T191	0	2	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30266892	1385	0	0
T23	104040	0	0	0
T55	8652	0	0	0
T81	25321	26	0	0
T82	15444	0	0	0
T83	2283	0	0	0
T84	6160	0	0	0
T85	3814	0	0	0
T86	5187	0	0	0
T87	86213	0	0	0
T145	0	15	0	0
T156	0	10	0	0
T184	0	12	0	0
T185	3297	16	0	0
T186	0	41	0	0
T187	0	28	0	0
T188	0	73	0	0
T189	0	38	0	0
T191	0	9	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30266892	1125	0	0
T23	104040	0	0	0
T55	8652	0	0	0
T81	25321	51	0	0
T82	15444	0	0	0
T83	2283	0	0	0
T84	6160	0	0	0
T85	3814	0	0	0
T86	5187	0	0	0
T87	86213	0	0	0
T145	0	9	0	0
T184	0	7	0	0
T185	3297	4	0	0
T186	0	6	0	0
T187	0	22	0	0
T188	0	63	0	0
T189	0	36	0	0
T191	0	8	0	0
T192	0	4	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30266892	1081	0	0
T23	104040	0	0	0
T55	8652	0	0	0
T81	25321	34	0	0
T82	15444	0	0	0
T83	2283	0	0	0
T84	6160	0	0	0
T85	3814	0	0	0
T86	5187	0	0	0
T87	86213	0	0	0
T145	0	7	0	0
T156	0	9	0	0
T184	0	5	0	0
T185	3297	1	0	0
T186	0	22	0	0
T187	0	20	0	0
T188	0	53	0	0
T191	0	12	0	0
T192	0	1	0	0