Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : keymgr_ctrl
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.80 100.00 98.09 100.00 100.00 90.91

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_ctrl.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_ctrl 97.80 100.00 98.09 100.00 100.00 90.91



Module Instance : tb.dut.u_ctrl

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.80 100.00 98.09 100.00 100.00 90.91


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.26 99.71 95.24 95.82 100.00 98.67 94.12


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.09 96.20 98.36 99.96 95.92 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[0].u_dec 97.26 97.26
gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[1].u_dec 98.63 98.63
gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[2].u_dec 95.89 95.89
gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[3].u_dec 98.63 98.63
gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[0].u_dec 95.89 95.89
gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[1].u_dec 95.89 95.89
gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[2].u_dec 95.89 95.89
gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[3].u_dec 97.26 97.26
gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[0].u_dec 93.15 93.15
gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[1].u_dec 97.95 97.95
gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[2].u_dec 93.15 93.15
gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[3].u_dec 93.15 93.15
gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[0].u_dec 93.15 93.15
gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[1].u_dec 97.95 97.95
gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[2].u_dec 93.15 93.15
gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[3].u_dec 95.89 95.89
u_cnt 100.00 100.00
u_data_en 84.15 97.44 33.33 100.00 90.00 100.00
u_err 94.81 100.00 84.44 100.00
u_hw_sel 100.00 100.00 100.00 100.00
u_key_valid_sync 100.00 100.00 100.00
u_op_state 100.00 100.00 100.00 100.00 100.00 100.00
u_state_regs 100.00 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : keymgr_ctrl
Line No.TotalCoveredPercent
TOTAL193193100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15211100.00
CONT_ASSIGN15311100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN16511100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN16911100.00
CONT_ASSIGN18511100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN20211100.00
CONT_ASSIGN20711100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN21511100.00
CONT_ASSIGN23011100.00
CONT_ASSIGN24311100.00
ALWAYS24833100.00
CONT_ASSIGN25511100.00
ALWAYS26133100.00
ALWAYS26433100.00
CONT_ASSIGN27511100.00
CONT_ASSIGN27711100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28811100.00
ALWAYS29077100.00
CONT_ASSIGN31611100.00
CONT_ASSIGN31611100.00
CONT_ASSIGN31611100.00
CONT_ASSIGN31611100.00
CONT_ASSIGN31611100.00
CONT_ASSIGN31611100.00
CONT_ASSIGN31611100.00
CONT_ASSIGN31611100.00
CONT_ASSIGN31611100.00
CONT_ASSIGN31611100.00
CONT_ASSIGN31611100.00
CONT_ASSIGN31611100.00
CONT_ASSIGN31611100.00
CONT_ASSIGN31611100.00
CONT_ASSIGN31611100.00
CONT_ASSIGN31611100.00
CONT_ASSIGN32311100.00
CONT_ASSIGN34611100.00
ALWAYS3492121100.00
CONT_ASSIGN43311100.00
CONT_ASSIGN44411100.00
CONT_ASSIGN44511100.00
CONT_ASSIGN45111100.00
ALWAYS4557979100.00
ALWAYS68144100.00
ALWAYS6891212100.00
ALWAYS72555100.00
CONT_ASSIGN76311100.00
CONT_ASSIGN76911100.00
CONT_ASSIGN80011100.00
ALWAYS80833100.00
CONT_ASSIGN81811100.00
ALWAYS89533100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_ctrl.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_ctrl.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
150 1 1
151 1 1
152 1 1
153 1 1
155 1 1
165 1 1
166 1 1
169 1 1
185 1 1
186 1 1
187 1 1
188 1 1
202 1 1
207 1 1
213 1 1
215 1 1
230 1 1
243 1 1
248 1 1
249 1 1
251 1 1
255 1 1
261 3 3
264 1 1
265 1 1
267 1 1
275 1 1
277 1 1
281 2 2
288 1 1
290 1 1
291 1 1
292 1 1
294 1 1
295 1 1
296 1 1
297 1 1
316 16 16
323 1 1
346 1 1
349 1 1
350 1 1
351 1 1
355 1 1
357 1 1
358 1 1
361 1 1
367 1 1
368 1 1
369 1 1
370 1 1
371 1 1
373 unreachable
375 unreachable
380 1 1
381 1 1
382 1 1
388 1 1
389 1 1
393 1 1
394 1 1
395 1 1
396 1 1
433 1 1
444 1 1
445 1 1
451 1 1
455 1 1
458 1 1
459 1 1
460 1 1
463 1 1
466 1 1
469 1 1
472 1 1
475 1 1
478 1 1
481 1 1
484 1 1
487 1 1
491 1 1
493 1 1
496 1 1
500 1 1
504 1 1
507 1 1
508 1 1
509 1 1
510 1 1
MISSING_ELSE
516 1 1
517 1 1
519 1 1
520 1 1
MISSING_ELSE
526 1 1
527 1 1
532 1 1
533 unreachable
534 unreachable
MISSING_ELSE
540 1 1
541 1 1
542 1 1
549 1 1
552 1 1
553 1 1
555 1 1
556 1 1
557 1 1
558 1 1
559 1 1
560 1 1
561 1 1
MISSING_ELSE
567 1 1
572 1 1
575 1 1
576 1 1
577 1 1
578 1 1
579 1 1
580 1 1
581 1 1
MISSING_ELSE
587 1 1
592 1 1
595 1 1
596 1 1
597 1 1
598 1 1
599 1 1
600 1 1
601 1 1
MISSING_ELSE
608 1 1
613 1 1
615 1 1
616 1 1
617 1 1
618 1 1
619 1 1
MISSING_ELSE
628 1 1
630 1 1
631 1 1
640 1 1
641 1 1
642 1 1
MISSING_ELSE
653 1 1
654 1 1
656 1 1
657 1 1
MISSING_ELSE
662 1 1
663 1 1
681 1 1
682 1 1
683 1 1
684 1 1
MISSING_ELSE
689 1 1
690 1 1
692 1 1
694 1 1
697 1 1
700 1 1
703 1 1
706 1 1
709 1 1
712 1 1
713 1 1
717 1 1
725 1 1
726 1 1
730 1 1
731 1 1
732 1 1
MISSING_ELSE
763 1 1
769 1 1
800 1 1
808 1 1
809 1 1
811 1 1
818 1 1
895 3 3


Cond Coverage for Module : keymgr_ctrl
TotalCoveredPercent
Conditions20920598.09
Logical20920598.09
Non-Logical00
Event00

 LINE       150
 EXPRESSION (op_i == OpAdvance)
            ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       151
 EXPRESSION (op_i == OpGenId)
            --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       152
 EXPRESSION (op_i == OpGenSwOut)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       153
 EXPRESSION (op_i == OpGenHwOut)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5

 LINE       155
 EXPRESSION (gen_id_op | gen_sw_op | gen_hw_op)
             ----1----   ----2----   ----3----
-1--2--3-StatusTests
000CoveredT1,T2,T4
001CoveredT1,T2,T5
010CoveredT1,T2,T4
100CoveredT1,T2,T3

 LINE       165
 EXPRESSION (op_start_i & adv_op & en_i)
             -----1----   ---2--   --3-
-1--2--3-StatusTests
011CoveredT1,T2,T4
101CoveredT1,T2,T4
110CoveredT40,T41,T42
111CoveredT1,T2,T4

 LINE       166
 EXPRESSION (op_start_i & gen_hw_op & en_i)
             -----1----   ----2----   --3-
-1--2--3-StatusTests
011CoveredT1,T2,T5
101CoveredT1,T2,T4
110CoveredT7,T8,T43
111CoveredT1,T2,T5

 LINE       169
 EXPRESSION ((op_start_i & dis_op) | ((!en_i)))
             ----------1----------   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT25,T44,T45

 LINE       169
 SUB-EXPRESSION (op_start_i & dis_op)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT25,T44,T45
10CoveredT1,T2,T4
11CoveredT25,T44,T45

 LINE       185
 EXPRESSION (op_req & adv_op)
             ---1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       186
 EXPRESSION (op_req & dis_op)
             ---1--   ---2--
-1--2-StatusTests
01CoveredT25,T44,T45
10CoveredT1,T2,T4
11CoveredT25,T44,T45

 LINE       187
 EXPRESSION (op_req & gen_id_op)
             ---1--   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       188
 EXPRESSION (op_req & (gen_sw_op | gen_hw_op))
             ---1--   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       188
 SUB-EXPRESSION (gen_sw_op | gen_hw_op)
                 ----1----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T5
10CoveredT1,T2,T4

 LINE       202
 EXPRESSION (adv_req & op_ack & ( ~ (op_err | op_fault_err) ))
             ---1---   ---2--   --------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T4
101CoveredT1,T2,T4
110CoveredT1,T2,T4
111CoveredT1,T2,T4

 LINE       202
 SUB-EXPRESSION (op_err | op_fault_err)
                 ---1--   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T16
10CoveredT1,T2,T4

 LINE       230
 EXPRESSION (wipe_req ? KeyUpdateWipe : (random_req ? KeyUpdateRandom : (init_o ? KeyUpdateRoot : op_update_sel)))
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T16

 LINE       230
 SUB-EXPRESSION (random_req ? KeyUpdateRandom : (init_o ? KeyUpdateRoot : op_update_sel))
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       230
 SUB-EXPRESSION (init_o ? KeyUpdateRoot : op_update_sel)
                 ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       243
 EXPRESSION (prng_en_dis_inv_set ? 2'b11 : (prng_reseed_done_i ? ({1'b0, prng_en_dis_inv_q[1]}) : prng_en_dis_inv_q))
             ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       243
 SUB-EXPRESSION (prng_reseed_done_i ? ({1'b0, prng_en_dis_inv_q[1]}) : prng_en_dis_inv_q)
                 ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       255
 EXPRESSION (random_req | wipe_req | prng_en_dis_inv_q[0])
             -----1----   ----2---   ----------3---------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT1,T2,T4
010CoveredT1,T2,T16
100CoveredT1,T2,T4

 LINE       277
 EXPRESSION (advance_sel ? cdi_cnt : op_cdi_sel_i)
             -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       281
 EXPRESSION (invalid_stage_sel_o ? ({EntropyRounds {entropy_i[0]}}) : key_state_q[cdi_sel_o][0])
             ---------1---------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T3

 LINE       281
 EXPRESSION (invalid_stage_sel_o ? ({EntropyRounds {entropy_i[1]}}) : key_state_q[cdi_sel_o][1])
             ---------1---------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T3

 LINE       333
 EXPRESSION (root_key_i.creator_root_key_share0_valid && root_key_i.creator_root_key_share1_valid)
             --------------------1-------------------    --------------------2-------------------
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT1,T2,T3

 LINE       346
 EXPRESSION (op_req ? cnt[0] : '0)
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       389
 EXPRESSION ((adv_op || dis_op) ? kmac_data_i : key_state_q[cdi_sel_o])
             ---------1--------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T4

 LINE       389
 SUB-EXPRESSION (adv_op || dis_op)
                 ---1--    ---2--
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT25,T44,T45
10CoveredT1,T2,T4

 LINE       408
 EXPRESSION (op_ack | random_ack)
             ---1--   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T4
10CoveredT1,T2,T4

 LINE       408
 EXPRESSION (op_update | random_req)
             ----1----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T4
10CoveredT1,T2,T4

 LINE       433
 EXPRESSION (op_req ? op_ack : (init_o | invalid_op))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       433
 SUB-EXPRESSION (init_o | invalid_op)
                 ---1--   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T15,T16
10CoveredT1,T2,T4

 LINE       444
 EXPRESSION (op_ack & adv_req & ((~op_err)))
             ---1--   ---2---   -----3-----
-1--2--3-StatusTests
011CoveredT1,T2,T4
101CoveredT1,T2,T4
110CoveredT1,T2,T4
111CoveredT1,T2,T4

 LINE       445
 EXPRESSION (op_ack & dis_req)
             ---1--   ---2---
-1--2-StatusTests
01CoveredT25,T44,T45
10CoveredT1,T2,T4
11CoveredT25,T44,T45

 LINE       504
 EXPRESSION (op_start_i & ((~advance_sel)))
             -----1----   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T4
11CoveredT2,T15,T16

 LINE       532
 EXPRESSION (int'(cnt) == (EntropyRounds - 1))
            -----------------1----------------
-1-StatusTests
0CoveredT1,T2,T4
1UnreachableT1,T2,T4

 LINE       542
 EXPRESSION (en_i ? StCtrlInit : StCtrlWipe)
             --1-
-1-StatusTests
0CoveredT46,T47,T48
1CoveredT1,T2,T4

 LINE       552
 EXPRESSION (advance_sel ? Creator : Disable)
             -----1-----
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T4

 LINE       553
 EXPRESSION (op_start_i & ( ~ (advance_sel | disable_sel) ))
             -----1----   ----------------2----------------
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       553
 SUB-EXPRESSION (advance_sel | disable_sel)
                 -----1-----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT40,T49,T7
10CoveredT1,T2,T4

 LINE       555
 EXPRESSION (((!en_i)) || inv_state)
             ----1----    ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT50,T51,T24
10CoveredT40,T49,T7

 LINE       572
 EXPRESSION (disable_sel ? Disable : (advance_sel ? OwnerInt : Creator))
             -----1-----
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT25,T45,T7

 LINE       572
 SUB-EXPRESSION (advance_sel ? OwnerInt : Creator)
                 -----1-----
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T4

 LINE       575
 EXPRESSION (((!en_i)) || inv_state)
             ----1----    ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT16,T35,T52
10CoveredT7,T53,T42

 LINE       592
 EXPRESSION (disable_sel ? Disable : (advance_sel ? Owner : OwnerInt))
             -----1-----
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT44,T8,T54

 LINE       592
 SUB-EXPRESSION (advance_sel ? Owner : OwnerInt)
                 -----1-----
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T4

 LINE       595
 EXPRESSION (((!en_i)) || inv_state)
             ----1----    ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT17,T55,T56
10CoveredT54,T57,T58

 LINE       613
 EXPRESSION ((disable_sel | advance_sel) ? Disable : Owner)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T4

 LINE       613
 SUB-EXPRESSION (disable_sel | advance_sel)
                 -----1-----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T2,T4
10CoveredT59,T41,T60

 LINE       615
 EXPRESSION (((!en_i)) || inv_state)
             ----1----    ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT2,T36,T61
10CoveredT41,T62,T63

 LINE       617
 EXPRESSION (adv_state || dis_state)
             ----1----    ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT59,T60,T8
10CoveredT1,T4,T5

 LINE       656
 EXPRESSION (((!en_i)) || inv_state)
             ----1----    ----2----
-1--2-StatusTests
00CoveredT1,T4,T5
01CoveredT1,T34,T26
10CoveredT41,T64,T65

 LINE       730
 EXPRESSION (((|{error_o, fault_o})) ? OpDoneFail : OpDoneSuccess)
             -----------1-----------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T4

 LINE       763
 EXPRESSION ((adv_en_o & ( ~ (advance_sel | disable_sel) )) | (gen_en_o & ((~gen_op))))
             -----------------------1----------------------   ------------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT26,T66,T67
10CoveredT10,T11,T33

 LINE       763
 SUB-EXPRESSION (adv_en_o & ( ~ (advance_sel | disable_sel) ))
                 ----1---   ----------------2----------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T4
11CoveredT20,T10,T11

 LINE       763
 SUB-EXPRESSION (advance_sel | disable_sel)
                 -----1-----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T4

 LINE       763
 SUB-EXPRESSION (gen_en_o & ((~gen_op)))
                 ----1---   -----2-----
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT1,T2,T4
11CoveredT20,T26,T66

 LINE       769
 EXPRESSION 
 Number  Term
      1  ((op_ack | op_update) & invalid) ? KeyUpdateKmac : (((op_ack | op_update) & op_fault_err) ? KeyUpdateWipe : (((op_ack | op_update) & disabled) ? KeyUpdateKmac : (((op_ack | op_update) & op_err) ? KeyUpdateIdle : ((op_ack | op_update) ? KeyUpdateKmac : KeyUpdateIdle)))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T34,T35

 LINE       769
 SUB-EXPRESSION ((op_ack | op_update) & invalid)
                 ----------1---------   ---2---
-1--2-StatusTests
01CoveredT1,T2,T16
10CoveredT1,T2,T4
11CoveredT1,T34,T35

 LINE       769
 SUB-EXPRESSION (op_ack | op_update)
                 ---1--   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T4
10CoveredT1,T2,T4

 LINE       769
 SUB-EXPRESSION 
 Number  Term
      1  ((op_ack | op_update) & op_fault_err) ? KeyUpdateWipe : (((op_ack | op_update) & disabled) ? KeyUpdateKmac : (((op_ack | op_update) & op_err) ? KeyUpdateIdle : ((op_ack | op_update) ? KeyUpdateKmac : KeyUpdateIdle))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T16

 LINE       769
 SUB-EXPRESSION ((op_ack | op_update) & op_fault_err)
                 ----------1---------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T16
10CoveredT1,T2,T4
11CoveredT1,T2,T16

 LINE       769
 SUB-EXPRESSION (op_ack | op_update)
                 ---1--   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T4
10CoveredT1,T2,T4

 LINE       769
 SUB-EXPRESSION 
 Number  Term
      1  ((op_ack | op_update) & disabled) ? KeyUpdateKmac : (((op_ack | op_update) & op_err) ? KeyUpdateIdle : ((op_ack | op_update) ? KeyUpdateKmac : KeyUpdateIdle)))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       769
 SUB-EXPRESSION ((op_ack | op_update) & disabled)
                 ----------1---------   ----2---
-1--2-StatusTests
01CoveredT1,T4,T5
10CoveredT1,T2,T4
11CoveredT1,T4,T5

 LINE       769
 SUB-EXPRESSION (op_ack | op_update)
                 ---1--   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T4
10CoveredT1,T2,T4

 LINE       769
 SUB-EXPRESSION (((op_ack | op_update) & op_err) ? KeyUpdateIdle : ((op_ack | op_update) ? KeyUpdateKmac : KeyUpdateIdle))
                 ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       769
 SUB-EXPRESSION ((op_ack | op_update) & op_err)
                 ----------1---------   ---2--
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       769
 SUB-EXPRESSION (op_ack | op_update)
                 ---1--   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T4
10CoveredT1,T2,T4

 LINE       769
 SUB-EXPRESSION ((op_ack | op_update) ? KeyUpdateKmac : KeyUpdateIdle)
                 ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       769
 SUB-EXPRESSION (op_ack | op_update)
                 ---1--   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T4
10CoveredT1,T2,T4

 LINE       800
 EXPRESSION ((state_d != state_q) & (state_d inside {StCtrlRootKey, StCtrlCreatorRootKey, StCtrlOwnerIntKey, StCtrlOwnerKey}))
             ----------1---------   --------------------------------------------2--------------------------------------------
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       800
 SUB-EXPRESSION (state_d != state_q)
                ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       818
 EXPRESSION (vld_state_change_q & ((!adv_op)))
             ---------1--------   -----2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T4
11Not Covered

 LINE       820
 EXPRESSION (disabled | (initialized & ((~en_i))))
             ----1---   ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT40,T49,T7
10CoveredT1,T4,T5

 LINE       820
 SUB-EXPRESSION (initialized & ((~en_i)))
                 -----1-----   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T4
11CoveredT40,T49,T7

 LINE       820
 EXPRESSION (state_intg_err_q | state_intg_err_d)
             --------1-------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT9,T13,T14
10Not Covered

FSM Coverage for Module : keymgr_ctrl
Summary for FSM :: state_q
TotalCoveredPercent
States 11 11 100.00 (Not included in score)
Transitions 19 19 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
StCtrlCreatorRootKey 561 Covered T1,T2,T4
StCtrlDisabled 558 Covered T1,T4,T5
StCtrlEntropyReseed 510 Covered T1,T2,T4
StCtrlInit 542 Covered T1,T2,T4
StCtrlInvalid 641 Covered T1,T2,T16
StCtrlOwnerIntKey 581 Covered T1,T2,T4
StCtrlOwnerKey 601 Covered T1,T2,T4
StCtrlRandom 520 Covered T1,T2,T4
StCtrlReset 495 Covered T1,T2,T3
StCtrlRootKey 534 Covered T1,T2,T4
StCtrlWipe 508 Covered T1,T2,T16


transitions   Line No.   Covered   Tests   
StCtrlCreatorRootKey->StCtrlDisabled 578 Covered T25,T45,T68
StCtrlCreatorRootKey->StCtrlOwnerIntKey 581 Covered T1,T2,T4
StCtrlCreatorRootKey->StCtrlWipe 576 Covered T16,T35,T7
StCtrlDisabled->StCtrlWipe 657 Covered T1,T34,T41
StCtrlEntropyReseed->StCtrlRandom 520 Covered T1,T2,T4
StCtrlInit->StCtrlCreatorRootKey 561 Covered T1,T2,T4
StCtrlInit->StCtrlDisabled 558 Covered T69,T70,T68
StCtrlInit->StCtrlWipe 556 Covered T40,T49,T7
StCtrlOwnerIntKey->StCtrlDisabled 598 Covered T44,T8,T54
StCtrlOwnerIntKey->StCtrlOwnerKey 601 Covered T1,T2,T4
StCtrlOwnerIntKey->StCtrlWipe 596 Covered T17,T55,T54
StCtrlOwnerKey->StCtrlDisabled 618 Covered T1,T4,T5
StCtrlOwnerKey->StCtrlWipe 616 Covered T2,T41,T36
StCtrlRandom->StCtrlRootKey 534 Covered T1,T2,T4
StCtrlReset->StCtrlEntropyReseed 510 Covered T1,T2,T4
StCtrlReset->StCtrlWipe 508 Covered T9,T13,T71
StCtrlRootKey->StCtrlInit 542 Covered T1,T2,T4
StCtrlRootKey->StCtrlWipe 542 Covered T46,T47,T48
StCtrlWipe->StCtrlInvalid 641 Covered T1,T2,T16



Branch Coverage for Module : keymgr_ctrl
Line No.TotalCoveredPercent
Branches 97 97 100.00
TERNARY 230 4 4 100.00
TERNARY 243 3 3 100.00
TERNARY 277 2 2 100.00
TERNARY 346 2 2 100.00
TERNARY 433 2 2 100.00
TERNARY 769 6 6 100.00
TERNARY 281 2 2 100.00
TERNARY 281 2 2 100.00
IF 248 2 2 100.00
IF 261 2 2 100.00
IF 264 2 2 100.00
IF 290 2 2 100.00
CASE 355 7 7 100.00
CASE 493 39 39 100.00
IF 681 3 3 100.00
CASE 692 9 9 100.00
IF 726 4 4 100.00
IF 808 2 2 100.00
IF 895 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_ctrl.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 230 (wipe_req) ? -2-: 230 (random_req) ? -3-: 230 (init_o) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T16
0 1 - Covered T1,T2,T4
0 0 1 Covered T1,T2,T4
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 243 (prng_en_dis_inv_set) ? -2-: 243 (prng_reseed_done_i) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T4
0 1 Covered T1,T2,T4
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 277 (advance_sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 346 (op_req) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 433 (op_req) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 769 (((op_ack | op_update) & invalid)) ? -2-: 769 (((op_ack | op_update) & op_fault_err)) ? -3-: 769 (((op_ack | op_update) & disabled)) ? -4-: 769 (((op_ack | op_update) & op_err)) ? -5-: 769 ((op_ack | op_update)) ?

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T34,T35
0 1 - - - Covered T1,T2,T16
0 0 1 - - Covered T1,T4,T5
0 0 0 1 - Covered T1,T2,T4
0 0 0 0 1 Covered T1,T2,T4
0 0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 281 (invalid_stage_sel_o) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T4


LineNo. Expression -1-: 281 (invalid_stage_sel_o) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T4


LineNo. Expression -1-: 248 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 261 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 264 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 290 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 355 case (update_sel) -2-: 367 if (root_key_valid_q) -3-: 389 ((adv_op || dis_op)) ?

Branches:
-1--2--3-StatusTests
KeyUpdateRandom - - Covered T1,T2,T4
KeyUpdateRoot 1 - Covered T1,T2,T4
KeyUpdateRoot 0 - Covered T22,T50,T23
KeyUpdateKmac - 1 Covered T1,T2,T4
KeyUpdateKmac - 0 Covered T1,T2,T4
KeyUpdateWipe - - Covered T1,T2,T16
default - - Covered T1,T2,T3


LineNo. Expression -1-: 493 case (state_q) -2-: 507 if (inv_state) -3-: 509 if (advance_sel) -4-: 519 if (prng_reseed_ack_i) -5-: 532 if ((int'(cnt) == (EntropyRounds - 1))) -6-: 542 (en_i) ? -7-: 552 (advance_sel) ? -8-: 555 if (((!en_i) || inv_state)) -9-: 557 if (dis_state) -10-: 560 if (adv_state) -11-: 572 (disable_sel) ? -12-: 572 (advance_sel) ? -13-: 575 if (((!en_i) || inv_state)) -14-: 577 if (dis_state) -15-: 580 if (adv_state) -16-: 592 (disable_sel) ? -17-: 592 (advance_sel) ? -18-: 595 if (((!en_i) || inv_state)) -19-: 597 if (dis_state) -20-: 600 if (adv_state) -21-: 613 ((disable_sel | advance_sel)) ? -22-: 615 if (((!en_i) || inv_state)) -23-: 617 if ((adv_state || dis_state)) -24-: 640 if ((!op_start_i)) -25-: 656 if (((!en_i) || inv_state))

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14--15--16--17--18--19--20--21--22--23--24--25-StatusTests
StCtrlReset 1 - - - - - - - - - - - - - - - - - - - - - - - Covered T9,T13,T71
StCtrlReset 0 1 - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T4
StCtrlReset 0 0 - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
StCtrlEntropyReseed - - 1 - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T4
StCtrlEntropyReseed - - 0 - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T4
StCtrlRandom - - - 1 - - - - - - - - - - - - - - - - - - - - Unreachable T1,T2,T4
StCtrlRandom - - - 0 - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T4
StCtrlRootKey - - - - 1 - - - - - - - - - - - - - - - - - - - Covered T1,T2,T4
StCtrlRootKey - - - - 0 - - - - - - - - - - - - - - - - - - - Covered T46,T47,T48
StCtrlInit - - - - - 1 - - - - - - - - - - - - - - - - - - Covered T1,T2,T4
StCtrlInit - - - - - 0 - - - - - - - - - - - - - - - - - - Covered T1,T2,T4
StCtrlInit - - - - - - 1 - - - - - - - - - - - - - - - - - Covered T40,T49,T7
StCtrlInit - - - - - - 0 1 - - - - - - - - - - - - - - - - Covered T69,T70,T68
StCtrlInit - - - - - - 0 0 1 - - - - - - - - - - - - - - - Covered T1,T2,T4
StCtrlInit - - - - - - 0 0 0 - - - - - - - - - - - - - - - Covered T1,T2,T4
StCtrlCreatorRootKey - - - - - - - - - 1 - - - - - - - - - - - - - - Covered T25,T45,T7
StCtrlCreatorRootKey - - - - - - - - - 0 1 - - - - - - - - - - - - - Covered T1,T2,T4
StCtrlCreatorRootKey - - - - - - - - - 0 0 - - - - - - - - - - - - - Covered T1,T2,T4
StCtrlCreatorRootKey - - - - - - - - - - - 1 - - - - - - - - - - - - Covered T16,T35,T7
StCtrlCreatorRootKey - - - - - - - - - - - 0 1 - - - - - - - - - - - Covered T25,T45,T68
StCtrlCreatorRootKey - - - - - - - - - - - 0 0 1 - - - - - - - - - - Covered T1,T2,T4
StCtrlCreatorRootKey - - - - - - - - - - - 0 0 0 - - - - - - - - - - Covered T1,T2,T4
StCtrlOwnerIntKey - - - - - - - - - - - - - - 1 - - - - - - - - - Covered T44,T8,T54
StCtrlOwnerIntKey - - - - - - - - - - - - - - 0 1 - - - - - - - - Covered T1,T2,T4
StCtrlOwnerIntKey - - - - - - - - - - - - - - 0 0 - - - - - - - - Covered T1,T2,T4
StCtrlOwnerIntKey - - - - - - - - - - - - - - - - 1 - - - - - - - Covered T17,T55,T54
StCtrlOwnerIntKey - - - - - - - - - - - - - - - - 0 1 - - - - - - Covered T44,T8,T54
StCtrlOwnerIntKey - - - - - - - - - - - - - - - - 0 0 1 - - - - - Covered T1,T2,T4
StCtrlOwnerIntKey - - - - - - - - - - - - - - - - 0 0 0 - - - - - Covered T1,T2,T4
StCtrlOwnerKey - - - - - - - - - - - - - - - - - - - 1 - - - - Covered T1,T2,T4
StCtrlOwnerKey - - - - - - - - - - - - - - - - - - - 0 - - - - Covered T1,T2,T4
StCtrlOwnerKey - - - - - - - - - - - - - - - - - - - - 1 - - - Covered T2,T41,T36
StCtrlOwnerKey - - - - - - - - - - - - - - - - - - - - 0 1 - - Covered T1,T4,T5
StCtrlOwnerKey - - - - - - - - - - - - - - - - - - - - 0 0 - - Covered T1,T2,T4
StCtrlWipe - - - - - - - - - - - - - - - - - - - - - - 1 - Covered T1,T2,T16
StCtrlWipe - - - - - - - - - - - - - - - - - - - - - - 0 - Covered T1,T2,T16
StCtrlDisabled - - - - - - - - - - - - - - - - - - - - - - - 1 Covered T1,T34,T41
StCtrlDisabled - - - - - - - - - - - - - - - - - - - - - - - 0 Covered T1,T4,T5
StCtrlInvalid - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T16
default - - - - - - - - - - - - - - - - - - - - - - - - Covered T9,T13,T14


LineNo. Expression -1-: 681 if ((!rst_ni)) -2-: 683 if (update_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T16


LineNo. Expression -1-: 692 case (state_q)

Branches:
-1-StatusTests
StCtrlReset StCtrlEntropyReseed StCtrlRandom Covered T1,T2,T3
StCtrlRootKey StCtrlInit Covered T1,T2,T4
StCtrlCreatorRootKey Covered T1,T2,T4
StCtrlOwnerIntKey Covered T1,T2,T4
StCtrlOwnerKey Covered T1,T2,T4
StCtrlDisabled Covered T1,T4,T5
StCtrlWipe Covered T1,T2,T16
StCtrlInvalid Covered T1,T2,T16
default Covered T9,T13,T14


LineNo. Expression -1-: 726 if (op_done_o) -2-: 730 ((|{error_o, fault_o})) ? -3-: 731 if (op_start_i)

Branches:
-1--2--3-StatusTests
1 1 - Covered T1,T2,T4
1 0 - Covered T1,T2,T4
0 - 1 Covered T1,T2,T4
0 - 0 Covered T1,T2,T3


LineNo. Expression -1-: 808 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 895 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : keymgr_ctrl
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 11 11 100.00 10 90.91
Cover properties 0 0 0
Cover sequences 0 0 0
Total 11 11 100.00 10 90.91




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
CntZero_A 27267846 27525 0 0
DataEnDis_A 26457129 27017 0 0
DataEn_A 26457129 5946946 0 0
GeneralLegalCommands_A 28033928 37361 0 0
InitLegalCommands_A 28033928 1345580 0 0
LoadKey_A 27389377 20706223 0 0
OwnerLegalCommands_A 28033928 1625991 0 0
SameErrCnt_A 885 885 0 0
SecCmCFILinear_A 28033928 0 0 4776
StageDisableSel_A 28033928 897443 0 0
u_state_regs_A 28033928 27884921 0 0


CntZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 27267846 27525 0 0
T1 583 2 0 0
T2 22413 36 0 0
T3 930 0 0 0
T4 18717 16 0 0
T5 12919 16 0 0
T6 39681 34 0 0
T15 174786 39 0 0
T16 10814 25 0 0
T17 6064 20 0 0
T18 26108 28 0 0
T25 0 183 0 0

DataEnDis_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26457129 27017 0 0
T1 583 2 0 0
T2 22413 36 0 0
T3 930 0 0 0
T4 18717 16 0 0
T5 12919 16 0 0
T6 39681 34 0 0
T15 174786 39 0 0
T16 10814 25 0 0
T17 6064 20 0 0
T18 26108 28 0 0
T25 0 183 0 0

DataEn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 26457129 5946946 0 0
T1 583 107 0 0
T2 22413 3888 0 0
T3 930 0 0 0
T4 18717 2508 0 0
T5 12919 2052 0 0
T6 39681 12888 0 0
T15 174786 67907 0 0
T16 10814 2777 0 0
T17 6064 634 0 0
T18 26108 4218 0 0
T25 0 4919 0 0

GeneralLegalCommands_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 28033928 37361 0 0
T8 0 152 0 0
T51 2181 0 0 0
T68 94445 58 0 0
T72 0 12822 0 0
T73 0 6377 0 0
T74 0 956 0 0
T75 0 2500 0 0
T76 0 1393 0 0
T77 0 182 0 0
T78 0 58 0 0
T79 0 604 0 0
T80 4901 0 0 0
T81 25321 0 0 0
T82 15444 0 0 0
T83 2283 0 0 0
T84 6160 0 0 0
T85 3814 0 0 0
T86 5187 0 0 0
T87 86213 0 0 0

InitLegalCommands_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 28033928 1345580 0 0
T1 9289 554 0 0
T2 22413 662 0 0
T3 930 0 0 0
T4 18717 137 0 0
T5 12919 120 0 0
T6 39681 1447 0 0
T15 174786 67949 0 0
T16 10814 1804 0 0
T17 6064 263 0 0
T18 26108 286 0 0
T25 0 708 0 0

LoadKey_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 27389377 20706223 0 0
T1 9289 6219 0 0
T2 22413 15002 0 0
T3 930 0 0 0
T4 18717 15459 0 0
T5 12919 9319 0 0
T6 39681 30693 0 0
T15 174786 164455 0 0
T16 10814 6978 0 0
T17 6064 1105 0 0
T18 26108 24114 0 0
T25 0 12886 0 0

OwnerLegalCommands_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 28033928 1625991 0 0
T1 9289 642 0 0
T2 22413 409 0 0
T3 930 0 0 0
T4 18717 1773 0 0
T5 12919 1053 0 0
T6 39681 2683 0 0
T15 174786 0 0 0
T16 10814 0 0 0
T17 6064 0 0 0
T18 26108 2581 0 0
T25 0 1095 0 0
T34 0 537 0 0
T39 0 190 0 0
T88 0 187 0 0

SameErrCnt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 885 885 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

SecCmCFILinear_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 28033928 0 0 4776

StageDisableSel_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 28033928 897443 0 0
T1 9289 588 0 0
T2 22413 136 0 0
T3 930 56 0 0
T4 18717 38 0 0
T5 12919 102 0 0
T6 39681 23 0 0
T15 174786 53 0 0
T16 10814 39 0 0
T17 6064 61 0 0
T18 26108 48 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 28033928 27884921 0 0
T1 9289 9144 0 0
T2 22413 22261 0 0
T3 930 835 0 0
T4 18717 18617 0 0
T5 12919 12833 0 0
T6 39681 39584 0 0
T15 174786 174711 0 0
T16 10814 10685 0 0
T17 6064 5896 0 0
T18 26108 26008 0 0