Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3742918	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

550177

1

T1

177

T2

151

T3

171

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3932337	1			T1	504		T2	440		T3	689
values[0x0]	178956	1			T1	52		T2	47		T3	47
values[0x1]	181802	1			T1	34		T2	41		T3	59

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2549755	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1743340

1

T1

299

T2

232

T3

356

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16224	1			T2	1		T3	3		T6	7
valid_sources[0x01]	13567	1			T3	2		T5	26		T6	13
valid_sources[0x02]	17869	1			T3	6		T6	3		T15	18
valid_sources[0x03]	13679	1			T3	1		T5	9		T6	7
valid_sources[0x04]	12769	1			T3	4		T6	6		T15	20
valid_sources[0x05]	18371	1			T2	3		T3	4		T4	93
valid_sources[0x06]	13001	1			T3	4		T6	5		T15	19
valid_sources[0x07]	14422	1			T1	6		T3	1		T5	1
valid_sources[0x08]	15430	1			T3	3		T6	6		T15	23
valid_sources[0x09]	12875	1			T2	10		T3	4		T5	12
valid_sources[0x0a]	17922	1			T3	3		T5	35		T6	8
valid_sources[0x0b]	15246	1			T2	30		T3	6		T6	6
valid_sources[0x0c]	42394	1			T3	3		T5	6		T6	9
valid_sources[0x0d]	13421	1			T3	1		T5	4		T6	4
valid_sources[0x0e]	15654	1			T3	4		T5	1		T6	7
valid_sources[0x0f]	14962	1			T3	2		T5	3		T6	8
valid_sources[0x10]	13355	1			T3	3		T6	4		T15	16
valid_sources[0x11]	12573	1			T3	3		T5	14		T6	6
valid_sources[0x12]	14396	1			T3	6		T5	35		T6	8
valid_sources[0x13]	15062	1			T1	4		T2	17		T3	4
valid_sources[0x14]	17849	1			T3	2		T5	6		T15	30
valid_sources[0x15]	18389	1			T1	20		T3	3		T5	10
valid_sources[0x16]	12759	1			T1	5		T2	3		T3	2
valid_sources[0x17]	13307	1			T1	1		T3	4		T6	9
valid_sources[0x18]	14801	1			T1	3		T3	4		T5	7
valid_sources[0x19]	25270	1			T2	2		T3	3		T4	10
valid_sources[0x1a]	15197	1			T1	9		T3	8		T5	27
valid_sources[0x1b]	12808	1			T2	2		T3	2		T6	6
valid_sources[0x1c]	13140	1			T1	4		T3	3		T6	7
valid_sources[0x1d]	15048	1			T3	6		T5	18		T6	10
valid_sources[0x1e]	13623	1			T1	2		T3	4		T5	47
valid_sources[0x1f]	13739	1			T3	3		T6	7		T15	17
valid_sources[0x20]	12999	1			T3	1		T5	31		T6	3
valid_sources[0x21]	25417	1			T3	1		T5	3		T6	3
valid_sources[0x22]	12799	1			T3	1		T5	3		T6	5
valid_sources[0x23]	13419	1			T1	2		T3	4		T5	18
valid_sources[0x24]	14234	1			T1	6		T14	511		T6	4
valid_sources[0x25]	14717	1			T3	5		T5	11		T6	9
valid_sources[0x26]	51157	1			T1	1		T2	3		T3	6
valid_sources[0x27]	13109	1			T3	6		T5	16		T6	5
valid_sources[0x28]	13098	1			T1	7		T3	6		T5	36
valid_sources[0x29]	17011	1			T3	1		T6	2		T15	29
valid_sources[0x2a]	29162	1			T3	9		T5	3		T6	6
valid_sources[0x2b]	15725	1			T3	5		T4	23		T5	1
valid_sources[0x2c]	15842	1			T2	10		T3	1		T5	1
valid_sources[0x2d]	13454	1			T3	5		T6	7		T15	22
valid_sources[0x2e]	24676	1			T1	7		T3	1		T5	38
valid_sources[0x2f]	16943	1			T3	2		T4	11		T5	6
valid_sources[0x30]	14075	1			T3	5		T4	19		T6	9
valid_sources[0x31]	13037	1			T2	6		T3	1		T5	14
valid_sources[0x32]	23163	1			T3	1		T4	48		T5	20
valid_sources[0x33]	13971	1			T3	5		T4	7		T5	20
valid_sources[0x34]	15888	1			T2	2		T3	1		T5	9
valid_sources[0x35]	13372	1			T3	4		T6	14		T15	18
valid_sources[0x36]	21236	1			T1	7		T3	3		T4	21
valid_sources[0x37]	13501	1			T3	6		T5	17		T6	10
valid_sources[0x38]	19260	1			T1	2		T3	5		T4	32
valid_sources[0x39]	12932	1			T1	3		T2	20		T5	43
valid_sources[0x3a]	21094	1			T1	2		T3	1		T5	3
valid_sources[0x3b]	15125	1			T1	10		T3	2		T5	8
valid_sources[0x3c]	13288	1			T2	7		T3	2		T4	7
valid_sources[0x3d]	19158	1			T3	4		T5	25		T6	8
valid_sources[0x3e]	13650	1			T2	14		T3	2		T5	3
valid_sources[0x3f]	22787	1			T3	1		T5	2		T6	5
valid_sources[0x40]	12645	1			T3	3		T5	2		T6	4
valid_sources[0x41]	13638	1			T2	2		T3	5		T5	29
valid_sources[0x42]	26788	1			T6	3		T15	19		T16	3
valid_sources[0x43]	14836	1			T3	1		T4	12		T5	1
valid_sources[0x44]	15100	1			T3	3		T4	20		T5	11
valid_sources[0x45]	13438	1			T1	8		T3	3		T5	50
valid_sources[0x46]	14718	1			T1	4		T3	2		T5	4
valid_sources[0x47]	13343	1			T3	3		T6	2		T15	23
valid_sources[0x48]	23411	1			T2	4		T3	2		T6	5
valid_sources[0x49]	18628	1			T1	29		T3	1		T5	12
valid_sources[0x4a]	14040	1			T1	11		T3	5		T6	9
valid_sources[0x4b]	70346	1			T1	6		T2	19		T3	6
valid_sources[0x4c]	20499	1			T1	2		T3	2		T4	54
valid_sources[0x4d]	27446	1			T3	1		T6	3		T15	23
valid_sources[0x4e]	14084	1			T3	1		T6	5		T15	29
valid_sources[0x4f]	13377	1			T3	1		T4	7		T5	11
valid_sources[0x50]	15503	1			T3	1		T5	7		T6	3
valid_sources[0x51]	14041	1			T1	2		T3	9		T5	13
valid_sources[0x52]	17780	1			T6	12		T15	21		T16	5
valid_sources[0x53]	14795	1			T3	3		T5	16		T6	9
valid_sources[0x54]	13526	1			T1	3		T3	4		T6	5
valid_sources[0x55]	16402	1			T1	8		T3	1		T6	6
valid_sources[0x56]	16144	1			T1	2		T3	3		T6	9
valid_sources[0x57]	14033	1			T3	3		T6	3		T15	14
valid_sources[0x58]	13011	1			T1	29		T3	6		T6	1
valid_sources[0x59]	13475	1			T3	2		T5	4		T6	3
valid_sources[0x5a]	27906	1			T3	4		T6	6		T15	21
valid_sources[0x5b]	14029	1			T3	2		T6	3		T15	24
valid_sources[0x5c]	18771	1			T3	2		T6	7		T15	22
valid_sources[0x5d]	30568	1			T3	2		T4	8		T5	4
valid_sources[0x5e]	12887	1			T1	1		T3	2		T4	21
valid_sources[0x5f]	14433	1			T3	4		T6	9		T15	30
valid_sources[0x60]	13115	1			T1	3		T3	4		T6	6
valid_sources[0x61]	14536	1			T3	6		T5	31		T6	4
valid_sources[0x62]	13364	1			T2	5		T3	3		T5	71
valid_sources[0x63]	13571	1			T1	5		T2	3		T3	6
valid_sources[0x64]	13055	1			T3	4		T4	8		T6	12
valid_sources[0x65]	14151	1			T1	6		T2	2		T3	3
valid_sources[0x66]	17975	1			T1	19		T3	6		T5	27
valid_sources[0x67]	12788	1			T3	4		T5	28		T6	7
valid_sources[0x68]	13808	1			T1	2		T3	2		T6	4
valid_sources[0x69]	13354	1			T2	20		T3	1		T5	28
valid_sources[0x6a]	13490	1			T3	3		T6	2		T15	30
valid_sources[0x6b]	13396	1			T3	4		T6	6		T15	19
valid_sources[0x6c]	14510	1			T2	20		T3	4		T6	4
valid_sources[0x6d]	13828	1			T1	11		T3	5		T5	4
valid_sources[0x6e]	13010	1			T3	4		T5	14		T6	6
valid_sources[0x6f]	13631	1			T3	3		T5	17		T6	1
valid_sources[0x70]	13086	1			T3	2		T6	4		T15	24
valid_sources[0x71]	13802	1			T1	7		T3	3		T5	8
valid_sources[0x72]	21192	1			T3	1		T5	13		T6	3
valid_sources[0x73]	15348	1			T1	3		T3	5		T5	5
valid_sources[0x74]	13763	1			T1	11		T3	4		T4	79
valid_sources[0x75]	16299	1			T3	1		T4	95		T6	10
valid_sources[0x76]	14766	1			T2	5		T3	4		T5	5
valid_sources[0x77]	14266	1			T1	9		T2	7		T3	3
valid_sources[0x78]	14452	1			T1	9		T3	3		T5	49
valid_sources[0x79]	13131	1			T3	6		T6	5		T15	29
valid_sources[0x7a]	13358	1			T1	2		T3	3		T6	3
valid_sources[0x7b]	13246	1			T1	3		T3	2		T6	6
valid_sources[0x7c]	13947	1			T3	4		T5	9		T6	7
valid_sources[0x7d]	14356	1			T2	2		T3	5		T5	12
valid_sources[0x7e]	16254	1			T2	7		T3	3		T5	1
valid_sources[0x7f]	13817	1			T1	2		T3	4		T6	2
valid_sources[0x80]	14223	1			T2	8		T5	9		T6	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

305713

1

T1

146

T2

118

T3

135

values[0x0]

all_enables

biggest_size

128802

1

T1

20

T2

19

T3

20

values[0x1]

all_enables

biggest_size

115662

1

T1

11

T2

14

T3

16