Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4126705	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

567433

1

T1

295

T2

354

T3

233

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4320560	1			T1	669		T2	356		T3	540
values[0x0]	184973	1			T1	91		T2	145		T3	64
values[0x1]	188605	1			T1	77		T2	173		T3	62

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2805970	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1888168

1

T1

433

T2

442

T3

338

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	14615	1			T1	12		T4	1		T15	1
valid_sources[0x01]	16438	1			T4	1		T12	4		T13	2
valid_sources[0x02]	14385	1			T1	11		T3	15		T4	3
valid_sources[0x03]	23763	1			T12	1		T14	12		T15	4
valid_sources[0x04]	15602	1			T4	2		T13	2		T14	4
valid_sources[0x05]	15429	1			T3	1		T4	2		T12	5
valid_sources[0x06]	23823	1			T3	6		T4	2		T12	6
valid_sources[0x07]	15731	1			T1	4		T12	1		T13	9
valid_sources[0x08]	16847	1			T4	1		T12	9		T14	3
valid_sources[0x09]	20053	1			T2	3		T4	1		T14	7
valid_sources[0x0a]	20219	1			T4	1		T14	4		T16	12
valid_sources[0x0b]	18116	1			T2	2		T4	5		T12	7
valid_sources[0x0c]	18470	1			T2	2		T3	6		T4	1
valid_sources[0x0d]	14881	1			T1	18		T3	16		T12	1
valid_sources[0x0e]	16799	1			T1	2		T3	3		T12	1
valid_sources[0x0f]	15326	1			T2	7		T4	2		T12	6
valid_sources[0x10]	16026	1			T2	1		T4	3		T14	4
valid_sources[0x11]	15504	1			T2	3		T3	8		T4	2
valid_sources[0x12]	16732	1			T2	8		T3	18		T4	2
valid_sources[0x13]	16591	1			T2	2		T3	2		T4	2
valid_sources[0x14]	15443	1			T1	2		T2	1		T4	2
valid_sources[0x15]	16555	1			T3	1		T12	4		T14	7
valid_sources[0x16]	15780	1			T2	1		T4	3		T12	6
valid_sources[0x17]	22882	1			T2	2		T4	4		T14	5
valid_sources[0x18]	18703	1			T2	4		T12	5		T14	8
valid_sources[0x19]	15380	1			T2	3		T4	2		T12	1
valid_sources[0x1a]	16159	1			T2	3		T4	1		T13	2
valid_sources[0x1b]	19665	1			T2	1		T12	2		T13	12
valid_sources[0x1c]	24827	1			T2	7		T3	2		T4	3
valid_sources[0x1d]	18332	1			T1	5		T4	1		T12	4
valid_sources[0x1e]	15395	1			T1	11		T4	4		T12	1
valid_sources[0x1f]	15791	1			T3	19		T4	7		T12	1
valid_sources[0x20]	17659	1			T1	4		T2	6		T4	5
valid_sources[0x21]	16566	1			T4	4		T12	2		T14	2
valid_sources[0x22]	17543	1			T2	2		T4	1		T12	1
valid_sources[0x23]	18279	1			T2	25		T4	1		T12	3
valid_sources[0x24]	16764	1			T2	6		T4	2		T12	5
valid_sources[0x25]	26928	1			T3	4		T4	3		T12	1
valid_sources[0x26]	26501	1			T1	21		T3	17		T4	3
valid_sources[0x27]	18586	1			T1	6		T4	3		T13	5
valid_sources[0x28]	16293	1			T1	21		T4	2		T12	1
valid_sources[0x29]	15642	1			T2	1		T4	8		T12	3
valid_sources[0x2a]	14946	1			T1	14		T2	4		T4	3
valid_sources[0x2b]	30878	1			T2	3		T4	2		T12	1
valid_sources[0x2c]	16440	1			T2	5		T4	1		T12	5
valid_sources[0x2d]	17836	1			T4	4		T14	2		T15	3
valid_sources[0x2e]	14738	1			T2	3		T3	7		T4	1
valid_sources[0x2f]	14994	1			T2	1		T3	7		T12	1
valid_sources[0x30]	15030	1			T4	1		T14	1		T16	6
valid_sources[0x31]	16135	1			T4	4		T13	12		T14	5
valid_sources[0x32]	17613	1			T3	3		T4	3		T12	3
valid_sources[0x33]	17255	1			T1	14		T2	6		T3	3
valid_sources[0x34]	16073	1			T2	4		T3	4		T4	3
valid_sources[0x35]	17482	1			T2	6		T4	2		T12	8
valid_sources[0x36]	16267	1			T1	7		T2	6		T4	3
valid_sources[0x37]	34787	1			T2	1		T3	7		T12	1
valid_sources[0x38]	18188	1			T2	3		T3	14		T4	1
valid_sources[0x39]	15077	1			T3	16		T4	8		T13	7
valid_sources[0x3a]	18179	1			T2	4		T3	9		T4	3
valid_sources[0x3b]	15349	1			T1	1		T4	2		T13	4
valid_sources[0x3c]	18526	1			T4	4		T12	4		T13	13
valid_sources[0x3d]	18830	1			T2	6		T4	1		T12	3
valid_sources[0x3e]	17294	1			T1	6		T4	5		T12	1
valid_sources[0x3f]	23800	1			T1	7		T2	3		T4	2
valid_sources[0x40]	14946	1			T1	5		T2	5		T4	3
valid_sources[0x41]	14975	1			T4	5		T12	2		T13	10
valid_sources[0x42]	16619	1			T1	23		T2	6		T3	3
valid_sources[0x43]	15573	1			T1	3		T2	1		T4	1
valid_sources[0x44]	15901	1			T2	5		T4	1		T12	1
valid_sources[0x45]	15301	1			T2	1		T4	2		T12	7
valid_sources[0x46]	15226	1			T1	7		T3	32		T4	1
valid_sources[0x47]	16355	1			T2	2		T12	1		T13	1
valid_sources[0x48]	17875	1			T2	3		T3	6		T4	2
valid_sources[0x49]	17984	1			T1	4		T2	4		T3	7
valid_sources[0x4a]	17708	1			T12	8		T14	1		T15	1
valid_sources[0x4b]	16069	1			T1	2		T2	22		T4	2
valid_sources[0x4c]	17731	1			T2	1		T3	5		T4	4
valid_sources[0x4d]	16110	1			T1	13		T3	1		T4	4
valid_sources[0x4e]	18003	1			T2	1		T3	8		T4	1
valid_sources[0x4f]	27686	1			T2	5		T12	5		T14	10
valid_sources[0x50]	16932	1			T2	2		T4	1		T14	2
valid_sources[0x51]	26381	1			T3	1		T4	2		T12	3
valid_sources[0x52]	16012	1			T2	1		T4	2		T12	2
valid_sources[0x53]	24290	1			T1	1		T2	3		T4	4
valid_sources[0x54]	15813	1			T4	1		T12	4		T13	4
valid_sources[0x55]	18266	1			T4	2		T12	2		T14	10
valid_sources[0x56]	15746	1			T2	3		T12	6		T14	9
valid_sources[0x57]	15802	1			T4	1		T13	18		T14	1
valid_sources[0x58]	15250	1			T2	7		T4	2		T12	4
valid_sources[0x59]	21465	1			T2	8		T12	2		T14	2
valid_sources[0x5a]	15170	1			T1	5		T4	2		T14	2
valid_sources[0x5b]	20863	1			T2	4		T4	1		T12	5
valid_sources[0x5c]	16708	1			T2	1		T3	1		T4	4
valid_sources[0x5d]	15797	1			T3	4		T4	4		T12	1
valid_sources[0x5e]	15583	1			T1	7		T4	1		T12	6
valid_sources[0x5f]	16434	1			T2	5		T3	3		T4	7
valid_sources[0x60]	15789	1			T2	16		T3	1		T12	1
valid_sources[0x61]	15658	1			T4	2		T12	2		T14	7
valid_sources[0x62]	18593	1			T12	3		T14	3		T15	2
valid_sources[0x63]	15105	1			T3	5		T14	4		T15	1
valid_sources[0x64]	16278	1			T3	12		T4	2		T14	7
valid_sources[0x65]	18083	1			T2	5		T3	3		T4	2
valid_sources[0x66]	16158	1			T1	3		T4	3		T12	4
valid_sources[0x67]	14623	1			T1	25		T4	1		T12	3
valid_sources[0x68]	33794	1			T1	11		T2	2		T4	3
valid_sources[0x69]	16173	1			T2	2		T4	4		T14	2
valid_sources[0x6a]	20220	1			T2	1		T3	18		T12	1
valid_sources[0x6b]	15058	1			T2	13		T4	2		T12	3
valid_sources[0x6c]	15322	1			T2	1		T4	2		T12	1
valid_sources[0x6d]	15514	1			T4	4		T14	2		T15	1
valid_sources[0x6e]	14238	1			T2	9		T4	1		T12	2
valid_sources[0x6f]	19321	1			T2	3		T3	5		T4	1
valid_sources[0x70]	15465	1			T1	47		T2	9		T3	7
valid_sources[0x71]	17628	1			T1	13		T4	2		T12	8
valid_sources[0x72]	21915	1			T12	5		T14	16		T15	2
valid_sources[0x73]	16318	1			T4	3		T12	3		T13	13
valid_sources[0x74]	18401	1			T1	7		T2	2		T3	12
valid_sources[0x75]	18383	1			T2	2		T4	6		T12	4
valid_sources[0x76]	14988	1			T2	12		T4	3		T12	4
valid_sources[0x77]	19482	1			T4	2		T13	14		T14	10
valid_sources[0x78]	14638	1			T4	4		T12	2		T14	5
valid_sources[0x79]	22242	1			T1	9		T4	1		T12	3
valid_sources[0x7a]	17131	1			T1	8		T12	2		T14	7
valid_sources[0x7b]	15988	1			T2	2		T3	6		T4	2
valid_sources[0x7c]	17206	1			T3	1		T12	1		T14	7
valid_sources[0x7d]	16168	1			T4	4		T12	5		T14	5
valid_sources[0x7e]	22643	1			T2	7		T3	29		T12	6
valid_sources[0x7f]	15421	1			T2	9		T3	7		T12	2
valid_sources[0x80]	17783	1			T2	1		T4	2		T12	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

312532

1

T1

195

T2

117

T3

190

values[0x0]

all_enables

biggest_size

134084

1

T1

58

T2

114

T3

29

values[0x1]

all_enables

biggest_size

120817

1

T1

42

T2

123

T3

14