Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	225113	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

124477

1

T1

210

T2

1

T3

17

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	266461	1			T1	15493		T2	1		T3	1
values[0x0]	40977	1			T1	57		T2	10		T3	22
values[0x1]	42152	1			T1	56		T2	16		T3	24

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	155722	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

193868

1

T1

5291

T2

2

T3

21

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1186	1			T1	67		T6	2		T9	6
valid_sources[0x01]	1374	1			T1	41		T6	2		T9	5
valid_sources[0x02]	1255	1			T1	52		T6	2		T9	10
valid_sources[0x03]	1135	1			T1	67		T6	9		T9	11
valid_sources[0x04]	945	1			T1	78		T9	9		T7	8
valid_sources[0x05]	886	1			T1	49		T6	4		T9	13
valid_sources[0x06]	1153	1			T1	57		T6	4		T9	9
valid_sources[0x07]	1190	1			T1	76		T6	2		T9	23
valid_sources[0x08]	1166	1			T1	70		T6	5		T9	16
valid_sources[0x09]	1273	1			T1	61		T6	9		T9	11
valid_sources[0x0a]	1478	1			T1	56		T16	2		T6	7
valid_sources[0x0b]	1455	1			T1	70		T9	9		T7	5
valid_sources[0x0c]	1016	1			T1	47		T3	3		T6	3
valid_sources[0x0d]	1333	1			T1	60		T17	1		T6	10
valid_sources[0x0e]	1295	1			T1	56		T6	7		T9	8
valid_sources[0x0f]	1059	1			T1	45		T9	11		T7	5
valid_sources[0x10]	1100	1			T1	58		T19	1		T6	10
valid_sources[0x11]	1077	1			T1	72		T6	1		T9	19
valid_sources[0x12]	1167	1			T1	66		T6	2		T9	9
valid_sources[0x13]	8060	1			T1	53		T3	1		T6	3
valid_sources[0x14]	1104	1			T1	80		T6	5		T9	5
valid_sources[0x15]	1141	1			T1	60		T2	1		T6	1
valid_sources[0x16]	1248	1			T1	56		T6	10		T9	12
valid_sources[0x17]	1091	1			T1	52		T2	1		T6	1
valid_sources[0x18]	1170	1			T1	64		T6	1		T9	11
valid_sources[0x19]	1224	1			T1	68		T6	18		T9	15
valid_sources[0x1a]	1667	1			T1	67		T6	3		T9	10
valid_sources[0x1b]	2078	1			T1	77		T6	6		T9	10
valid_sources[0x1c]	1212	1			T1	74		T6	3		T9	13
valid_sources[0x1d]	9227	1			T1	69		T6	7		T9	2
valid_sources[0x1e]	995	1			T1	68		T6	3		T9	4
valid_sources[0x1f]	1276	1			T1	88		T6	1		T9	1
valid_sources[0x20]	1323	1			T1	53		T6	2		T9	8
valid_sources[0x21]	1226	1			T1	54		T6	4		T9	9
valid_sources[0x22]	1290	1			T1	66		T6	4		T9	5
valid_sources[0x23]	12882	1			T1	66		T6	5		T9	6
valid_sources[0x24]	1276	1			T1	56		T6	2		T9	15
valid_sources[0x25]	1347	1			T1	59		T6	5		T9	12
valid_sources[0x26]	1297	1			T1	68		T19	1		T6	11
valid_sources[0x27]	2413	1			T1	45		T2	2		T19	1
valid_sources[0x28]	1280	1			T1	65		T9	12		T27	1
valid_sources[0x29]	1271	1			T1	58		T6	3		T9	4
valid_sources[0x2a]	1317	1			T1	66		T6	5		T9	9
valid_sources[0x2b]	1121	1			T1	51		T6	5		T9	11
valid_sources[0x2c]	1119	1			T1	51		T6	7		T9	13
valid_sources[0x2d]	1256	1			T1	67		T6	2		T9	9
valid_sources[0x2e]	1171	1			T1	58		T17	2		T6	3
valid_sources[0x2f]	1266	1			T1	63		T19	1		T6	5
valid_sources[0x30]	1450	1			T1	63		T6	3		T9	16
valid_sources[0x31]	1271	1			T1	43		T15	13		T17	4
valid_sources[0x32]	1177	1			T1	69		T3	1		T6	7
valid_sources[0x33]	1178	1			T1	64		T6	5		T9	13
valid_sources[0x34]	1232	1			T1	63		T6	4		T9	6
valid_sources[0x35]	1257	1			T1	59		T9	9		T7	4
valid_sources[0x36]	1118	1			T1	52		T16	1		T19	1
valid_sources[0x37]	1127	1			T1	54		T2	1		T3	1
valid_sources[0x38]	1463	1			T1	48		T19	1		T6	10
valid_sources[0x39]	1095	1			T1	56		T6	5		T9	12
valid_sources[0x3a]	1470	1			T1	68		T19	1		T6	4
valid_sources[0x3b]	1245	1			T1	59		T19	1		T9	13
valid_sources[0x3c]	1319	1			T1	65		T6	1		T9	7
valid_sources[0x3d]	1192	1			T1	75		T2	3		T19	1
valid_sources[0x3e]	1167	1			T1	56		T6	5		T9	11
valid_sources[0x3f]	1020	1			T1	68		T17	1		T19	1
valid_sources[0x40]	1107	1			T1	62		T9	2		T7	6
valid_sources[0x41]	1165	1			T1	59		T19	1		T6	11
valid_sources[0x42]	1130	1			T1	57		T6	5		T9	12
valid_sources[0x43]	1098	1			T1	70		T17	1		T6	5
valid_sources[0x44]	1636	1			T1	61		T6	9		T9	9
valid_sources[0x45]	1125	1			T1	53		T6	9		T9	11
valid_sources[0x46]	1130	1			T1	55		T3	1		T17	1
valid_sources[0x47]	1450	1			T1	66		T6	3		T9	8
valid_sources[0x48]	1159	1			T1	64		T6	1		T9	6
valid_sources[0x49]	1799	1			T1	47		T5	583		T6	1
valid_sources[0x4a]	1094	1			T1	73		T3	2		T6	3
valid_sources[0x4b]	1978	1			T1	60		T6	2		T9	10
valid_sources[0x4c]	1284	1			T1	56		T19	2		T6	7
valid_sources[0x4d]	2500	1			T1	53		T4	988		T6	6
valid_sources[0x4e]	1105	1			T1	40		T6	3		T9	14
valid_sources[0x4f]	1161	1			T1	52		T6	6		T9	10
valid_sources[0x50]	1262	1			T1	60		T6	4		T9	9
valid_sources[0x51]	1181	1			T1	79		T3	2		T6	2
valid_sources[0x52]	1377	1			T1	74		T6	3		T9	7
valid_sources[0x53]	1194	1			T1	52		T19	1		T6	3
valid_sources[0x54]	1107	1			T1	55		T6	6		T9	7
valid_sources[0x55]	1173	1			T1	67		T6	3		T9	15
valid_sources[0x56]	1176	1			T1	75		T6	3		T9	11
valid_sources[0x57]	1047	1			T1	79		T6	4		T9	6
valid_sources[0x58]	1453	1			T1	56		T6	8		T9	8
valid_sources[0x59]	1129	1			T1	74		T3	1		T6	3
valid_sources[0x5a]	1062	1			T1	63		T3	1		T6	2
valid_sources[0x5b]	1263	1			T1	52		T6	2		T9	17
valid_sources[0x5c]	1130	1			T1	45		T3	1		T6	7
valid_sources[0x5d]	1519	1			T1	45		T6	4		T9	11
valid_sources[0x5e]	1337	1			T1	80		T6	5		T9	19
valid_sources[0x5f]	1240	1			T1	77		T6	2		T9	12
valid_sources[0x60]	1300	1			T1	78		T6	9		T9	5
valid_sources[0x61]	1508	1			T1	54		T2	1		T17	1
valid_sources[0x62]	1513	1			T1	52		T19	1		T6	8
valid_sources[0x63]	1343	1			T1	55		T6	4		T9	11
valid_sources[0x64]	1273	1			T1	66		T6	1		T9	16
valid_sources[0x65]	1239	1			T1	59		T6	5		T9	21
valid_sources[0x66]	1063	1			T1	64		T16	1		T6	3
valid_sources[0x67]	1173	1			T1	63		T6	4		T9	4
valid_sources[0x68]	881	1			T1	62		T3	1		T6	4
valid_sources[0x69]	1311	1			T1	61		T6	5		T9	10
valid_sources[0x6a]	1261	1			T1	65		T6	11		T9	10
valid_sources[0x6b]	1174	1			T1	71		T2	2		T6	7
valid_sources[0x6c]	2477	1			T1	74		T6	6		T9	32
valid_sources[0x6d]	1364	1			T1	53		T19	1		T6	6
valid_sources[0x6e]	1398	1			T1	59		T6	7		T9	5
valid_sources[0x6f]	1481	1			T1	54		T6	6		T9	12
valid_sources[0x70]	1213	1			T1	59		T6	2		T9	19
valid_sources[0x71]	1185	1			T1	54		T2	1		T3	1
valid_sources[0x72]	1393	1			T1	42		T6	4		T9	11
valid_sources[0x73]	1361	1			T1	66		T3	2		T19	1
valid_sources[0x74]	1285	1			T1	63		T6	1		T9	10
valid_sources[0x75]	1331	1			T1	74		T6	10		T9	3
valid_sources[0x76]	1216	1			T1	53		T6	3		T9	10
valid_sources[0x77]	1176	1			T1	59		T6	4		T9	4
valid_sources[0x78]	1385	1			T1	57		T6	1		T9	10
valid_sources[0x79]	1075	1			T1	53		T6	8		T9	18
valid_sources[0x7a]	1912	1			T1	62		T3	1		T6	4
valid_sources[0x7b]	1201	1			T1	58		T6	2		T9	16
valid_sources[0x7c]	1346	1			T1	83		T6	10		T9	5
valid_sources[0x7d]	1318	1			T1	66		T2	1		T19	1
valid_sources[0x7e]	1248	1			T1	53		T6	4		T9	12
valid_sources[0x7f]	1223	1			T1	55		T6	3		T9	10
valid_sources[0x80]	1317	1			T1	52		T6	7		T9	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

56744

1

T1

139

T16

1

T4

239

values[0x0]

all_enables

biggest_size

35077

1

T1

40

T3

9

T15

1

values[0x1]

all_enables

biggest_size

32656

1

T1

31

T2

1

T3

8