| SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
| NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| keymgr_dpe_reg_block.control_shadowed.dest_sel_shadowed_errs_cov | 100.00 | 1 | 100 | 1 | 64 | 64 |
| keymgr_dpe_reg_block.control_shadowed.operation_shadowed_errs_cov | 100.00 | 1 | 100 | 1 | 64 | 64 |
| keymgr_dpe_reg_block.control_shadowed.slot_dst_sel_shadowed_errs_cov | 100.00 | 1 | 100 | 1 | 64 | 64 |
| keymgr_dpe_reg_block.control_shadowed.slot_src_sel_shadowed_errs_cov | 100.00 | 1 | 100 | 1 | 64 | 64 |
| keymgr_dpe_reg_block.max_key_ver_shadowed.val_shadowed_errs_cov | 100.00 | 1 | 100 | 1 | 64 | 64 |
| keymgr_dpe_reg_block.reseed_interval_shadowed.val_shadowed_errs_cov | 100.00 | 1 | 100 | 1 | 64 | 64 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 2 | 0 | 2 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_storage_err | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 0 | |
| cp_update_err | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 0 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 2 | 0 | 2 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_storage_err | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 0 | |
| cp_update_err | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 0 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 2 | 0 | 2 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_storage_err | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 0 | |
| cp_update_err | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 0 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 2 | 0 | 2 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_storage_err | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 0 | |
| cp_update_err | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 0 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 2 | 0 | 2 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_storage_err | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 0 | |
| cp_update_err | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 0 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 2 | 0 | 2 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_storage_err | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 0 | |
| cp_update_err | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 0 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 1 | 0 | 1 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| storage_err | 4753 | 1 | T1 | 32 | T4 | 52 | T5 | 30 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 1 | 0 | 1 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| update_err | 38 | 1 | T49 | 1 | T50 | 1 | T51 | 2 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 1 | 0 | 1 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| storage_err | 4753 | 1 | T1 | 32 | T4 | 52 | T5 | 30 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 1 | 0 | 1 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| update_err | 52 | 1 | T48 | 1 | T49 | 2 | T50 | 1 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 1 | 0 | 1 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| storage_err | 4753 | 1 | T1 | 32 | T4 | 52 | T5 | 30 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 1 | 0 | 1 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| update_err | 38 | 1 | T48 | 2 | T49 | 1 | T50 | 1 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 1 | 0 | 1 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| storage_err | 4753 | 1 | T1 | 32 | T4 | 52 | T5 | 30 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 1 | 0 | 1 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| update_err | 49 | 1 | T50 | 1 | T51 | 1 | T61 | 2 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 1 | 0 | 1 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| storage_err | 3173 | 1 | T1 | 10 | T4 | 10 | T5 | 10 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 1 | 0 | 1 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| update_err | 78 | 1 | T49 | 4 | T50 | 1 | T51 | 2 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 1 | 0 | 1 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| storage_err | 2811 | 1 | T1 | 2 | T4 | 2 | T5 | 2 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 1 | 0 | 1 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| update_err | 70 | 1 | T48 | 2 | T49 | 2 | T61 | 3 |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |