Unified Coverage Report :: Module :: keymgr_dpe_csr_assert_fpv

Module : keymgr_dpe_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_dpe_csr_assert_0/keymgr_dpe_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_dpe_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_dpe_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.17	100.00	79.12	53.88		97.83	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_dpe_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	22	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	22	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2961387	8369	0	0
intr_enable_rd_A	2961387	2317	0	0
key_version_rd_A	2961387	1985	0	0
reseed_interval_regwen_rd_A	2961387	528	0	0
salt_0_rd_A	2961387	1941	0	0
salt_1_rd_A	2961387	1971	0	0
salt_2_rd_A	2961387	1982	0	0
salt_3_rd_A	2961387	2029	0	0
salt_4_rd_A	2961387	1804	0	0
salt_5_rd_A	2961387	2029	0	0
salt_6_rd_A	2961387	2111	0	0
salt_7_rd_A	2961387	2075	0	0
sideload_clear_rd_A	2961387	1960	0	0
slot_policy_rd_A	2961387	2772	0	0
sw_binding_0_rd_A	2961387	1963	0	0
sw_binding_1_rd_A	2961387	2056	0	0
sw_binding_2_rd_A	2961387	1960	0	0
sw_binding_3_rd_A	2961387	2066	0	0
sw_binding_4_rd_A	2961387	2014	0	0
sw_binding_5_rd_A	2961387	1953	0	0
sw_binding_6_rd_A	2961387	2145	0	0
sw_binding_7_rd_A	2961387	1988	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2961387	8369	0	0
T21	7496	3	0	0
T22	10314	601	0	0
T23	19448	2	0	0
T30	1674	138	0	0
T31	0	839	0	0
T32	0	6	0	0
T39	5315	0	0	0
T40	1802	20	0	0
T41	2040	6	0	0
T42	2337	13	0	0
T57	1755	8	0	0
T83	935	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2961387	2317	0	0
T30	1674	0	0	0
T31	0	34	0	0
T42	0	5	0	0
T53	14986	74	0	0
T54	4234	6	0	0
T55	876	0	0	0
T56	867	0	0	0
T57	1755	3	0	0
T58	0	8	0	0
T62	7899	30	0	0
T67	11977	82	0	0
T72	880	8	0	0
T83	935	9	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2961387	1985	0	0
T30	1674	0	0	0
T33	0	85	0	0
T34	0	48	0	0
T39	5315	0	0	0
T42	0	7	0	0
T53	14986	70	0	0
T54	4234	10	0	0
T55	876	0	0	0
T56	867	0	0	0
T57	1755	3	0	0
T58	0	2	0	0
T62	7899	17	0	0
T67	11977	47	0	0
T83	935	0	0	0
T84	0	27	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2961387	528	0	0
T30	1674	0	0	0
T31	0	34	0	0
T33	0	8	0	0
T38	0	11	0	0
T39	5315	0	0	0
T53	14986	23	0	0
T54	4234	7	0	0
T55	876	0	0	0
T56	867	0	0	0
T57	1755	2	0	0
T62	7899	31	0	0
T67	11977	39	0	0
T83	935	0	0	0
T84	0	25	0	0
T85	0	12	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2961387	1941	0	0
T30	1674	0	0	0
T33	0	83	0	0
T34	0	43	0	0
T39	5315	0	0	0
T42	0	3	0	0
T53	14986	85	0	0
T54	4234	6	0	0
T55	876	0	0	0
T56	867	0	0	0
T57	1755	2	0	0
T62	7899	48	0	0
T67	11977	43	0	0
T83	935	0	0	0
T84	0	22	0	0
T85	0	9	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2961387	1971	0	0
T30	1674	0	0	0
T31	0	10	0	0
T33	0	65	0	0
T34	0	46	0	0
T39	5315	0	0	0
T53	14986	94	0	0
T54	4234	17	0	0
T55	876	0	0	0
T56	867	0	0	0
T57	1755	1	0	0
T58	0	1	0	0
T62	7899	19	0	0
T67	11977	50	0	0
T83	935	0	0	0
T84	0	11	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2961387	1982	0	0
T30	1674	0	0	0
T31	0	4	0	0
T33	0	98	0	0
T34	0	25	0	0
T39	5315	0	0	0
T42	0	5	0	0
T53	14986	68	0	0
T54	4234	13	0	0
T55	876	0	0	0
T56	867	0	0	0
T57	1755	8	0	0
T62	7899	88	0	0
T67	11977	63	0	0
T83	935	0	0	0
T84	0	15	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2961387	2029	0	0
T30	1674	0	0	0
T31	0	9	0	0
T33	0	89	0	0
T34	0	37	0	0
T39	5315	0	0	0
T42	0	3	0	0
T53	14986	84	0	0
T54	4234	9	0	0
T55	876	0	0	0
T56	867	0	0	0
T57	1755	6	0	0
T62	7899	66	0	0
T67	11977	57	0	0
T83	935	0	0	0
T84	0	20	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2961387	1804	0	0
T30	1674	0	0	0
T31	0	18	0	0
T33	0	89	0	0
T34	0	39	0	0
T39	5315	0	0	0
T53	14986	62	0	0
T54	4234	13	0	0
T55	876	0	0	0
T56	867	0	0	0
T57	1755	1	0	0
T58	0	3	0	0
T62	7899	29	0	0
T67	11977	66	0	0
T83	935	0	0	0
T84	0	4	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2961387	2029	0	0
T30	1674	0	0	0
T31	0	27	0	0
T33	0	83	0	0
T34	0	52	0	0
T39	5315	0	0	0
T42	0	9	0	0
T53	14986	80	0	0
T54	4234	5	0	0
T55	876	0	0	0
T56	867	0	0	0
T57	1755	6	0	0
T62	7899	72	0	0
T67	11977	56	0	0
T83	935	0	0	0
T84	0	24	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2961387	2111	0	0
T30	1674	0	0	0
T31	0	11	0	0
T33	0	95	0	0
T34	0	37	0	0
T39	5315	0	0	0
T53	14986	91	0	0
T54	4234	9	0	0
T55	876	0	0	0
T56	867	0	0	0
T57	1755	10	0	0
T58	0	10	0	0
T62	7899	41	0	0
T67	11977	61	0	0
T83	935	0	0	0
T84	0	18	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2961387	2075	0	0
T30	1674	0	0	0
T31	0	12	0	0
T33	0	73	0	0
T34	0	46	0	0
T39	5315	0	0	0
T42	0	5	0	0
T53	14986	66	0	0
T54	4234	11	0	0
T55	876	0	0	0
T56	867	0	0	0
T57	1755	3	0	0
T62	7899	20	0	0
T67	11977	74	0	0
T83	935	0	0	0
T84	0	22	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2961387	1960	0	0
T30	1674	0	0	0
T31	0	8	0	0
T33	0	97	0	0
T39	5315	0	0	0
T42	0	12	0	0
T53	14986	91	0	0
T54	4234	12	0	0
T55	876	0	0	0
T56	867	0	0	0
T57	1755	8	0	0
T58	0	4	0	0
T62	7899	30	0	0
T67	11977	29	0	0
T83	935	0	0	0
T84	0	13	0	0

slot_policy_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2961387	2772	0	0
T30	1674	0	0	0
T31	0	21	0	0
T33	0	169	0	0
T34	0	71	0	0
T39	5315	0	0	0
T53	14986	141	0	0
T54	4234	11	0	0
T55	876	0	0	0
T56	867	0	0	0
T57	1755	0	0	0
T58	0	8	0	0
T62	7899	61	0	0
T67	11977	70	0	0
T83	935	0	0	0
T84	0	17	0	0
T85	0	14	0	0

sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2961387	1963	0	0
T30	1674	0	0	0
T31	0	15	0	0
T33	0	64	0	0
T34	0	39	0	0
T39	5315	0	0	0
T53	14986	82	0	0
T54	4234	16	0	0
T55	876	0	0	0
T56	867	0	0	0
T57	1755	9	0	0
T58	0	2	0	0
T62	7899	59	0	0
T67	11977	47	0	0
T83	935	0	0	0
T84	0	13	0	0

sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2961387	2056	0	0
T30	1674	0	0	0
T33	0	73	0	0
T34	0	54	0	0
T39	5315	0	0	0
T53	14986	89	0	0
T54	4234	16	0	0
T55	876	0	0	0
T56	867	0	0	0
T57	1755	3	0	0
T58	0	7	0	0
T62	7899	18	0	0
T67	11977	55	0	0
T83	935	0	0	0
T84	0	18	0	0
T85	0	14	0	0

sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2961387	1960	0	0
T30	1674	0	0	0
T33	0	77	0	0
T34	0	34	0	0
T39	5315	0	0	0
T53	14986	82	0	0
T54	4234	11	0	0
T55	876	0	0	0
T56	867	0	0	0
T57	1755	1	0	0
T58	0	4	0	0
T62	7899	28	0	0
T67	11977	42	0	0
T83	935	0	0	0
T84	0	27	0	0
T85	0	3	0	0

sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2961387	2066	0	0
T30	1674	0	0	0
T31	0	21	0	0
T33	0	79	0	0
T34	0	29	0	0
T36	0	2	0	0
T39	5315	0	0	0
T53	14986	95	0	0
T54	4234	16	0	0
T55	876	0	0	0
T56	867	0	0	0
T57	1755	9	0	0
T62	7899	38	0	0
T67	11977	65	0	0
T83	935	0	0	0
T84	0	27	0	0

sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2961387	2014	0	0
T30	1674	0	0	0
T31	0	18	0	0
T33	0	87	0	0
T34	0	37	0	0
T39	5315	0	0	0
T53	14986	61	0	0
T54	4234	9	0	0
T55	876	0	0	0
T56	867	0	0	0
T57	1755	9	0	0
T58	0	1	0	0
T62	7899	41	0	0
T67	11977	64	0	0
T83	935	0	0	0
T84	0	40	0	0

sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2961387	1953	0	0
T30	1674	0	0	0
T31	0	20	0	0
T33	0	81	0	0
T34	0	50	0	0
T39	5315	0	0	0
T53	14986	58	0	0
T54	4234	13	0	0
T55	876	0	0	0
T56	867	0	0	0
T57	1755	7	0	0
T62	7899	46	0	0
T67	11977	47	0	0
T83	935	0	0	0
T84	0	46	0	0
T85	0	8	0	0

sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2961387	2145	0	0
T30	1674	0	0	0
T31	0	9	0	0
T33	0	81	0	0
T34	0	38	0	0
T39	5315	0	0	0
T42	0	1	0	0
T53	14986	82	0	0
T54	4234	15	0	0
T55	876	0	0	0
T56	867	0	0	0
T57	1755	15	0	0
T62	7899	20	0	0
T67	11977	62	0	0
T83	935	0	0	0
T84	0	17	0	0

sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2961387	1988	0	0
T30	1674	0	0	0
T33	0	62	0	0
T34	0	36	0	0
T39	5315	0	0	0
T53	14986	79	0	0
T54	4234	15	0	0
T55	876	0	0	0
T56	867	0	0	0
T57	1755	1	0	0
T58	0	2	0	0
T62	7899	71	0	0
T67	11977	68	0	0
T83	935	0	0	0
T84	0	32	0	0
T85	0	26	0	0