509f2f46b9| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | keymgr_dpe_smoke | 35.700s | 5.644ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | keymgr_dpe_csr_hw_reset | 1.360s | 164.645us | 5 | 5 | 100.00 |
| V1 | csr_rw | keymgr_dpe_csr_rw | 1.370s | 48.757us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | keymgr_dpe_csr_bit_bash | 11.630s | 886.386us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | keymgr_dpe_csr_aliasing | 9.020s | 1.218ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | keymgr_dpe_csr_mem_rw_with_rand_reset | 1.710s | 59.292us | 19 | 20 | 95.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | keymgr_dpe_csr_rw | 1.370s | 48.757us | 20 | 20 | 100.00 |
| keymgr_dpe_csr_aliasing | 9.020s | 1.218ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 104 | 105 | 99.05 | |||
| V2 | intr_test | keymgr_dpe_intr_test | 0.850s | 10.197us | 50 | 50 | 100.00 |
| V2 | alert_test | keymgr_dpe_alert_test | 1.030s | 64.770us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | keymgr_dpe_tl_errors | 6.100s | 184.423us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | keymgr_dpe_tl_errors | 6.100s | 184.423us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | keymgr_dpe_csr_hw_reset | 1.360s | 164.645us | 5 | 5 | 100.00 |
| keymgr_dpe_csr_rw | 1.370s | 48.757us | 20 | 20 | 100.00 | ||
| keymgr_dpe_csr_aliasing | 9.020s | 1.218ms | 5 | 5 | 100.00 | ||
| keymgr_dpe_same_csr_outstanding | 3.310s | 703.462us | 19 | 20 | 95.00 | ||
| V2 | tl_d_partial_access | keymgr_dpe_csr_hw_reset | 1.360s | 164.645us | 5 | 5 | 100.00 |
| keymgr_dpe_csr_rw | 1.370s | 48.757us | 20 | 20 | 100.00 | ||
| keymgr_dpe_csr_aliasing | 9.020s | 1.218ms | 5 | 5 | 100.00 | ||
| keymgr_dpe_same_csr_outstanding | 3.310s | 703.462us | 19 | 20 | 95.00 | ||
| V2 | TOTAL | 139 | 140 | 99.29 | |||
| V2S | tl_intg_err | keymgr_dpe_sec_cm | 41.120s | 1.927ms | 5 | 5 | 100.00 |
| keymgr_dpe_tl_intg_err | 8.310s | 894.842us | 20 | 20 | 100.00 | ||
| V2S | shadow_reg_update_error | keymgr_dpe_shadow_reg_errors | 3.830s | 533.206us | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | keymgr_dpe_shadow_reg_errors | 3.830s | 533.206us | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | keymgr_dpe_shadow_reg_errors | 3.830s | 533.206us | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | keymgr_dpe_shadow_reg_errors | 3.830s | 533.206us | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | keymgr_dpe_shadow_reg_errors_with_csr_rw | 10.900s | 466.523us | 20 | 20 | 100.00 |
| V2S | prim_count_check | keymgr_dpe_sec_cm | 41.120s | 1.927ms | 5 | 5 | 100.00 |
| V2S | prim_fsm_check | keymgr_dpe_sec_cm | 41.120s | 1.927ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 65 | 65 | 100.00 | |||
| V3 | stress_all_with_rand_reset | keymgr_dpe_stress_all_with_rand_reset | 0.800s | 6.446us | 0 | 50 | 0.00 |
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| Unmapped tests | keymgr_dpe_stress_all | 0.740s | 0 | 50 | 0.00 | ||
| TOTAL | 308 | 410 | 75.12 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 0 | 0.00 |
| V1 | 6 | 6 | 5 | 83.33 |
| V2 | 4 | 4 | 3 | 75.00 |
| V2S | 4 | 4 | 4 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 73.67 | 97.17 | 89.51 | 57.52 | 61.54 | 93.92 | 98.34 | 17.67 |
UVM_WARNING [BDTYP] Cannot create an object of type 'keymgr_dpe_stress_all_vseq' because it is not registered with the factory. has 100 failures:
0.keymgr_dpe_stress_all_with_rand_reset.66232203
Line 253, in log /container/opentitan-public/scratch/os_regression/keymgr_dpe-sim-vcs/0.keymgr_dpe_stress_all_with_rand_reset/latest/run.log
UVM_WARNING @ 5865715 ps: [BDTYP] Cannot create an object of type 'keymgr_dpe_stress_all_vseq' because it is not registered with the factory.
UVM_INFO @ 5865715 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
1.keymgr_dpe_stress_all_with_rand_reset.1056526163
Line 253, in log /container/opentitan-public/scratch/os_regression/keymgr_dpe-sim-vcs/1.keymgr_dpe_stress_all_with_rand_reset/latest/run.log
UVM_WARNING @ 1447859 ps: [BDTYP] Cannot create an object of type 'keymgr_dpe_stress_all_vseq' because it is not registered with the factory.
UVM_INFO @ 1447859 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
... and 48 more failures.
0.keymgr_dpe_stress_all.2311655468
Line 249, in log /container/opentitan-public/scratch/os_regression/keymgr_dpe-sim-vcs/0.keymgr_dpe_stress_all/latest/run.log
UVM_WARNING @ 0 ps: [BDTYP] Cannot create an object of type 'keymgr_dpe_stress_all_vseq' because it is not registered with the factory.
UVM_INFO @ 0 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
1.keymgr_dpe_stress_all.1200551019
Line 249, in log /container/opentitan-public/scratch/os_regression/keymgr_dpe-sim-vcs/1.keymgr_dpe_stress_all/latest/run.log
UVM_WARNING @ 0 ps: [BDTYP] Cannot create an object of type 'keymgr_dpe_stress_all_vseq' because it is not registered with the factory.
UVM_INFO @ 0 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
... and 48 more failures.
UVM_ERROR (cip_base_vseq.sv:248) [keymgr_dpe_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
2.keymgr_dpe_same_csr_outstanding.3586055623
Line 254, in log /container/opentitan-public/scratch/os_regression/keymgr_dpe-sim-vcs/2.keymgr_dpe_same_csr_outstanding/latest/run.log
UVM_ERROR @ 14501996 ps: (cip_base_vseq.sv:248) [uvm_test_top.env.virtual_sequencer.keymgr_dpe_common_vseq] Check failed masked_data == exp_data (256 [0x100] vs 0 [0x0]) addr 0xe0fc97d0 read out mismatch
UVM_INFO @ 14501996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: keymgr_dpe_reg_block.debug reset value: * has 1 failures:
2.keymgr_dpe_csr_mem_rw_with_rand_reset.802515488
Line 271, in log /container/opentitan-public/scratch/os_regression/keymgr_dpe-sim-vcs/2.keymgr_dpe_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 16246450 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (256 [0x100] vs 0 [0x0]) Regname: keymgr_dpe_reg_block.debug reset value: 0x0
UVM_INFO @ 16246450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---