KEYMGR_DPE Simulation Results

Saturday June 08 2024 19:02:20 UTC

GitHub Revision: `8dab2b7626`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 4247883128

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_dpe_smoke	6.854m	52.114ms	48	50	96.00
V1	csr_hw_reset	keymgr_dpe_csr_hw_reset	1.070s	104.193us	5	5	100.00
V1	csr_rw	keymgr_dpe_csr_rw	1.420s	30.462us	20	20	100.00
V1	csr_bit_bash	keymgr_dpe_csr_bit_bash	17.040s	575.743us	5	5	100.00
V1	csr_aliasing	keymgr_dpe_csr_aliasing	5.440s	310.534us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_dpe_csr_mem_rw_with_rand_reset	1.940s	76.442us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_dpe_csr_rw	1.420s	30.462us	20	20	100.00
		keymgr_dpe_csr_aliasing	5.440s	310.534us	5	5	100.00
V1		TOTAL			103	105	98.10
V2	intr_test	keymgr_dpe_intr_test	0.940s	16.478us	50	50	100.00
V2	alert_test	keymgr_dpe_alert_test	0.950s	111.485us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_dpe_tl_errors	5.590s	626.927us	20	20	100.00
V2	tl_d_illegal_access	keymgr_dpe_tl_errors	5.590s	626.927us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_dpe_csr_hw_reset	1.070s	104.193us	5	5	100.00
		keymgr_dpe_csr_rw	1.420s	30.462us	20	20	100.00
		keymgr_dpe_csr_aliasing	5.440s	310.534us	5	5	100.00
		keymgr_dpe_same_csr_outstanding	3.310s	766.847us	20	20	100.00
V2	tl_d_partial_access	keymgr_dpe_csr_hw_reset	1.070s	104.193us	5	5	100.00
		keymgr_dpe_csr_rw	1.420s	30.462us	20	20	100.00
		keymgr_dpe_csr_aliasing	5.440s	310.534us	5	5	100.00
		keymgr_dpe_same_csr_outstanding	3.310s	766.847us	20	20	100.00
V2		TOTAL			140	140	100.00
V2S	tl_intg_err	keymgr_dpe_sec_cm	22.070s	3.180ms	5	5	100.00
		keymgr_dpe_tl_intg_err	8.110s	3.448ms	20	20	100.00
V2S	shadow_reg_update_error	keymgr_dpe_shadow_reg_errors	5.300s	353.384us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_dpe_shadow_reg_errors	5.300s	353.384us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_dpe_shadow_reg_errors	5.300s	353.384us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_dpe_shadow_reg_errors	5.300s	353.384us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_dpe_shadow_reg_errors_with_csr_rw	9.480s	326.703us	20	20	100.00
V2S	prim_count_check	keymgr_dpe_sec_cm	22.070s	3.180ms	5	5	100.00
V2S	prim_fsm_check	keymgr_dpe_sec_cm	22.070s	3.180ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	keymgr_dpe_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			308	310	99.35

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	5	83.33
V2	4	4	4	100.00
V2S	4	4	4	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
76.26	97.60	90.64	57.52	76.92	94.97	98.34	17.82

Failure Buckets

UVM_ERROR (keymgr_dpe_scoreboard.sv:564) scoreboard [scoreboard] After a disable kmac sideload key was not presevedexp * vs. act *

has 2 failures:

Test keymgr_dpe_smoke has 2 failures.

17.keymgr_dpe_smoke.2627989193
Line 2518, in log /container/opentitan-public/scratch/os_regression/keymgr_dpe-sim-vcs/17.keymgr_dpe_smoke/latest/run.log

  UVM_ERROR @ 950666897 ps: (keymgr_dpe_scoreboard.sv:564) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] After a disable kmac sideload key was not presevedexp 'hd3bec2f04d517f7071a3727cb277a6e9d38d741a0839e556ee9d04b7e656b69e8fdd955d75bcd4803bf138102735b003605b98559abab43b1756bc3209f88afe vs. act 'h0
  UVM_INFO @ 950666897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

33.keymgr_dpe_smoke.1970830007
Line 2594, in log /container/opentitan-public/scratch/os_regression/keymgr_dpe-sim-vcs/33.keymgr_dpe_smoke/latest/run.log

  UVM_ERROR @ 639372870 ps: (keymgr_dpe_scoreboard.sv:564) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] After a disable kmac sideload key was not presevedexp 'h88a6ca2d520677bc8caf3bd4d4e2d19d6e79b28a1bb230777dd19ee8241559a0874b5673b984113b3c2ec399e778d2dfb40ecdf26a745c6b491af0060076408f vs. act 'h0
  UVM_INFO @ 639372870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---