Unified Coverage Report :: Group :: keymgr_dpe_env_pkg::keymgr_dpe_sw_input_cg_wrap::keymgr_dpe_sw_input_cg

Group : keymgr_dpe_env_pkg::keymgr_dpe_sw_input_cg_wrap::keymgr_dpe_sw_input_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
68.37	7.47	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_dpe_env_0.1/keymgr_dpe_env_cov.sv

19 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
salt_1	0.00	1	100	1	64	64
salt_2	0.00	1	100	1	64	64
salt_3	0.00	1	100	1	64	64
salt_4	0.00	1	100	1	64	64
salt_5	0.00	1	100	1	64	64
salt_6	0.00	1	100	1	64	64
salt_7	0.00	1	100	1	64	64
sw_binding_1	0.00	1	100	1	64	64
sw_binding_2	0.00	1	100	1	64	64
sw_binding_3	0.00	1	100	1	64	64
sw_binding_4	0.00	1	100	1	64	64
sw_binding_5	0.00	1	100	1	64	64
sw_binding_6	0.00	1	100	1	64	64
sw_binding_7	0.00	1	100	1	64	64
key_version	3.06	1	100	1	64	64
salt_0	3.06	1	100	1	64	64
start	3.06	1	100	1	64	64
max_key_ver_shadowed	66.33	1	100	1	64	64
sw_binding_0	66.33	1	100	1	64	64

---

Group Instance : salt_1

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
0.00	1	100	1	64	64

---

Summary for Group Instance salt_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	34	34	0	0.00
Crosses	64	64	0	0.00

Variables for Group Instance salt_1

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
regwen_cp	2	2	0	0.00	100	1	1	2
sw_input_cp	32	32	0	0.00	100	1	1	32

Crosses for Group Instance salt_1

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_input_x_regwen_cr	64	64	0	0.00	100	1	1	0

---

Group Instance : salt_2

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
0.00	1	100	1	64	64

---

Summary for Group Instance salt_2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	34	34	0	0.00
Crosses	64	64	0	0.00

Variables for Group Instance salt_2

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
regwen_cp	2	2	0	0.00	100	1	1	2
sw_input_cp	32	32	0	0.00	100	1	1	32

Crosses for Group Instance salt_2

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_input_x_regwen_cr	64	64	0	0.00	100	1	1	0

---

Group Instance : salt_3

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
0.00	1	100	1	64	64

---

Summary for Group Instance salt_3

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	34	34	0	0.00
Crosses	64	64	0	0.00

Variables for Group Instance salt_3

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
regwen_cp	2	2	0	0.00	100	1	1	2
sw_input_cp	32	32	0	0.00	100	1	1	32

Crosses for Group Instance salt_3

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_input_x_regwen_cr	64	64	0	0.00	100	1	1	0

---

Group Instance : salt_4

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
0.00	1	100	1	64	64

---

Summary for Group Instance salt_4

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	34	34	0	0.00
Crosses	64	64	0	0.00

Variables for Group Instance salt_4

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
regwen_cp	2	2	0	0.00	100	1	1	2
sw_input_cp	32	32	0	0.00	100	1	1	32

Crosses for Group Instance salt_4

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_input_x_regwen_cr	64	64	0	0.00	100	1	1	0

---

Group Instance : salt_5

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
0.00	1	100	1	64	64

---

Summary for Group Instance salt_5

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	34	34	0	0.00
Crosses	64	64	0	0.00

Variables for Group Instance salt_5

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
regwen_cp	2	2	0	0.00	100	1	1	2
sw_input_cp	32	32	0	0.00	100	1	1	32

Crosses for Group Instance salt_5

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_input_x_regwen_cr	64	64	0	0.00	100	1	1	0

---

Group Instance : salt_6

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
0.00	1	100	1	64	64

---

Summary for Group Instance salt_6

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	34	34	0	0.00
Crosses	64	64	0	0.00

Variables for Group Instance salt_6

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
regwen_cp	2	2	0	0.00	100	1	1	2
sw_input_cp	32	32	0	0.00	100	1	1	32

Crosses for Group Instance salt_6

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_input_x_regwen_cr	64	64	0	0.00	100	1	1	0

---

Group Instance : salt_7

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
0.00	1	100	1	64	64

---

Summary for Group Instance salt_7

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	34	34	0	0.00
Crosses	64	64	0	0.00

Variables for Group Instance salt_7

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
regwen_cp	2	2	0	0.00	100	1	1	2
sw_input_cp	32	32	0	0.00	100	1	1	32

Crosses for Group Instance salt_7

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_input_x_regwen_cr	64	64	0	0.00	100	1	1	0

---

Group Instance : sw_binding_1

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
0.00	1	100	1	64	64

---

Summary for Group Instance sw_binding_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	34	34	0	0.00
Crosses	64	64	0	0.00

Variables for Group Instance sw_binding_1

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
regwen_cp	2	2	0	0.00	100	1	1	2
sw_input_cp	32	32	0	0.00	100	1	1	32

Crosses for Group Instance sw_binding_1

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_input_x_regwen_cr	64	64	0	0.00	100	1	1	0

---

Group Instance : sw_binding_2

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
0.00	1	100	1	64	64

---

Summary for Group Instance sw_binding_2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	34	34	0	0.00
Crosses	64	64	0	0.00

Variables for Group Instance sw_binding_2

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
regwen_cp	2	2	0	0.00	100	1	1	2
sw_input_cp	32	32	0	0.00	100	1	1	32

Crosses for Group Instance sw_binding_2

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_input_x_regwen_cr	64	64	0	0.00	100	1	1	0

---

Group Instance : sw_binding_3

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
0.00	1	100	1	64	64

---

Summary for Group Instance sw_binding_3

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	34	34	0	0.00
Crosses	64	64	0	0.00

Variables for Group Instance sw_binding_3

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
regwen_cp	2	2	0	0.00	100	1	1	2
sw_input_cp	32	32	0	0.00	100	1	1	32

Crosses for Group Instance sw_binding_3

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_input_x_regwen_cr	64	64	0	0.00	100	1	1	0

---

Group Instance : sw_binding_4

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
0.00	1	100	1	64	64

---

Summary for Group Instance sw_binding_4

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	34	34	0	0.00
Crosses	64	64	0	0.00

Variables for Group Instance sw_binding_4

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
regwen_cp	2	2	0	0.00	100	1	1	2
sw_input_cp	32	32	0	0.00	100	1	1	32

Crosses for Group Instance sw_binding_4

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_input_x_regwen_cr	64	64	0	0.00	100	1	1	0

---

Group Instance : sw_binding_5

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
0.00	1	100	1	64	64

---

Summary for Group Instance sw_binding_5

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	34	34	0	0.00
Crosses	64	64	0	0.00

Variables for Group Instance sw_binding_5

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
regwen_cp	2	2	0	0.00	100	1	1	2
sw_input_cp	32	32	0	0.00	100	1	1	32

Crosses for Group Instance sw_binding_5

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_input_x_regwen_cr	64	64	0	0.00	100	1	1	0

---

Group Instance : sw_binding_6

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
0.00	1	100	1	64	64

---

Summary for Group Instance sw_binding_6

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	34	34	0	0.00
Crosses	64	64	0	0.00

Variables for Group Instance sw_binding_6

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
regwen_cp	2	2	0	0.00	100	1	1	2
sw_input_cp	32	32	0	0.00	100	1	1	32

Crosses for Group Instance sw_binding_6

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_input_x_regwen_cr	64	64	0	0.00	100	1	1	0

---

Group Instance : sw_binding_7

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
0.00	1	100	1	64	64

---

Summary for Group Instance sw_binding_7

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	34	34	0	0.00
Crosses	64	64	0	0.00

Variables for Group Instance sw_binding_7

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
regwen_cp	2	2	0	0.00	100	1	1	2
sw_input_cp	32	32	0	0.00	100	1	1	32

Crosses for Group Instance sw_binding_7

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_input_x_regwen_cr	64	64	0	0.00	100	1	1	0

---

Group Instance : key_version

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
3.06	1	100	1	64	64

---

Summary for Group Instance key_version

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	34	32	2	5.88
Crosses	64	63	1	1.56

Variables for Group Instance key_version

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
regwen_cp	2	1	1	50.00	100	1	1	2
sw_input_cp	32	31	1	3.12	100	1	1	32

Crosses for Group Instance key_version

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_input_x_regwen_cr	64	63	1	1.56	100	1	1	0

---

Group Instance : salt_0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
3.06	1	100	1	64	64

---

Summary for Group Instance salt_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	34	32	2	5.88
Crosses	64	63	1	1.56

Variables for Group Instance salt_0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
regwen_cp	2	1	1	50.00	100	1	1	2
sw_input_cp	32	31	1	3.12	100	1	1	32

Crosses for Group Instance salt_0

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_input_x_regwen_cr	64	63	1	1.56	100	1	1	0

---

Group Instance : start

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
3.06	1	100	1	64	64

---

Summary for Group Instance start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	34	32	2	5.88
Crosses	64	63	1	1.56

Variables for Group Instance start

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
regwen_cp	2	1	1	50.00	100	1	1	2
sw_input_cp	32	31	1	3.12	100	1	1	32

Crosses for Group Instance start

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_input_x_regwen_cr	64	63	1	1.56	100	1	1	0

---

Group Instance : max_key_ver_shadowed

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
66.33	1	100	1	64	64

---

Summary for Group Instance max_key_ver_shadowed

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	34	1	33	97.06
Crosses	64	32	32	50.00

Variables for Group Instance max_key_ver_shadowed

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
regwen_cp	2	1	1	50.00	100	1	1	2
sw_input_cp	32	0	32	100.00	100	1	1	32

Crosses for Group Instance max_key_ver_shadowed

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_input_x_regwen_cr	64	32	32	50.00	100	1	1	0

---

Group Instance : sw_binding_0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
66.33	1	100	1	64	64

---

Summary for Group Instance sw_binding_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	34	1	33	97.06
Crosses	64	32	32	50.00

Variables for Group Instance sw_binding_0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
regwen_cp	2	1	1	50.00	100	1	1	2
sw_input_cp	32	0	32	100.00	100	1	1	32

Crosses for Group Instance sw_binding_0

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_input_x_regwen_cr	64	32	32	50.00	100	1	1	0

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for regwen_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	32	0	0.00

Automatically Generated Bins for sw_input_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0:134217727] - auto[4160749568:4294967295]]	--	--	32

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	64	0	0.00	64

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	64

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for regwen_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	32	0	0.00

Automatically Generated Bins for sw_input_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0:134217727] - auto[4160749568:4294967295]]	--	--	32

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	64	0	0.00	64

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	64

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for regwen_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	32	0	0.00

Automatically Generated Bins for sw_input_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0:134217727] - auto[4160749568:4294967295]]	--	--	32

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	64	0	0.00	64

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	64

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for regwen_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	32	0	0.00

Automatically Generated Bins for sw_input_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0:134217727] - auto[4160749568:4294967295]]	--	--	32

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	64	0	0.00	64

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	64

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for regwen_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	32	0	0.00

Automatically Generated Bins for sw_input_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0:134217727] - auto[4160749568:4294967295]]	--	--	32

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	64	0	0.00	64

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	64

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for regwen_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	32	0	0.00

Automatically Generated Bins for sw_input_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0:134217727] - auto[4160749568:4294967295]]	--	--	32

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	64	0	0.00	64

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	64

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for regwen_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	32	0	0.00

Automatically Generated Bins for sw_input_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0:134217727] - auto[4160749568:4294967295]]	--	--	32

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	64	0	0.00	64

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	64

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for regwen_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	32	0	0.00

Automatically Generated Bins for sw_input_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0:134217727] - auto[4160749568:4294967295]]	--	--	32

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	64	0	0.00	64

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	64

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for regwen_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	32	0	0.00

Automatically Generated Bins for sw_input_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0:134217727] - auto[4160749568:4294967295]]	--	--	32

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	64	0	0.00	64

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	64

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for regwen_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	32	0	0.00

Automatically Generated Bins for sw_input_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0:134217727] - auto[4160749568:4294967295]]	--	--	32

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	64	0	0.00	64

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	64

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for regwen_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	32	0	0.00

Automatically Generated Bins for sw_input_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0:134217727] - auto[4160749568:4294967295]]	--	--	32

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	64	0	0.00	64

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	64

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for regwen_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	32	0	0.00

Automatically Generated Bins for sw_input_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0:134217727] - auto[4160749568:4294967295]]	--	--	32

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	64	0	0.00	64

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	64

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for regwen_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	32	0	0.00

Automatically Generated Bins for sw_input_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0:134217727] - auto[4160749568:4294967295]]	--	--	32

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	64	0	0.00	64

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	64

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for regwen_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	32	0	0.00

Automatically Generated Bins for sw_input_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0:134217727] - auto[4160749568:4294967295]]	--	--	32

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	64	0	0.00	64

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	64

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for regwen_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

810

1

T4

26

T5

19

T6

18

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	31	1	3.12

Automatically Generated Bins for sw_input_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	--	--	31

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0:134217727]

810

1

T4

26

T5

19

T6

18

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	63	1	1.56	63

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Element holes

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	*	--	--	62

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0:134217727]]	[auto[1]]	0	1	1

Covered bins

sw_input_cp

regwen_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0:134217727]

auto[0]

810

1

T4

26

T5

19

T6

18

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for regwen_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

810

1

T4

26

T5

19

T6

18

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	31	1	3.12

Automatically Generated Bins for sw_input_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	--	--	31

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0:134217727]

810

1

T4

26

T5

19

T6

18

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	63	1	1.56	63

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Element holes

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	*	--	--	62

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0:134217727]]	[auto[1]]	0	1	1

Covered bins

sw_input_cp

regwen_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0:134217727]

auto[0]

810

1

T4

26

T5

19

T6

18

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for regwen_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1170

1

T4

34

T5

27

T6

26

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	31	1	3.12

Automatically Generated Bins for sw_input_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	--	--	31

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0:134217727]

1170

1

T4

34

T5

27

T6

26

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	63	1	1.56	63

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Element holes

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	*	--	--	62

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0:134217727]]	[auto[1]]	0	1	1

Covered bins

sw_input_cp

regwen_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0:134217727]

auto[0]

1170

1

T4

34

T5

27

T6

26

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for regwen_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

500

1

T4

10

T5

10

T6

10

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	18	1			T4	4		T11	2		T16	2
auto[134217728:268435455]	22	1			T5	2		T12	4		T31	4
auto[268435456:402653183]	10	1			T10	2		T26	2		T107	2
auto[402653184:536870911]	12	1			T35	2		T40	2		T108	2
auto[536870912:671088639]	8	1			T4	2		T28	2		T121	2
auto[671088640:805306367]	24	1			T11	2		T16	2		T111	2
auto[805306368:939524095]	24	1			T10	2		T13	2		T106	2
auto[939524096:1073741823]	16	1			T5	2		T6	2		T11	2
auto[1073741824:1207959551]	20	1			T10	2		T28	2		T120	2
auto[1207959552:1342177279]	24	1			T6	2		T10	2		T25	2
auto[1342177280:1476395007]	18	1			T14	2		T25	2		T27	2
auto[1476395008:1610612735]	8	1			T26	2		T27	2		T113	2
auto[1610612736:1744830463]	20	1			T5	2		T11	2		T13	2
auto[1744830464:1879048191]	18	1			T4	2		T12	4		T30	2
auto[1879048192:2013265919]	8	1			T6	2		T11	2		T122	2
auto[2013265920:2147483647]	8	1			T6	2		T26	2		T29	2
auto[2147483648:2281701375]	10	1			T30	2		T35	2		T38	2
auto[2281701376:2415919103]	14	1			T28	2		T30	2		T106	2
auto[2415919104:2550136831]	28	1			T10	2		T26	2		T104	2
auto[2550136832:2684354559]	6	1			T29	2		T112	2		T117	2
auto[2684354560:2818572287]	14	1			T13	2		T16	2		T27	2
auto[2818572288:2952790015]	16	1			T4	2		T111	2		T35	2
auto[2952790016:3087007743]	18	1			T5	2		T111	2		T32	2
auto[3087007744:3221225471]	16	1			T14	2		T15	2		T26	2
auto[3221225472:3355443199]	10	1			T14	2		T25	2		T27	2
auto[3355443200:3489660927]	20	1			T30	2		T32	2		T120	2
auto[3489660928:3623878655]	16	1			T13	2		T30	2		T35	2
auto[3623878656:3758096383]	16	1			T6	2		T14	2		T31	2
auto[3758096384:3892314111]	28	1			T12	2		T15	4		T25	2
auto[3892314112:4026531839]	10	1			T104	2		T123	2		T116	2
auto[4026531840:4160749567]	10	1			T5	2		T13	2		T105	2
auto[4160749568:4294967295]	10	1			T15	2		T16	2		T29	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	32	32	50.00	32

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Element holes

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[0]]	--	--	32

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[1]	18	1			T4	4		T11	2		T16	2
auto[134217728:268435455]	auto[1]	22	1			T5	2		T12	4		T31	4
auto[268435456:402653183]	auto[1]	10	1			T10	2		T26	2		T107	2
auto[402653184:536870911]	auto[1]	12	1			T35	2		T40	2		T108	2
auto[536870912:671088639]	auto[1]	8	1			T4	2		T28	2		T121	2
auto[671088640:805306367]	auto[1]	24	1			T11	2		T16	2		T111	2
auto[805306368:939524095]	auto[1]	24	1			T10	2		T13	2		T106	2
auto[939524096:1073741823]	auto[1]	16	1			T5	2		T6	2		T11	2
auto[1073741824:1207959551]	auto[1]	20	1			T10	2		T28	2		T120	2
auto[1207959552:1342177279]	auto[1]	24	1			T6	2		T10	2		T25	2
auto[1342177280:1476395007]	auto[1]	18	1			T14	2		T25	2		T27	2
auto[1476395008:1610612735]	auto[1]	8	1			T26	2		T27	2		T113	2
auto[1610612736:1744830463]	auto[1]	20	1			T5	2		T11	2		T13	2
auto[1744830464:1879048191]	auto[1]	18	1			T4	2		T12	4		T30	2
auto[1879048192:2013265919]	auto[1]	8	1			T6	2		T11	2		T122	2
auto[2013265920:2147483647]	auto[1]	8	1			T6	2		T26	2		T29	2
auto[2147483648:2281701375]	auto[1]	10	1			T30	2		T35	2		T38	2
auto[2281701376:2415919103]	auto[1]	14	1			T28	2		T30	2		T106	2
auto[2415919104:2550136831]	auto[1]	28	1			T10	2		T26	2		T104	2
auto[2550136832:2684354559]	auto[1]	6	1			T29	2		T112	2		T117	2
auto[2684354560:2818572287]	auto[1]	14	1			T13	2		T16	2		T27	2
auto[2818572288:2952790015]	auto[1]	16	1			T4	2		T111	2		T35	2
auto[2952790016:3087007743]	auto[1]	18	1			T5	2		T111	2		T32	2
auto[3087007744:3221225471]	auto[1]	16	1			T14	2		T15	2		T26	2
auto[3221225472:3355443199]	auto[1]	10	1			T14	2		T25	2		T27	2
auto[3355443200:3489660927]	auto[1]	20	1			T30	2		T32	2		T120	2
auto[3489660928:3623878655]	auto[1]	16	1			T13	2		T30	2		T35	2
auto[3623878656:3758096383]	auto[1]	16	1			T6	2		T14	2		T31	2
auto[3758096384:3892314111]	auto[1]	28	1			T12	2		T15	4		T25	2
auto[3892314112:4026531839]	auto[1]	10	1			T104	2		T123	2		T116	2
auto[4026531840:4160749567]	auto[1]	10	1			T5	2		T13	2		T105	2
auto[4160749568:4294967295]	auto[1]	10	1			T15	2		T16	2		T29	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for regwen_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

250

1

T4

5

T5

5

T6

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	9	1			T16	3		T124	1		T123	1
auto[134217728:268435455]	7	1			T27	2		T30	1		T32	1
auto[268435456:402653183]	8	1			T12	1		T120	1		T35	1
auto[402653184:536870911]	7	1			T6	1		T14	1		T26	1
auto[536870912:671088639]	13	1			T10	1		T26	1		T32	2
auto[671088640:805306367]	5	1			T38	1		T122	1		T116	1
auto[805306368:939524095]	9	1			T13	1		T31	1		T35	1
auto[939524096:1073741823]	9	1			T4	1		T11	1		T111	1
auto[1073741824:1207959551]	2	1			T12	1		T26	1		-	-
auto[1207959552:1342177279]	9	1			T11	1		T16	1		T111	1
auto[1342177280:1476395007]	8	1			T4	1		T6	1		T12	1
auto[1476395008:1610612735]	8	1			T27	1		T30	1		T120	1
auto[1610612736:1744830463]	10	1			T4	1		T5	1		T12	1
auto[1744830464:1879048191]	10	1			T10	1		T12	1		T14	1
auto[1879048192:2013265919]	6	1			T111	1		T29	1		T38	2
auto[2013265920:2147483647]	4	1			T14	1		T28	1		T109	1
auto[2147483648:2281701375]	7	1			T10	1		T25	1		T28	1
auto[2281701376:2415919103]	11	1			T4	1		T5	1		T6	1
auto[2415919104:2550136831]	5	1			T11	1		T13	1		T30	1
auto[2550136832:2684354559]	7	1			T15	1		T26	1		T40	1
auto[2684354560:2818572287]	2	1			T124	1		T122	1		-	-
auto[2818572288:2952790015]	5	1			T111	1		T28	1		T124	1
auto[2952790016:3087007743]	7	1			T10	2		T11	1		T40	1
auto[3087007744:3221225471]	7	1			T5	1		T25	1		T111	1
auto[3221225472:3355443199]	11	1			T6	1		T14	1		T28	1
auto[3355443200:3489660927]	13	1			T28	1		T30	1		T120	1
auto[3489660928:3623878655]	9	1			T25	1		T35	1		T118	1
auto[3623878656:3758096383]	9	1			T26	1		T120	1		T104	1
auto[3758096384:3892314111]	7	1			T6	1		T15	1		T104	1
auto[3892314112:4026531839]	9	1			T5	1		T13	2		T15	1
auto[4026531840:4160749567]	9	1			T5	1		T11	1		T29	1
auto[4160749568:4294967295]	8	1			T4	1		T25	1		T27	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	32	32	50.00	32

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Element holes

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[0]]	--	--	32

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[1]	9	1			T16	3		T124	1		T123	1
auto[134217728:268435455]	auto[1]	7	1			T27	2		T30	1		T32	1
auto[268435456:402653183]	auto[1]	8	1			T12	1		T120	1		T35	1
auto[402653184:536870911]	auto[1]	7	1			T6	1		T14	1		T26	1
auto[536870912:671088639]	auto[1]	13	1			T10	1		T26	1		T32	2
auto[671088640:805306367]	auto[1]	5	1			T38	1		T122	1		T116	1
auto[805306368:939524095]	auto[1]	9	1			T13	1		T31	1		T35	1
auto[939524096:1073741823]	auto[1]	9	1			T4	1		T11	1		T111	1
auto[1073741824:1207959551]	auto[1]	2	1			T12	1		T26	1		-	-
auto[1207959552:1342177279]	auto[1]	9	1			T11	1		T16	1		T111	1
auto[1342177280:1476395007]	auto[1]	8	1			T4	1		T6	1		T12	1
auto[1476395008:1610612735]	auto[1]	8	1			T27	1		T30	1		T120	1
auto[1610612736:1744830463]	auto[1]	10	1			T4	1		T5	1		T12	1
auto[1744830464:1879048191]	auto[1]	10	1			T10	1		T12	1		T14	1
auto[1879048192:2013265919]	auto[1]	6	1			T111	1		T29	1		T38	2
auto[2013265920:2147483647]	auto[1]	4	1			T14	1		T28	1		T109	1
auto[2147483648:2281701375]	auto[1]	7	1			T10	1		T25	1		T28	1
auto[2281701376:2415919103]	auto[1]	11	1			T4	1		T5	1		T6	1
auto[2415919104:2550136831]	auto[1]	5	1			T11	1		T13	1		T30	1
auto[2550136832:2684354559]	auto[1]	7	1			T15	1		T26	1		T40	1
auto[2684354560:2818572287]	auto[1]	2	1			T124	1		T122	1		-	-
auto[2818572288:2952790015]	auto[1]	5	1			T111	1		T28	1		T124	1
auto[2952790016:3087007743]	auto[1]	7	1			T10	2		T11	1		T40	1
auto[3087007744:3221225471]	auto[1]	7	1			T5	1		T25	1		T111	1
auto[3221225472:3355443199]	auto[1]	11	1			T6	1		T14	1		T28	1
auto[3355443200:3489660927]	auto[1]	13	1			T28	1		T30	1		T120	1
auto[3489660928:3623878655]	auto[1]	9	1			T25	1		T35	1		T118	1
auto[3623878656:3758096383]	auto[1]	9	1			T26	1		T120	1		T104	1
auto[3758096384:3892314111]	auto[1]	7	1			T6	1		T15	1		T104	1
auto[3892314112:4026531839]	auto[1]	9	1			T5	1		T13	2		T15	1
auto[4026531840:4160749567]	auto[1]	9	1			T5	1		T11	1		T29	1
auto[4160749568:4294967295]	auto[1]	8	1			T4	1		T25	1		T27	1