Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	189675	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

125113

1

T1

6

T2

6

T3

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	232724	1			T1	1		T2	1		T3	1
values[0x0]	40412	1			T1	12		T2	15		T3	10
values[0x1]	41652	1			T1	9		T2	9		T3	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	131862	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

182926

1

T1

7

T2

7

T3

6

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1254	1			T4	7		T5	48		T6	55
valid_sources[0x01]	3620	1			T5	59		T6	40		T12	1
valid_sources[0x02]	1032	1			T5	56		T6	66		T12	5
valid_sources[0x03]	1199	1			T5	45		T6	45		T10	7
valid_sources[0x04]	1045	1			T5	51		T6	60		T12	4
valid_sources[0x05]	1213	1			T4	36		T5	45		T6	56
valid_sources[0x06]	1172	1			T4	13		T5	64		T6	29
valid_sources[0x07]	1130	1			T2	3		T3	1		T5	47
valid_sources[0x08]	893	1			T4	4		T5	59		T6	48
valid_sources[0x09]	1973	1			T5	49		T6	20		T10	2
valid_sources[0x0a]	971	1			T5	32		T6	24		T10	9
valid_sources[0x0b]	1095	1			T5	65		T6	30		T10	5
valid_sources[0x0c]	1157	1			T4	6		T5	54		T6	23
valid_sources[0x0d]	974	1			T5	57		T6	42		T10	1
valid_sources[0x0e]	1187	1			T4	120		T5	41		T6	40
valid_sources[0x0f]	1052	1			T4	10		T5	71		T6	20
valid_sources[0x10]	893	1			T4	4		T5	54		T6	14
valid_sources[0x11]	846	1			T21	1		T4	19		T5	44
valid_sources[0x12]	944	1			T5	48		T6	21		T12	3
valid_sources[0x13]	856	1			T5	29		T6	59		T10	6
valid_sources[0x14]	964	1			T5	34		T6	13		T12	4
valid_sources[0x15]	1096	1			T5	46		T10	6		T12	1
valid_sources[0x16]	973	1			T3	1		T4	2		T5	62
valid_sources[0x17]	854	1			T4	7		T5	36		T6	9
valid_sources[0x18]	941	1			T4	20		T5	60		T6	36
valid_sources[0x19]	1038	1			T3	1		T5	44		T6	69
valid_sources[0x1a]	988	1			T5	48		T6	26		T12	1
valid_sources[0x1b]	906	1			T4	27		T5	47		T6	14
valid_sources[0x1c]	993	1			T2	1		T4	21		T5	61
valid_sources[0x1d]	994	1			T4	11		T5	73		T6	9
valid_sources[0x1e]	1088	1			T5	39		T6	21		T10	6
valid_sources[0x1f]	1023	1			T4	2		T5	47		T6	23
valid_sources[0x20]	1044	1			T3	1		T5	68		T6	69
valid_sources[0x21]	1113	1			T3	1		T4	9		T5	51
valid_sources[0x22]	976	1			T5	42		T6	7		T12	1
valid_sources[0x23]	922	1			T5	37		T6	22		T10	5
valid_sources[0x24]	1273	1			T3	1		T4	13		T5	40
valid_sources[0x25]	921	1			T5	59		T6	21		T12	2
valid_sources[0x26]	879	1			T5	35		T6	47		T10	11
valid_sources[0x27]	1078	1			T4	8		T5	37		T6	105
valid_sources[0x28]	1042	1			T4	36		T5	64		T6	13
valid_sources[0x29]	1547	1			T5	56		T6	52		T12	2
valid_sources[0x2a]	1181	1			T4	77		T5	63		T6	27
valid_sources[0x2b]	1033	1			T4	1		T5	28		T6	57
valid_sources[0x2c]	965	1			T4	20		T5	49		T6	36
valid_sources[0x2d]	1083	1			T4	21		T5	50		T6	11
valid_sources[0x2e]	869	1			T4	1		T5	43		T6	14
valid_sources[0x2f]	904	1			T5	53		T6	10		T10	1
valid_sources[0x30]	835	1			T4	34		T5	36		T6	17
valid_sources[0x31]	888	1			T21	1		T5	38		T6	12
valid_sources[0x32]	1237	1			T4	16		T5	55		T6	38
valid_sources[0x33]	1217	1			T5	63		T6	32		T10	2
valid_sources[0x34]	1025	1			T4	16		T5	44		T6	48
valid_sources[0x35]	937	1			T5	52		T6	34		T10	5
valid_sources[0x36]	1076	1			T5	50		T6	20		T10	1
valid_sources[0x37]	884	1			T5	60		T6	24		T12	4
valid_sources[0x38]	1039	1			T5	60		T6	36		T14	3
valid_sources[0x39]	993	1			T21	1		T4	30		T5	52
valid_sources[0x3a]	1020	1			T3	1		T21	1		T5	43
valid_sources[0x3b]	825	1			T5	39		T6	42		T10	4
valid_sources[0x3c]	971	1			T5	64		T6	44		T10	2
valid_sources[0x3d]	948	1			T4	33		T5	51		T6	5
valid_sources[0x3e]	1038	1			T4	13		T5	35		T6	8
valid_sources[0x3f]	961	1			T4	95		T5	32		T6	53
valid_sources[0x40]	812	1			T3	1		T5	43		T6	24
valid_sources[0x41]	1083	1			T4	2		T5	44		T6	5
valid_sources[0x42]	974	1			T21	1		T4	48		T5	40
valid_sources[0x43]	944	1			T4	9		T5	69		T6	8
valid_sources[0x44]	897	1			T4	2		T5	31		T6	17
valid_sources[0x45]	1104	1			T21	1		T4	8		T5	51
valid_sources[0x46]	1017	1			T5	45		T6	32		T10	15
valid_sources[0x47]	1201	1			T5	65		T6	39		T10	1
valid_sources[0x48]	1039	1			T4	96		T5	53		T6	2
valid_sources[0x49]	943	1			T5	47		T6	36		T10	4
valid_sources[0x4a]	945	1			T4	1		T5	67		T6	4
valid_sources[0x4b]	1047	1			T5	51		T6	15		T10	19
valid_sources[0x4c]	1008	1			T4	35		T5	75		T6	37
valid_sources[0x4d]	844	1			T5	72		T6	13		T12	1
valid_sources[0x4e]	954	1			T21	1		T5	63		T6	31
valid_sources[0x4f]	967	1			T4	21		T5	46		T6	5
valid_sources[0x50]	1059	1			T21	1		T4	111		T5	66
valid_sources[0x51]	985	1			T5	60		T6	58		T12	4
valid_sources[0x52]	1018	1			T2	1		T4	20		T5	44
valid_sources[0x53]	1005	1			T5	39		T6	19		T10	3
valid_sources[0x54]	9637	1			T5	42		T6	26		T10	7
valid_sources[0x55]	1294	1			T5	40		T6	74		T10	1
valid_sources[0x56]	1013	1			T2	4		T4	12		T5	45
valid_sources[0x57]	841	1			T21	1		T4	21		T5	54
valid_sources[0x58]	1112	1			T4	44		T5	36		T6	41
valid_sources[0x59]	920	1			T3	1		T5	51		T6	15
valid_sources[0x5a]	4237	1			T2	1		T4	8		T5	52
valid_sources[0x5b]	16757	1			T4	15		T5	40		T6	3
valid_sources[0x5c]	1121	1			T4	17		T5	46		T6	48
valid_sources[0x5d]	871	1			T4	22		T5	36		T6	25
valid_sources[0x5e]	909	1			T5	47		T6	30		T10	5
valid_sources[0x5f]	2129	1			T5	50		T6	20		T12	2
valid_sources[0x60]	931	1			T4	6		T5	42		T6	53
valid_sources[0x61]	972	1			T4	7		T5	56		T6	30
valid_sources[0x62]	1106	1			T5	64		T6	90		T14	6
valid_sources[0x63]	988	1			T4	22		T5	42		T6	21
valid_sources[0x64]	1103	1			T4	3		T5	45		T6	24
valid_sources[0x65]	852	1			T5	61		T6	10		T10	5
valid_sources[0x66]	1000	1			T4	35		T5	51		T6	26
valid_sources[0x67]	1004	1			T5	40		T6	31		T14	4
valid_sources[0x68]	1040	1			T5	57		T6	48		T10	1
valid_sources[0x69]	1050	1			T3	1		T5	41		T6	42
valid_sources[0x6a]	929	1			T2	1		T5	34		T6	68
valid_sources[0x6b]	916	1			T4	16		T5	75		T6	28
valid_sources[0x6c]	908	1			T21	2		T5	61		T6	11
valid_sources[0x6d]	1016	1			T5	54		T6	36		T10	9
valid_sources[0x6e]	1038	1			T4	39		T5	48		T6	14
valid_sources[0x6f]	1000	1			T4	14		T5	39		T6	89
valid_sources[0x70]	793	1			T5	51		T6	45		T17	2
valid_sources[0x71]	960	1			T5	61		T6	34		T10	7
valid_sources[0x72]	1639	1			T5	56		T6	92		T10	3
valid_sources[0x73]	1035	1			T5	57		T6	18		T12	5
valid_sources[0x74]	1029	1			T4	13		T5	53		T6	108
valid_sources[0x75]	1066	1			T5	73		T6	96		T10	3
valid_sources[0x76]	1122	1			T5	54		T6	9		T10	1
valid_sources[0x77]	833	1			T2	2		T5	55		T6	18
valid_sources[0x78]	1014	1			T5	44		T6	72		T10	6
valid_sources[0x79]	1039	1			T21	4		T4	16		T5	45
valid_sources[0x7a]	921	1			T4	16		T5	54		T6	7
valid_sources[0x7b]	1481	1			T2	5		T4	22		T5	49
valid_sources[0x7c]	1009	1			T4	9		T5	57		T6	74
valid_sources[0x7d]	927	1			T4	10		T5	54		T6	15
valid_sources[0x7e]	984	1			T5	44		T6	75		T12	3
valid_sources[0x7f]	935	1			T4	24		T5	45		T6	50
valid_sources[0x80]	1054	1			T5	43		T6	34		T10	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

57057

1

T1

1

T3

1

T4

365

values[0x0]

all_enables

biggest_size

35095

1

T1

5

T2

2

T3

3

values[0x1]

all_enables

biggest_size

32961

1

T2

4

T3

2

T21

2