Unified Coverage Report :: Module :: keymgr_dpe_csr_assert_fpv

Module : keymgr_dpe_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_dpe_csr_assert_0/keymgr_dpe_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_dpe_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_dpe_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.17	100.00	79.12	53.88		97.83	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_dpe_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	22	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	22	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2588164	9693	0	0
intr_enable_rd_A	2588164	2411	0	0
key_version_rd_A	2588164	1944	0	0
reseed_interval_regwen_rd_A	2588164	613	0	0
salt_0_rd_A	2588164	2118	0	0
salt_1_rd_A	2588164	2074	0	0
salt_2_rd_A	2588164	2033	0	0
salt_3_rd_A	2588164	1987	0	0
salt_4_rd_A	2588164	2010	0	0
salt_5_rd_A	2588164	1896	0	0
salt_6_rd_A	2588164	2031	0	0
salt_7_rd_A	2588164	2015	0	0
sideload_clear_rd_A	2588164	1954	0	0
slot_policy_rd_A	2588164	2620	0	0
sw_binding_0_rd_A	2588164	1994	0	0
sw_binding_1_rd_A	2588164	1999	0	0
sw_binding_2_rd_A	2588164	2231	0	0
sw_binding_3_rd_A	2588164	2086	0	0
sw_binding_4_rd_A	2588164	1933	0	0
sw_binding_5_rd_A	2588164	2024	0	0
sw_binding_6_rd_A	2588164	1935	0	0
sw_binding_7_rd_A	2588164	2118	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2588164	9693	0	0
T22	2590	19	0	0
T23	5466	220	0	0
T24	2262	144	0	0
T43	17598	4	0	0
T44	8061	358	0	0
T45	2215	165	0	0
T46	6394	490	0	0
T47	13498	702	0	0
T48	0	334	0	0
T49	0	244	0	0
T51	957	0	0	0
T52	1104	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2588164	2411	0	0
T47	13498	7	0	0
T48	13355	9	0	0
T52	1104	0	0	0
T53	1307	0	0	0
T56	12305	52	0	0
T58	1128	0	0	0
T59	0	11	0	0
T61	0	56	0	0
T64	0	29	0	0
T69	12160	30	0	0
T72	5254	0	0	0
T73	1241	0	0	0
T74	5801	10	0	0
T95	0	7	0	0
T96	0	18	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2588164	1944	0	0
T47	13498	12	0	0
T48	13355	0	0	0
T50	0	61	0	0
T52	1104	0	0	0
T53	1307	0	0	0
T56	12305	50	0	0
T58	1128	0	0	0
T61	0	29	0	0
T64	0	34	0	0
T69	12160	29	0	0
T72	5254	0	0	0
T73	1241	0	0	0
T74	5801	2	0	0
T81	0	82	0	0
T84	0	31	0	0
T97	0	4	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2588164	613	0	0
T47	13498	5	0	0
T48	13355	7	0	0
T52	1104	0	0	0
T53	1307	0	0	0
T56	12305	6	0	0
T58	1128	0	0	0
T61	0	5	0	0
T64	0	27	0	0
T69	12160	10	0	0
T72	5254	0	0	0
T73	1241	0	0	0
T74	5801	6	0	0
T94	0	19	0	0
T97	0	20	0	0
T98	0	93	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2588164	2118	0	0
T47	13498	4	0	0
T48	13355	22	0	0
T50	0	21	0	0
T52	1104	0	0	0
T53	1307	0	0	0
T56	12305	26	0	0
T58	1128	0	0	0
T61	0	27	0	0
T64	0	22	0	0
T69	12160	31	0	0
T72	5254	0	0	0
T73	1241	0	0	0
T74	5801	10	0	0
T81	0	84	0	0
T97	0	14	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2588164	2074	0	0
T47	13498	5	0	0
T48	13355	11	0	0
T50	0	30	0	0
T52	1104	0	0	0
T53	1307	0	0	0
T56	12305	41	0	0
T58	1128	0	0	0
T61	0	37	0	0
T64	0	33	0	0
T69	12160	23	0	0
T72	5254	0	0	0
T73	1241	0	0	0
T74	5801	13	0	0
T81	0	82	0	0
T97	0	10	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2588164	2033	0	0
T47	13498	4	0	0
T48	13355	13	0	0
T50	0	34	0	0
T52	1104	0	0	0
T53	1307	0	0	0
T56	12305	43	0	0
T58	1128	0	0	0
T61	0	51	0	0
T64	0	28	0	0
T69	12160	34	0	0
T72	5254	0	0	0
T73	1241	0	0	0
T74	5801	7	0	0
T81	0	77	0	0
T97	0	10	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2588164	1987	0	0
T47	13498	16	0	0
T48	13355	12	0	0
T50	0	44	0	0
T52	1104	0	0	0
T53	1307	0	0	0
T56	12305	40	0	0
T58	1128	0	0	0
T61	0	86	0	0
T64	0	26	0	0
T69	12160	53	0	0
T72	5254	0	0	0
T73	1241	0	0	0
T74	5801	3	0	0
T81	0	93	0	0
T97	0	13	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2588164	2010	0	0
T48	13355	7	0	0
T49	4872	0	0	0
T50	0	52	0	0
T56	12305	27	0	0
T58	1128	0	0	0
T59	1138	0	0	0
T60	2588	0	0	0
T61	8632	39	0	0
T62	1212	0	0	0
T64	0	16	0	0
T69	12160	50	0	0
T74	5801	8	0	0
T81	0	88	0	0
T84	0	30	0	0
T97	0	10	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2588164	1896	0	0
T47	13498	10	0	0
T48	13355	1	0	0
T50	0	34	0	0
T52	1104	0	0	0
T53	1307	0	0	0
T56	12305	14	0	0
T58	1128	0	0	0
T61	0	39	0	0
T64	0	29	0	0
T69	12160	37	0	0
T72	5254	0	0	0
T73	1241	0	0	0
T74	5801	7	0	0
T81	0	82	0	0
T97	0	9	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2588164	2031	0	0
T47	13498	11	0	0
T48	13355	18	0	0
T50	0	26	0	0
T52	1104	0	0	0
T53	1307	0	0	0
T56	12305	59	0	0
T58	1128	0	0	0
T61	0	30	0	0
T64	0	20	0	0
T69	12160	51	0	0
T72	5254	0	0	0
T73	1241	0	0	0
T74	5801	14	0	0
T81	0	84	0	0
T97	0	10	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2588164	2015	0	0
T47	13498	8	0	0
T48	13355	4	0	0
T50	0	47	0	0
T52	1104	0	0	0
T53	1307	0	0	0
T56	12305	39	0	0
T58	1128	0	0	0
T61	0	31	0	0
T64	0	28	0	0
T69	12160	42	0	0
T72	5254	0	0	0
T73	1241	0	0	0
T74	5801	7	0	0
T81	0	68	0	0
T97	0	10	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2588164	1954	0	0
T48	13355	1	0	0
T49	4872	0	0	0
T50	0	43	0	0
T56	12305	48	0	0
T58	1128	0	0	0
T59	1138	0	0	0
T60	2588	0	0	0
T61	8632	37	0	0
T62	1212	0	0	0
T64	0	14	0	0
T69	12160	70	0	0
T74	5801	14	0	0
T81	0	89	0	0
T84	0	27	0	0
T97	0	10	0	0

slot_policy_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2588164	2620	0	0
T48	13355	16	0	0
T49	4872	0	0	0
T50	0	91	0	0
T56	12305	72	0	0
T58	1128	0	0	0
T59	1138	0	0	0
T60	2588	0	0	0
T61	8632	24	0	0
T62	1212	0	0	0
T64	0	32	0	0
T69	12160	69	0	0
T74	5801	6	0	0
T81	0	155	0	0
T84	0	57	0	0
T97	0	17	0	0

sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2588164	1994	0	0
T47	13498	9	0	0
T48	13355	25	0	0
T50	0	48	0	0
T52	1104	0	0	0
T53	1307	0	0	0
T56	12305	68	0	0
T58	1128	0	0	0
T61	0	55	0	0
T64	0	17	0	0
T69	12160	41	0	0
T72	5254	0	0	0
T73	1241	0	0	0
T74	5801	3	0	0
T81	0	74	0	0
T97	0	17	0	0

sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2588164	1999	0	0
T47	13498	1	0	0
T48	13355	6	0	0
T50	0	34	0	0
T52	1104	0	0	0
T53	1307	0	0	0
T56	12305	40	0	0
T58	1128	0	0	0
T61	0	46	0	0
T64	0	29	0	0
T69	12160	46	0	0
T72	5254	0	0	0
T73	1241	0	0	0
T74	5801	13	0	0
T81	0	86	0	0
T97	0	12	0	0

sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2588164	2231	0	0
T49	4872	0	0	0
T50	0	40	0	0
T56	12305	54	0	0
T61	8632	78	0	0
T62	1212	0	0	0
T63	2735	0	0	0
T64	7555	32	0	0
T69	12160	45	0	0
T74	5801	12	0	0
T81	0	83	0	0
T84	0	43	0	0
T94	0	6	0	0
T97	0	2	0	0
T99	781	0	0	0
T100	7338	0	0	0

sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2588164	2086	0	0
T47	13498	18	0	0
T48	13355	29	0	0
T50	0	42	0	0
T52	1104	0	0	0
T53	1307	0	0	0
T56	12305	17	0	0
T58	1128	0	0	0
T61	0	40	0	0
T64	0	15	0	0
T69	12160	56	0	0
T72	5254	0	0	0
T73	1241	0	0	0
T74	5801	10	0	0
T81	0	82	0	0
T97	0	5	0	0

sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2588164	1933	0	0
T47	13498	8	0	0
T48	13355	5	0	0
T50	0	33	0	0
T52	1104	0	0	0
T53	1307	0	0	0
T56	12305	45	0	0
T58	1128	0	0	0
T61	0	41	0	0
T64	0	12	0	0
T69	12160	42	0	0
T72	5254	0	0	0
T73	1241	0	0	0
T74	5801	2	0	0
T81	0	73	0	0
T97	0	22	0	0

sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2588164	2024	0	0
T47	13498	12	0	0
T48	13355	0	0	0
T50	0	56	0	0
T52	1104	0	0	0
T53	1307	0	0	0
T56	12305	54	0	0
T58	1128	0	0	0
T61	0	23	0	0
T64	0	25	0	0
T69	12160	53	0	0
T72	5254	0	0	0
T73	1241	0	0	0
T74	5801	5	0	0
T81	0	118	0	0
T84	0	33	0	0
T97	0	7	0	0

sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2588164	1935	0	0
T47	13498	2	0	0
T48	13355	13	0	0
T50	0	27	0	0
T52	1104	0	0	0
T53	1307	0	0	0
T56	12305	59	0	0
T58	1128	0	0	0
T61	0	69	0	0
T64	0	17	0	0
T69	12160	31	0	0
T72	5254	0	0	0
T73	1241	0	0	0
T74	5801	1	0	0
T81	0	84	0	0
T97	0	11	0	0

sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2588164	2118	0	0
T47	13498	17	0	0
T48	13355	8	0	0
T50	0	52	0	0
T52	1104	0	0	0
T53	1307	0	0	0
T56	12305	47	0	0
T58	1128	0	0	0
T61	0	8	0	0
T64	0	27	0	0
T69	12160	53	0	0
T72	5254	0	0	0
T73	1241	0	0	0
T74	5801	9	0	0
T81	0	77	0	0
T97	0	7	0	0