Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	753670	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

245891

1

T1

1

T2

3

T3

2964

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	856479	1			T1	1		T2	1		T3	5070
values[0x0]	71083	1			T1	3		T2	7		T3	710
values[0x1]	71999	1			T1	6		T2	13		T3	756

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	516974	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

482587

1

T1

3

T2

6

T3

3908

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2879	1			T3	27		T4	17		T5	54
valid_sources[0x01]	4845	1			T3	35		T4	58		T5	44
valid_sources[0x02]	2849	1			T3	21		T4	24		T5	30
valid_sources[0x03]	2819	1			T3	20		T4	17		T5	2
valid_sources[0x04]	2921	1			T3	34		T4	15		T5	28
valid_sources[0x05]	2784	1			T3	23		T4	19		T5	13
valid_sources[0x06]	2755	1			T3	15		T4	8		T5	9
valid_sources[0x07]	2748	1			T3	25		T4	79		T5	13
valid_sources[0x08]	3041	1			T3	39		T4	46		T5	26
valid_sources[0x09]	4827	1			T3	22		T4	14		T5	15
valid_sources[0x0a]	2856	1			T3	27		T4	33		T5	17
valid_sources[0x0b]	2925	1			T3	16		T4	41		T5	33
valid_sources[0x0c]	3030	1			T3	25		T4	93		T5	7
valid_sources[0x0d]	22508	1			T3	29		T4	123		T5	7
valid_sources[0x0e]	2767	1			T3	18		T4	11		T5	37
valid_sources[0x0f]	2545	1			T3	11		T4	26		T5	21
valid_sources[0x10]	2681	1			T3	23		T4	80		T5	12
valid_sources[0x11]	2831	1			T3	14		T4	48		T5	22
valid_sources[0x12]	2779	1			T3	33		T4	73		T5	28
valid_sources[0x13]	3056	1			T3	30		T4	23		T5	24
valid_sources[0x14]	2890	1			T3	24		T4	58		T5	35
valid_sources[0x15]	2687	1			T3	29		T5	26		T9	114
valid_sources[0x16]	2884	1			T3	33		T4	7		T5	19
valid_sources[0x17]	2812	1			T3	7		T4	8		T5	21
valid_sources[0x18]	2906	1			T3	25		T4	41		T5	6
valid_sources[0x19]	3013	1			T3	25		T4	86		T5	8
valid_sources[0x1a]	2821	1			T3	22		T5	14		T9	77
valid_sources[0x1b]	2791	1			T2	1		T3	22		T5	15
valid_sources[0x1c]	2737	1			T3	28		T4	6		T5	17
valid_sources[0x1d]	2736	1			T3	25		T4	100		T5	8
valid_sources[0x1e]	3112	1			T3	33		T4	146		T5	37
valid_sources[0x1f]	2796	1			T3	19		T4	24		T5	15
valid_sources[0x20]	2790	1			T3	32		T4	106		T5	11
valid_sources[0x21]	2913	1			T3	15		T4	82		T5	3
valid_sources[0x22]	2711	1			T3	26		T5	9		T9	103
valid_sources[0x23]	3010	1			T3	30		T4	85		T5	11
valid_sources[0x24]	2866	1			T3	24		T4	29		T5	26
valid_sources[0x25]	2765	1			T3	39		T5	60		T9	81
valid_sources[0x26]	2807	1			T2	2		T3	28		T5	5
valid_sources[0x27]	2998	1			T3	25		T4	58		T5	33
valid_sources[0x28]	2782	1			T3	22		T4	36		T5	37
valid_sources[0x29]	2687	1			T3	27		T4	8		T5	38
valid_sources[0x2a]	2692	1			T3	27		T4	74		T5	18
valid_sources[0x2b]	2841	1			T3	36		T4	15		T5	19
valid_sources[0x2c]	2840	1			T3	36		T4	12		T5	32
valid_sources[0x2d]	2647	1			T3	20		T9	103		T10	126
valid_sources[0x2e]	2734	1			T3	24		T5	34		T9	97
valid_sources[0x2f]	2879	1			T2	1		T3	25		T4	121
valid_sources[0x30]	2932	1			T3	12		T4	6		T5	54
valid_sources[0x31]	2778	1			T3	17		T4	21		T5	68
valid_sources[0x32]	2748	1			T3	32		T5	44		T9	93
valid_sources[0x33]	5950	1			T3	25		T4	1		T5	10
valid_sources[0x34]	6338	1			T3	25		T4	26		T5	25
valid_sources[0x35]	3305	1			T3	37		T4	54		T5	57
valid_sources[0x36]	2913	1			T3	31		T5	4		T9	99
valid_sources[0x37]	2817	1			T3	26		T4	39		T5	19
valid_sources[0x38]	2835	1			T3	17		T4	73		T5	51
valid_sources[0x39]	2748	1			T3	28		T5	9		T9	112
valid_sources[0x3a]	2738	1			T3	30		T4	71		T5	11
valid_sources[0x3b]	3488	1			T3	32		T4	114		T5	45
valid_sources[0x3c]	2965	1			T3	22		T4	58		T5	25
valid_sources[0x3d]	3044	1			T3	17		T4	8		T5	6
valid_sources[0x3e]	2821	1			T3	21		T4	21		T5	37
valid_sources[0x3f]	2862	1			T3	26		T4	73		T5	24
valid_sources[0x40]	2993	1			T3	20		T4	47		T5	10
valid_sources[0x41]	2784	1			T3	24		T4	34		T5	23
valid_sources[0x42]	2841	1			T3	28		T4	28		T5	20
valid_sources[0x43]	52773	1			T3	18		T5	38		T16	1
valid_sources[0x44]	2822	1			T3	28		T5	12		T9	100
valid_sources[0x45]	2933	1			T3	19		T4	2		T5	28
valid_sources[0x46]	2798	1			T2	1		T3	33		T4	36
valid_sources[0x47]	2850	1			T3	18		T4	90		T5	30
valid_sources[0x48]	2744	1			T3	32		T4	32		T5	30
valid_sources[0x49]	3065	1			T3	9		T5	19		T6	132
valid_sources[0x4a]	2740	1			T3	25		T4	38		T5	36
valid_sources[0x4b]	2855	1			T2	1		T3	33		T5	15
valid_sources[0x4c]	2802	1			T3	29		T5	10		T9	98
valid_sources[0x4d]	3223	1			T3	31		T4	129		T5	48
valid_sources[0x4e]	2533	1			T3	18		T5	2		T9	106
valid_sources[0x4f]	3384	1			T3	23		T4	45		T5	33
valid_sources[0x50]	5652	1			T3	29		T5	21		T9	94
valid_sources[0x51]	2837	1			T3	29		T4	15		T5	44
valid_sources[0x52]	2810	1			T3	45		T4	60		T5	5
valid_sources[0x53]	2770	1			T3	29		T4	51		T5	12
valid_sources[0x54]	2741	1			T3	46		T4	101		T5	52
valid_sources[0x55]	3052	1			T3	22		T4	23		T9	87
valid_sources[0x56]	2739	1			T3	26		T4	26		T5	11
valid_sources[0x57]	3114	1			T3	21		T4	144		T5	32
valid_sources[0x58]	3053	1			T3	20		T4	151		T5	47
valid_sources[0x59]	33410	1			T3	14		T4	7		T5	24
valid_sources[0x5a]	2854	1			T3	27		T4	28		T5	54
valid_sources[0x5b]	2889	1			T3	26		T5	14		T9	77
valid_sources[0x5c]	2865	1			T3	31		T4	39		T5	15
valid_sources[0x5d]	2839	1			T3	24		T4	99		T5	35
valid_sources[0x5e]	6911	1			T3	34		T4	39		T5	43
valid_sources[0x5f]	3061	1			T3	18		T4	71		T5	30
valid_sources[0x60]	2859	1			T3	38		T5	49		T6	46
valid_sources[0x61]	7450	1			T3	30		T5	30		T9	105
valid_sources[0x62]	2852	1			T3	24		T4	68		T5	30
valid_sources[0x63]	2750	1			T3	16		T5	48		T9	116
valid_sources[0x64]	3004	1			T3	23		T5	38		T9	101
valid_sources[0x65]	2637	1			T3	23		T5	18		T9	95
valid_sources[0x66]	2695	1			T3	26		T4	24		T5	13
valid_sources[0x67]	2689	1			T3	26		T4	7		T5	8
valid_sources[0x68]	2824	1			T3	20		T4	33		T5	47
valid_sources[0x69]	3141	1			T3	25		T4	6		T5	15
valid_sources[0x6a]	2844	1			T3	25		T5	10		T9	84
valid_sources[0x6b]	3049	1			T2	1		T3	17		T4	97
valid_sources[0x6c]	2648	1			T3	31		T4	80		T5	27
valid_sources[0x6d]	2989	1			T3	21		T5	73		T9	79
valid_sources[0x6e]	2911	1			T3	27		T5	10		T9	114
valid_sources[0x6f]	2774	1			T3	24		T5	2		T9	129
valid_sources[0x70]	2846	1			T3	29		T4	50		T5	32
valid_sources[0x71]	2827	1			T3	18		T5	35		T9	104
valid_sources[0x72]	2970	1			T3	20		T5	13		T9	97
valid_sources[0x73]	2811	1			T3	28		T4	51		T5	33
valid_sources[0x74]	2670	1			T3	20		T4	14		T5	3
valid_sources[0x75]	2799	1			T3	34		T4	25		T5	3
valid_sources[0x76]	6370	1			T3	23		T4	2		T5	25
valid_sources[0x77]	3020	1			T2	2		T3	18		T5	8
valid_sources[0x78]	2828	1			T3	26		T4	44		T5	11
valid_sources[0x79]	2676	1			T2	1		T3	28		T5	31
valid_sources[0x7a]	2664	1			T3	29		T4	65		T5	5
valid_sources[0x7b]	3131	1			T3	19		T4	57		T9	99
valid_sources[0x7c]	3045	1			T3	28		T4	28		T5	34
valid_sources[0x7d]	2919	1			T3	32		T5	9		T9	103
valid_sources[0x7e]	2800	1			T3	30		T5	10		T9	96
valid_sources[0x7f]	2535	1			T3	20		T4	19		T5	23
valid_sources[0x80]	2757	1			T3	28		T4	44		T5	30

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

136339

1

T2

1

T3

1947

T4

2014

values[0x0]

all_enables

biggest_size

58499

1

T2

1

T3

558

T4

584

values[0x1]

all_enables

biggest_size

51053

1

T1

1

T2

1

T3

459