Unified Coverage Report :: Module :: keymgr_dpe_csr_assert_fpv

Module : keymgr_dpe_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_dpe_csr_assert_0/keymgr_dpe_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_dpe_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_dpe_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.39	100.00	80.22	53.88		97.83	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_dpe_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	22	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	22	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	7831309	9774	0	0
intr_enable_rd_A	7831309	1898	0	0
key_version_rd_A	7831309	1850	0	0
reseed_interval_regwen_rd_A	7831309	661	0	0
salt_0_rd_A	7831309	1766	0	0
salt_1_rd_A	7831309	1762	0	0
salt_2_rd_A	7831309	1737	0	0
salt_3_rd_A	7831309	1621	0	0
salt_4_rd_A	7831309	1696	0	0
salt_5_rd_A	7831309	1620	0	0
salt_6_rd_A	7831309	1719	0	0
salt_7_rd_A	7831309	1694	0	0
sideload_clear_rd_A	7831309	1796	0	0
slot_policy_rd_A	7831309	2665	0	0
sw_binding_0_rd_A	7831309	1604	0	0
sw_binding_1_rd_A	7831309	1685	0	0
sw_binding_2_rd_A	7831309	1737	0	0
sw_binding_3_rd_A	7831309	1800	0	0
sw_binding_4_rd_A	7831309	1736	0	0
sw_binding_5_rd_A	7831309	1829	0	0
sw_binding_6_rd_A	7831309	1731	0	0
sw_binding_7_rd_A	7831309	1734	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7831309	9774	0	0
T19	4477	2	0	0
T20	10323	3	0	0
T21	1505	2	0	0
T26	0	648	0	0
T27	0	352	0	0
T28	27671	1	0	0
T29	1943	14	0	0
T53	0	4	0	0
T55	0	2	0	0
T65	2768	20	0	0
T66	4152	0	0	0
T70	2326	0	0	0
T98	1004	0	0	0
T99	1498	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7831309	1898	0	0
T21	1505	2	0	0
T28	0	69	0	0
T29	0	8	0	0
T39	1334	18	0	0
T40	1118	9	0	0
T64	6455	0	0	0
T66	0	11	0	0
T89	0	9	0	0
T100	1161	3	0	0
T101	843	9	0	0
T102	3041	9	0	0
T103	992	0	0	0
T104	1262	0	0	0
T105	988	0	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7831309	1850	0	0
T21	1505	9	0	0
T28	0	63	0	0
T29	0	4	0	0
T64	6455	0	0	0
T65	2768	0	0	0
T68	0	83	0	0
T70	0	11	0	0
T86	6693	0	0	0
T89	930	0	0	0
T90	1214	0	0	0
T102	3041	14	0	0
T103	992	0	0	0
T104	1262	0	0	0
T105	988	0	0	0
T106	0	24	0	0
T107	0	11	0	0
T108	0	90	0	0
T109	0	31	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7831309	661	0	0
T21	1505	4	0	0
T28	0	1	0	0
T29	0	8	0	0
T64	6455	0	0	0
T65	2768	0	0	0
T66	0	4	0	0
T68	0	12	0	0
T70	0	2	0	0
T86	6693	0	0	0
T89	930	0	0	0
T90	1214	0	0	0
T102	3041	7	0	0
T103	992	0	0	0
T104	1262	0	0	0
T105	988	0	0	0
T106	0	35	0	0
T107	0	23	0	0
T110	0	2	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7831309	1766	0	0
T21	1505	5	0	0
T28	0	95	0	0
T64	6455	0	0	0
T65	2768	0	0	0
T66	0	8	0	0
T68	0	90	0	0
T70	0	9	0	0
T86	6693	0	0	0
T89	930	0	0	0
T90	1214	0	0	0
T102	3041	10	0	0
T103	992	0	0	0
T104	1262	0	0	0
T105	988	0	0	0
T106	0	18	0	0
T107	0	22	0	0
T108	0	69	0	0
T109	0	27	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7831309	1762	0	0
T21	1505	9	0	0
T28	0	71	0	0
T29	0	3	0	0
T64	6455	0	0	0
T65	2768	0	0	0
T66	0	8	0	0
T68	0	87	0	0
T70	0	3	0	0
T86	6693	0	0	0
T89	930	0	0	0
T90	1214	0	0	0
T102	3041	13	0	0
T103	992	0	0	0
T104	1262	0	0	0
T105	988	0	0	0
T106	0	19	0	0
T107	0	2	0	0
T110	0	9	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7831309	1737	0	0
T21	1505	5	0	0
T28	0	90	0	0
T29	0	9	0	0
T64	6455	0	0	0
T65	2768	0	0	0
T66	0	7	0	0
T68	0	70	0	0
T86	6693	0	0	0
T89	930	0	0	0
T90	1214	0	0	0
T102	3041	3	0	0
T103	992	0	0	0
T104	1262	0	0	0
T105	988	0	0	0
T106	0	14	0	0
T107	0	6	0	0
T108	0	86	0	0
T110	0	5	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7831309	1621	0	0
T21	1505	7	0	0
T28	0	81	0	0
T29	0	9	0	0
T64	6455	0	0	0
T65	2768	0	0	0
T66	0	4	0	0
T68	0	82	0	0
T86	6693	0	0	0
T89	930	0	0	0
T90	1214	0	0	0
T102	3041	3	0	0
T103	992	0	0	0
T104	1262	0	0	0
T105	988	0	0	0
T106	0	33	0	0
T107	0	6	0	0
T108	0	62	0	0
T110	0	14	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7831309	1696	0	0
T21	1505	8	0	0
T28	0	87	0	0
T29	0	5	0	0
T64	6455	0	0	0
T65	2768	0	0	0
T68	0	70	0	0
T70	0	1	0	0
T86	6693	0	0	0
T89	930	0	0	0
T90	1214	0	0	0
T102	3041	8	0	0
T103	992	0	0	0
T104	1262	0	0	0
T105	988	0	0	0
T106	0	24	0	0
T107	0	16	0	0
T108	0	74	0	0
T110	0	9	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7831309	1620	0	0
T21	1505	9	0	0
T28	0	77	0	0
T29	0	4	0	0
T64	6455	0	0	0
T65	2768	0	0	0
T68	0	72	0	0
T70	0	3	0	0
T86	6693	0	0	0
T89	930	0	0	0
T90	1214	0	0	0
T102	3041	11	0	0
T103	992	0	0	0
T104	1262	0	0	0
T105	988	0	0	0
T106	0	20	0	0
T107	0	17	0	0
T108	0	77	0	0
T110	0	2	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7831309	1719	0	0
T21	1505	5	0	0
T28	0	73	0	0
T29	0	4	0	0
T64	6455	0	0	0
T65	2768	0	0	0
T66	0	5	0	0
T68	0	93	0	0
T70	0	4	0	0
T86	6693	0	0	0
T89	930	0	0	0
T90	1214	0	0	0
T102	3041	2	0	0
T103	992	0	0	0
T104	1262	0	0	0
T105	988	0	0	0
T106	0	21	0	0
T107	0	5	0	0
T108	0	76	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7831309	1694	0	0
T21	1505	6	0	0
T28	0	75	0	0
T29	0	4	0	0
T64	6455	0	0	0
T65	2768	0	0	0
T66	0	8	0	0
T68	0	88	0	0
T70	0	2	0	0
T86	6693	0	0	0
T89	930	0	0	0
T90	1214	0	0	0
T102	3041	10	0	0
T103	992	0	0	0
T104	1262	0	0	0
T105	988	0	0	0
T106	0	21	0	0
T107	0	12	0	0
T108	0	74	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7831309	1796	0	0
T21	1505	3	0	0
T28	0	95	0	0
T29	0	15	0	0
T64	6455	0	0	0
T65	2768	0	0	0
T66	0	8	0	0
T68	0	83	0	0
T70	0	2	0	0
T86	6693	0	0	0
T89	930	0	0	0
T90	1214	0	0	0
T102	3041	14	0	0
T103	992	0	0	0
T104	1262	0	0	0
T105	988	0	0	0
T106	0	33	0	0
T107	0	5	0	0
T110	0	7	0	0

slot_policy_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7831309	2665	0	0
T21	1505	2	0	0
T28	0	186	0	0
T29	0	4	0	0
T64	6455	0	0	0
T65	2768	0	0	0
T66	0	6	0	0
T68	0	127	0	0
T86	6693	0	0	0
T89	930	0	0	0
T90	1214	0	0	0
T102	3041	1	0	0
T103	992	0	0	0
T104	1262	0	0	0
T105	988	0	0	0
T106	0	30	0	0
T107	0	8	0	0
T108	0	140	0	0
T109	0	40	0	0

sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7831309	1604	0	0
T21	1505	4	0	0
T28	0	74	0	0
T29	0	1	0	0
T64	6455	0	0	0
T65	2768	0	0	0
T66	0	5	0	0
T68	0	69	0	0
T70	0	5	0	0
T86	6693	0	0	0
T89	930	0	0	0
T90	1214	0	0	0
T102	3041	4	0	0
T103	992	0	0	0
T104	1262	0	0	0
T105	988	0	0	0
T106	0	16	0	0
T107	0	22	0	0
T110	0	6	0	0

sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7831309	1685	0	0
T28	0	93	0	0
T29	0	10	0	0
T64	6455	0	0	0
T65	2768	0	0	0
T66	0	5	0	0
T68	0	65	0	0
T70	0	3	0	0
T86	6693	0	0	0
T89	930	0	0	0
T90	1214	0	0	0
T98	1004	0	0	0
T102	3041	16	0	0
T103	992	0	0	0
T104	1262	0	0	0
T105	988	0	0	0
T106	0	20	0	0
T107	0	9	0	0
T108	0	68	0	0
T110	0	9	0	0

sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7831309	1737	0	0
T21	1505	1	0	0
T28	0	86	0	0
T29	0	16	0	0
T64	6455	0	0	0
T65	2768	0	0	0
T68	0	81	0	0
T70	0	3	0	0
T86	6693	0	0	0
T89	930	0	0	0
T90	1214	0	0	0
T102	3041	8	0	0
T103	992	0	0	0
T104	1262	0	0	0
T105	988	0	0	0
T106	0	31	0	0
T107	0	18	0	0
T108	0	72	0	0
T110	0	4	0	0

sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7831309	1800	0	0
T21	1505	5	0	0
T28	0	85	0	0
T29	0	1	0	0
T64	6455	0	0	0
T65	2768	0	0	0
T66	0	3	0	0
T68	0	106	0	0
T86	6693	0	0	0
T89	930	0	0	0
T90	1214	0	0	0
T102	3041	5	0	0
T103	992	0	0	0
T104	1262	0	0	0
T105	988	0	0	0
T106	0	19	0	0
T107	0	12	0	0
T108	0	72	0	0
T110	0	8	0	0

sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7831309	1736	0	0
T21	1505	2	0	0
T28	0	59	0	0
T29	0	3	0	0
T64	6455	0	0	0
T65	2768	0	0	0
T66	0	14	0	0
T68	0	100	0	0
T86	6693	0	0	0
T89	930	0	0	0
T90	1214	0	0	0
T102	3041	8	0	0
T103	992	0	0	0
T104	1262	0	0	0
T105	988	0	0	0
T106	0	20	0	0
T107	0	25	0	0
T108	0	77	0	0
T110	0	13	0	0

sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7831309	1829	0	0
T21	1505	5	0	0
T28	0	79	0	0
T64	6455	0	0	0
T65	2768	0	0	0
T66	0	11	0	0
T68	0	81	0	0
T70	0	3	0	0
T86	6693	0	0	0
T89	930	0	0	0
T90	1214	0	0	0
T102	3041	15	0	0
T103	992	0	0	0
T104	1262	0	0	0
T105	988	0	0	0
T106	0	11	0	0
T107	0	16	0	0
T108	0	75	0	0
T110	0	10	0	0

sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7831309	1731	0	0
T21	1505	9	0	0
T28	0	82	0	0
T29	0	12	0	0
T64	6455	0	0	0
T65	2768	0	0	0
T66	0	7	0	0
T68	0	57	0	0
T70	0	16	0	0
T86	6693	0	0	0
T89	930	0	0	0
T90	1214	0	0	0
T102	3041	9	0	0
T103	992	0	0	0
T104	1262	0	0	0
T105	988	0	0	0
T106	0	29	0	0
T107	0	26	0	0
T110	0	10	0	0

sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7831309	1734	0	0
T21	1505	9	0	0
T28	0	63	0	0
T29	0	4	0	0
T64	6455	0	0	0
T65	2768	0	0	0
T66	0	5	0	0
T68	0	77	0	0
T70	0	7	0	0
T86	6693	0	0	0
T89	930	0	0	0
T90	1214	0	0	0
T102	3041	12	0	0
T103	992	0	0	0
T104	1262	0	0	0
T105	988	0	0	0
T106	0	21	0	0
T107	0	18	0	0
T110	0	10	0	0