Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1287178	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

241316

1

T1

8

T2

2561

T3

2642

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1386665	1			T1	1		T2	5170		T3	5203
values[0x0]	70648	1			T1	21		T2	691		T3	637
values[0x1]	71181	1			T1	20		T2	706		T3	617

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	873195	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

655299

1

T1

15

T2

3662

T3

3677

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6042	1			T2	15		T3	30		T8	49
valid_sources[0x01]	5151	1			T2	16		T3	11		T8	41
valid_sources[0x02]	5389	1			T2	12		T3	28		T8	8
valid_sources[0x03]	5633	1			T2	36		T3	31		T8	49
valid_sources[0x04]	5428	1			T2	25		T3	30		T8	10
valid_sources[0x05]	5734	1			T2	11		T3	23		T8	15
valid_sources[0x06]	5605	1			T2	31		T3	21		T8	49
valid_sources[0x07]	5459	1			T2	29		T3	31		T8	17
valid_sources[0x08]	17157	1			T2	23		T3	16		T8	74
valid_sources[0x09]	5506	1			T2	53		T3	21		T8	66
valid_sources[0x0a]	5229	1			T1	1		T2	10		T3	20
valid_sources[0x0b]	5876	1			T2	27		T3	26		T8	68
valid_sources[0x0c]	5071	1			T2	3		T3	15		T8	46
valid_sources[0x0d]	5616	1			T2	39		T3	40		T8	19
valid_sources[0x0e]	5136	1			T2	18		T3	28		T8	88
valid_sources[0x0f]	5172	1			T2	19		T3	27		T8	53
valid_sources[0x10]	5276	1			T2	20		T3	37		T8	9
valid_sources[0x11]	5639	1			T2	49		T3	30		T8	24
valid_sources[0x12]	6765	1			T2	52		T3	20		T8	85
valid_sources[0x13]	5669	1			T2	46		T3	27		T8	7
valid_sources[0x14]	5626	1			T2	29		T3	17		T8	34
valid_sources[0x15]	5497	1			T1	1		T2	44		T3	32
valid_sources[0x16]	6280	1			T2	22		T3	29		T8	52
valid_sources[0x17]	5444	1			T2	1		T3	15		T8	13
valid_sources[0x18]	7076	1			T2	20		T3	21		T8	3
valid_sources[0x19]	5418	1			T2	56		T3	22		T8	109
valid_sources[0x1a]	5490	1			T2	57		T3	27		T8	88
valid_sources[0x1b]	5525	1			T1	1		T2	55		T3	24
valid_sources[0x1c]	5362	1			T2	7		T3	34		T8	13
valid_sources[0x1d]	5454	1			T2	21		T3	34		T8	21
valid_sources[0x1e]	5351	1			T1	1		T2	23		T3	21
valid_sources[0x1f]	5167	1			T2	8		T3	34		T8	7
valid_sources[0x20]	5414	1			T2	23		T3	17		T8	93
valid_sources[0x21]	13525	1			T2	26		T3	17		T4	7956
valid_sources[0x22]	5367	1			T2	47		T3	30		T8	39
valid_sources[0x23]	5398	1			T2	51		T3	24		T8	52
valid_sources[0x24]	5291	1			T2	7		T3	21		T8	61
valid_sources[0x25]	5388	1			T2	43		T3	28		T8	30
valid_sources[0x26]	5499	1			T1	1		T2	30		T3	29
valid_sources[0x27]	5318	1			T2	34		T3	20		T8	11
valid_sources[0x28]	5661	1			T1	1		T2	12		T3	22
valid_sources[0x29]	5458	1			T2	14		T3	12		T8	19
valid_sources[0x2a]	5231	1			T2	21		T3	17		T8	39
valid_sources[0x2b]	5560	1			T2	47		T3	19		T8	49
valid_sources[0x2c]	5520	1			T2	68		T3	28		T8	40
valid_sources[0x2d]	5483	1			T2	8		T3	21		T8	24
valid_sources[0x2e]	5636	1			T2	24		T3	26		T8	31
valid_sources[0x2f]	5355	1			T2	29		T3	29		T8	78
valid_sources[0x30]	5369	1			T2	18		T3	20		T8	21
valid_sources[0x31]	5408	1			T2	25		T3	20		T8	26
valid_sources[0x32]	5219	1			T2	44		T3	10		T8	89
valid_sources[0x33]	7378	1			T1	1		T2	5		T3	21
valid_sources[0x34]	5635	1			T2	30		T3	36		T8	34
valid_sources[0x35]	5494	1			T2	29		T3	21		T8	71
valid_sources[0x36]	5554	1			T2	14		T3	16		T8	22
valid_sources[0x37]	5364	1			T2	34		T3	15		T8	31
valid_sources[0x38]	5286	1			T2	25		T3	22		T8	32
valid_sources[0x39]	5464	1			T1	1		T2	4		T3	38
valid_sources[0x3a]	5357	1			T1	1		T2	23		T3	25
valid_sources[0x3b]	5680	1			T2	33		T3	35		T8	11
valid_sources[0x3c]	5588	1			T2	54		T3	29		T8	25
valid_sources[0x3d]	5891	1			T2	43		T3	29		T8	83
valid_sources[0x3e]	5398	1			T2	34		T3	22		T8	18
valid_sources[0x3f]	5575	1			T2	33		T3	23		T8	52
valid_sources[0x40]	6798	1			T2	44		T3	18		T8	82
valid_sources[0x41]	5578	1			T2	46		T3	19		T8	3
valid_sources[0x42]	5271	1			T2	21		T3	26		T8	17
valid_sources[0x43]	5997	1			T2	34		T3	31		T8	24
valid_sources[0x44]	5432	1			T2	23		T3	31		T8	33
valid_sources[0x45]	5227	1			T2	17		T3	30		T8	55
valid_sources[0x46]	5308	1			T2	2		T3	20		T8	11
valid_sources[0x47]	5412	1			T2	5		T3	22		T8	54
valid_sources[0x48]	5319	1			T2	22		T3	31		T8	28
valid_sources[0x49]	5401	1			T2	34		T3	30		T8	39
valid_sources[0x4a]	5473	1			T2	27		T3	42		T8	9
valid_sources[0x4b]	5423	1			T2	22		T3	18		T8	27
valid_sources[0x4c]	5473	1			T2	10		T3	30		T8	44
valid_sources[0x4d]	5591	1			T2	18		T3	23		T8	74
valid_sources[0x4e]	5179	1			T2	10		T3	23		T8	18
valid_sources[0x4f]	5432	1			T2	30		T3	20		T8	8
valid_sources[0x50]	5363	1			T2	12		T3	33		T8	59
valid_sources[0x51]	5368	1			T2	24		T3	23		T8	25
valid_sources[0x52]	25601	1			T1	1		T2	18		T3	39
valid_sources[0x53]	5159	1			T2	9		T3	22		T8	33
valid_sources[0x54]	5396	1			T2	18		T3	25		T8	54
valid_sources[0x55]	5303	1			T2	13		T3	36		T8	56
valid_sources[0x56]	5173	1			T1	1		T2	34		T3	28
valid_sources[0x57]	5557	1			T2	23		T3	23		T8	86
valid_sources[0x58]	5561	1			T2	11		T3	16		T8	18
valid_sources[0x59]	5407	1			T2	37		T3	32		T9	27
valid_sources[0x5a]	5503	1			T2	16		T3	23		T8	28
valid_sources[0x5b]	5126	1			T2	7		T3	38		T8	30
valid_sources[0x5c]	5324	1			T1	1		T2	21		T3	23
valid_sources[0x5d]	8359	1			T1	1		T2	23		T3	22
valid_sources[0x5e]	5307	1			T2	21		T3	15		T8	37
valid_sources[0x5f]	5511	1			T1	1		T2	35		T3	27
valid_sources[0x60]	5084	1			T2	29		T3	32		T8	19
valid_sources[0x61]	5433	1			T2	29		T3	29		T8	6
valid_sources[0x62]	5438	1			T2	12		T3	24		T8	66
valid_sources[0x63]	5545	1			T2	62		T3	24		T8	53
valid_sources[0x64]	6147	1			T2	9		T3	30		T8	84
valid_sources[0x65]	5158	1			T2	2		T3	24		T8	27
valid_sources[0x66]	5317	1			T2	19		T3	26		T8	4
valid_sources[0x67]	5827	1			T2	42		T3	25		T8	48
valid_sources[0x68]	5325	1			T2	45		T3	17		T8	19
valid_sources[0x69]	5406	1			T2	36		T3	43		T8	28
valid_sources[0x6a]	5284	1			T2	23		T3	13		T8	33
valid_sources[0x6b]	5293	1			T1	1		T2	28		T3	42
valid_sources[0x6c]	5257	1			T2	28		T3	29		T8	29
valid_sources[0x6d]	5282	1			T2	5		T3	16		T8	30
valid_sources[0x6e]	5094	1			T2	22		T3	29		T8	7
valid_sources[0x6f]	5669	1			T2	34		T3	34		T8	8
valid_sources[0x70]	5530	1			T2	14		T3	30		T8	8
valid_sources[0x71]	8674	1			T1	1		T2	30		T3	34
valid_sources[0x72]	5559	1			T2	34		T3	23		T8	38
valid_sources[0x73]	5430	1			T2	17		T3	30		T8	52
valid_sources[0x74]	5343	1			T2	22		T3	10		T8	22
valid_sources[0x75]	5557	1			T2	19		T3	31		T8	26
valid_sources[0x76]	5081	1			T1	1		T2	8		T3	43
valid_sources[0x77]	5304	1			T2	12		T3	19		T8	52
valid_sources[0x78]	5361	1			T2	9		T3	20		T8	23
valid_sources[0x79]	5300	1			T2	32		T3	21		T8	52
valid_sources[0x7a]	5014	1			T2	18		T3	22		T8	23
valid_sources[0x7b]	6470	1			T2	1		T3	31		T4	586
valid_sources[0x7c]	5259	1			T2	9		T3	19		T8	60
valid_sources[0x7d]	5471	1			T2	26		T3	20		T8	81
valid_sources[0x7e]	5393	1			T1	1		T2	17		T3	8
valid_sources[0x7f]	5345	1			T2	33		T3	26		T8	10
valid_sources[0x80]	5382	1			T2	27		T3	14		T8	20

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

132269

1

T2

1629

T3

1786

T4

1630

values[0x0]

all_enables

biggest_size

58224

1

T1

4

T2

515

T3

483

values[0x1]

all_enables

biggest_size

50823

1

T1

4

T2

417

T3

373