Unified Coverage Report :: Module :: keymgr_dpe_csr_assert_fpv

Module : keymgr_dpe_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_dpe_csr_assert_0/keymgr_dpe_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_dpe_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_dpe_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.39	100.00	80.22	53.88		97.83	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_dpe_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	22	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	22	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	8765551	8987	0	0
intr_enable_rd_A	8765551	1989	0	0
key_version_rd_A	8765551	1485	0	0
reseed_interval_regwen_rd_A	8765551	708	0	0
salt_0_rd_A	8765551	1640	0	0
salt_1_rd_A	8765551	1556	0	0
salt_2_rd_A	8765551	1656	0	0
salt_3_rd_A	8765551	1554	0	0
salt_4_rd_A	8765551	1586	0	0
salt_5_rd_A	8765551	1512	0	0
salt_6_rd_A	8765551	1619	0	0
salt_7_rd_A	8765551	1557	0	0
sideload_clear_rd_A	8765551	1497	0	0
slot_policy_rd_A	8765551	2061	0	0
sw_binding_0_rd_A	8765551	1512	0	0
sw_binding_1_rd_A	8765551	1452	0	0
sw_binding_2_rd_A	8765551	1808	0	0
sw_binding_3_rd_A	8765551	1505	0	0
sw_binding_4_rd_A	8765551	1595	0	0
sw_binding_5_rd_A	8765551	1725	0	0
sw_binding_6_rd_A	8765551	1536	0	0
sw_binding_7_rd_A	8765551	1571	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8765551	8987	0	0
T18	22496	4	0	0
T19	11399	2	0	0
T20	8042	336	0	0
T34	4667	333	0	0
T35	5025	3	0	0
T36	1502	135	0	0
T37	3448	94	0	0
T48	0	5	0	0
T60	0	62	0	0
T68	4842	0	0	0
T71	7194	0	0	0
T73	1083	0	0	0
T94	0	27	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8765551	1989	0	0
T18	22496	27	0	0
T19	11399	43	0	0
T35	5025	0	0	0
T37	3448	0	0	0
T45	1418	3	0	0
T51	22954	94	0	0
T68	4842	13	0	0
T72	0	36	0	0
T73	1083	0	0	0
T84	2429	6	0	0
T95	835	15	0	0
T96	0	32	0	0
T97	0	14	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8765551	1485	0	0
T18	22496	61	0	0
T19	11399	50	0	0
T35	5025	0	0	0
T37	3448	0	0	0
T51	22954	94	0	0
T68	4842	14	0	0
T69	0	92	0	0
T71	7194	0	0	0
T72	8023	23	0	0
T73	1083	0	0	0
T84	2429	8	0	0
T90	0	39	0	0
T96	0	27	0	0
T98	0	5	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8765551	708	0	0
T35	5025	0	0	0
T48	9143	0	0	0
T51	22954	43	0	0
T68	4842	17	0	0
T69	0	40	0	0
T71	7194	0	0	0
T72	8023	19	0	0
T73	1083	0	0	0
T88	2264	0	0	0
T90	0	54	0	0
T96	7971	33	0	0
T98	0	1	0	0
T99	0	42	0	0
T100	0	16	0	0
T101	0	4	0	0
T102	778	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8765551	1640	0	0
T18	22496	37	0	0
T19	11399	45	0	0
T35	5025	0	0	0
T37	3448	0	0	0
T51	22954	97	0	0
T68	4842	12	0	0
T69	0	54	0	0
T71	7194	0	0	0
T72	8023	28	0	0
T73	1083	0	0	0
T84	2429	15	0	0
T90	0	27	0	0
T96	0	18	0	0
T98	0	3	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8765551	1556	0	0
T18	22496	24	0	0
T19	11399	27	0	0
T35	5025	0	0	0
T37	3448	0	0	0
T51	22954	94	0	0
T68	4842	16	0	0
T69	0	98	0	0
T71	7194	0	0	0
T72	8023	26	0	0
T73	1083	0	0	0
T84	2429	2	0	0
T90	0	67	0	0
T96	0	16	0	0
T98	0	1	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8765551	1656	0	0
T18	22496	31	0	0
T19	11399	39	0	0
T35	5025	0	0	0
T37	3448	0	0	0
T51	22954	128	0	0
T68	4842	6	0	0
T69	0	95	0	0
T71	7194	0	0	0
T72	8023	16	0	0
T73	1083	0	0	0
T84	2429	1	0	0
T90	0	41	0	0
T96	0	31	0	0
T98	0	2	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8765551	1554	0	0
T18	22496	54	0	0
T19	11399	28	0	0
T35	5025	0	0	0
T37	3448	0	0	0
T41	0	8	0	0
T51	22954	105	0	0
T68	4842	25	0	0
T69	0	92	0	0
T71	7194	0	0	0
T72	8023	24	0	0
T73	1083	0	0	0
T84	2429	1	0	0
T90	0	32	0	0
T96	0	24	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8765551	1586	0	0
T18	22496	38	0	0
T19	11399	28	0	0
T35	5025	0	0	0
T37	3448	0	0	0
T51	22954	81	0	0
T68	4842	14	0	0
T69	0	76	0	0
T71	7194	0	0	0
T72	8023	15	0	0
T73	1083	0	0	0
T84	2429	11	0	0
T90	0	75	0	0
T96	0	16	0	0
T98	0	1	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8765551	1512	0	0
T18	22496	34	0	0
T19	11399	27	0	0
T35	5025	0	0	0
T37	3448	0	0	0
T51	22954	94	0	0
T68	4842	14	0	0
T69	0	72	0	0
T71	7194	0	0	0
T72	8023	24	0	0
T73	1083	0	0	0
T84	2429	5	0	0
T90	0	10	0	0
T96	0	27	0	0
T98	0	1	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8765551	1619	0	0
T18	22496	34	0	0
T19	11399	39	0	0
T35	5025	0	0	0
T37	3448	0	0	0
T51	22954	85	0	0
T68	4842	11	0	0
T69	0	90	0	0
T71	7194	0	0	0
T72	8023	26	0	0
T73	1083	0	0	0
T84	2429	4	0	0
T90	0	39	0	0
T96	0	27	0	0
T98	0	5	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8765551	1557	0	0
T18	22496	52	0	0
T19	11399	27	0	0
T35	5025	0	0	0
T37	3448	0	0	0
T51	22954	86	0	0
T68	4842	16	0	0
T69	0	96	0	0
T71	7194	0	0	0
T72	8023	22	0	0
T73	1083	0	0	0
T84	2429	7	0	0
T90	0	16	0	0
T96	0	31	0	0
T98	0	3	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8765551	1497	0	0
T18	22496	21	0	0
T19	11399	41	0	0
T35	5025	0	0	0
T37	3448	0	0	0
T51	22954	64	0	0
T68	4842	12	0	0
T69	0	88	0	0
T71	7194	0	0	0
T72	8023	22	0	0
T73	1083	0	0	0
T84	2429	10	0	0
T90	0	28	0	0
T96	0	26	0	0
T98	0	1	0	0

slot_policy_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8765551	2061	0	0
T18	22496	62	0	0
T19	11399	86	0	0
T35	5025	0	0	0
T37	3448	0	0	0
T51	22954	102	0	0
T68	4842	11	0	0
T69	0	144	0	0
T71	7194	0	0	0
T72	8023	11	0	0
T73	1083	0	0	0
T84	2429	12	0	0
T90	0	60	0	0
T96	0	13	0	0
T98	0	8	0	0

sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8765551	1512	0	0
T18	22496	50	0	0
T19	11399	47	0	0
T35	5025	0	0	0
T37	3448	0	0	0
T51	22954	75	0	0
T68	4842	11	0	0
T69	0	77	0	0
T71	7194	0	0	0
T72	8023	23	0	0
T73	1083	0	0	0
T84	2429	2	0	0
T90	0	13	0	0
T96	0	29	0	0
T98	0	5	0	0

sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8765551	1452	0	0
T18	22496	21	0	0
T19	11399	49	0	0
T35	5025	0	0	0
T37	3448	0	0	0
T51	22954	111	0	0
T68	4842	12	0	0
T69	0	85	0	0
T71	7194	0	0	0
T72	8023	20	0	0
T73	1083	0	0	0
T84	2429	12	0	0
T90	0	5	0	0
T96	0	24	0	0
T98	0	10	0	0

sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8765551	1808	0	0
T18	22496	85	0	0
T19	11399	50	0	0
T35	5025	0	0	0
T37	3448	0	0	0
T51	22954	104	0	0
T68	4842	4	0	0
T69	0	75	0	0
T71	7194	0	0	0
T72	8023	19	0	0
T73	1083	0	0	0
T84	2429	11	0	0
T90	0	90	0	0
T96	0	23	0	0
T98	0	7	0	0

sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8765551	1505	0	0
T18	22496	30	0	0
T19	11399	49	0	0
T35	5025	0	0	0
T37	3448	0	0	0
T51	22954	103	0	0
T68	4842	8	0	0
T69	0	82	0	0
T71	7194	0	0	0
T72	8023	18	0	0
T73	1083	0	0	0
T84	2429	7	0	0
T90	0	18	0	0
T96	0	19	0	0
T99	0	14	0	0

sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8765551	1595	0	0
T18	22496	41	0	0
T19	11399	54	0	0
T35	5025	0	0	0
T37	3448	0	0	0
T51	22954	71	0	0
T68	4842	7	0	0
T69	0	75	0	0
T71	7194	0	0	0
T72	8023	28	0	0
T73	1083	0	0	0
T84	2429	3	0	0
T90	0	33	0	0
T96	0	29	0	0
T98	0	1	0	0

sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8765551	1725	0	0
T18	22496	40	0	0
T19	11399	56	0	0
T35	5025	0	0	0
T37	3448	0	0	0
T51	22954	70	0	0
T68	4842	14	0	0
T69	0	84	0	0
T71	7194	0	0	0
T72	8023	25	0	0
T73	1083	0	0	0
T84	2429	2	0	0
T90	0	89	0	0
T96	0	28	0	0
T98	0	9	0	0

sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8765551	1536	0	0
T18	22496	31	0	0
T19	11399	20	0	0
T35	5025	0	0	0
T37	3448	0	0	0
T51	22954	92	0	0
T68	4842	4	0	0
T69	0	91	0	0
T71	7194	0	0	0
T72	8023	17	0	0
T73	1083	0	0	0
T84	2429	4	0	0
T90	0	66	0	0
T96	0	29	0	0
T99	0	10	0	0

sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8765551	1571	0	0
T18	22496	46	0	0
T19	11399	45	0	0
T35	5025	0	0	0
T37	3448	0	0	0
T51	22954	118	0	0
T68	4842	21	0	0
T69	0	79	0	0
T71	7194	0	0	0
T72	8023	16	0	0
T73	1083	0	0	0
T84	2429	10	0	0
T90	0	29	0	0
T96	0	27	0	0
T98	0	9	0	0