Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	677731	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

251554

1

T2

11

T3

12

T4

2615

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	782007	1			T1	1		T2	1		T3	1
values[0x0]	73071	1			T1	6		T2	16		T3	21
values[0x1]	74207	1			T1	2		T2	13		T3	18

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	467372	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

461913

1

T1

1

T2

14

T3

14

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2259	1			T4	22		T5	49		T6	18
valid_sources[0x01]	2510	1			T4	22		T5	47		T6	15
valid_sources[0x02]	2505	1			T4	44		T5	33		T6	21
valid_sources[0x03]	2295	1			T4	25		T5	53		T6	20
valid_sources[0x04]	2587	1			T4	18		T5	50		T6	30
valid_sources[0x05]	2500	1			T4	26		T5	51		T6	19
valid_sources[0x06]	2485	1			T4	42		T5	63		T6	22
valid_sources[0x07]	2451	1			T4	16		T5	26		T6	20
valid_sources[0x08]	2532	1			T4	25		T5	51		T6	24
valid_sources[0x09]	2571	1			T4	30		T5	60		T6	23
valid_sources[0x0a]	2510	1			T4	29		T5	47		T6	17
valid_sources[0x0b]	10604	1			T4	15		T5	55		T6	31
valid_sources[0x0c]	2473	1			T4	36		T5	60		T6	24
valid_sources[0x0d]	2401	1			T4	21		T5	59		T6	34
valid_sources[0x0e]	2584	1			T4	48		T5	43		T6	8
valid_sources[0x0f]	2576	1			T4	25		T5	48		T17	23
valid_sources[0x10]	2884	1			T2	1		T4	26		T5	55
valid_sources[0x11]	2476	1			T4	38		T5	35		T6	19
valid_sources[0x12]	2401	1			T4	32		T5	47		T6	19
valid_sources[0x13]	2364	1			T4	20		T5	59		T6	17
valid_sources[0x14]	2525	1			T4	32		T5	70		T6	33
valid_sources[0x15]	2528	1			T4	35		T5	45		T6	15
valid_sources[0x16]	2553	1			T4	23		T5	45		T6	26
valid_sources[0x17]	2259	1			T4	23		T5	47		T6	15
valid_sources[0x18]	10183	1			T4	24		T5	44		T6	20
valid_sources[0x19]	2434	1			T4	21		T5	52		T6	16
valid_sources[0x1a]	7169	1			T4	34		T5	42		T6	25
valid_sources[0x1b]	2378	1			T4	36		T5	44		T6	24
valid_sources[0x1c]	2447	1			T4	29		T5	29		T6	34
valid_sources[0x1d]	2346	1			T4	33		T5	47		T6	25
valid_sources[0x1e]	2733	1			T4	23		T5	41		T6	22
valid_sources[0x1f]	2328	1			T4	23		T5	49		T6	25
valid_sources[0x20]	2219	1			T2	4		T4	42		T5	54
valid_sources[0x21]	2324	1			T4	33		T5	50		T6	24
valid_sources[0x22]	2584	1			T4	25		T5	30		T6	20
valid_sources[0x23]	2483	1			T2	3		T4	25		T5	44
valid_sources[0x24]	2486	1			T4	27		T5	55		T6	19
valid_sources[0x25]	3041	1			T4	42		T5	66		T6	21
valid_sources[0x26]	12430	1			T4	20		T5	59		T6	24
valid_sources[0x27]	2243	1			T4	31		T5	42		T6	23
valid_sources[0x28]	2292	1			T4	29		T5	38		T6	16
valid_sources[0x29]	2558	1			T4	34		T5	51		T6	22
valid_sources[0x2a]	2299	1			T4	26		T5	44		T6	18
valid_sources[0x2b]	2232	1			T4	28		T5	41		T6	28
valid_sources[0x2c]	2494	1			T4	30		T5	63		T6	22
valid_sources[0x2d]	2744	1			T4	33		T5	55		T6	12
valid_sources[0x2e]	2426	1			T4	28		T5	52		T6	19
valid_sources[0x2f]	4741	1			T4	13		T5	95		T6	19
valid_sources[0x30]	2322	1			T1	6		T4	18		T5	52
valid_sources[0x31]	2617	1			T4	27		T5	54		T6	22
valid_sources[0x32]	2481	1			T4	21		T5	68		T6	30
valid_sources[0x33]	2688	1			T4	36		T5	37		T6	21
valid_sources[0x34]	2474	1			T4	28		T5	59		T6	18
valid_sources[0x35]	2340	1			T4	38		T5	38		T6	24
valid_sources[0x36]	2398	1			T4	22		T5	38		T6	21
valid_sources[0x37]	2372	1			T4	16		T5	38		T6	22
valid_sources[0x38]	2472	1			T4	23		T5	77		T6	23
valid_sources[0x39]	2250	1			T4	24		T5	62		T6	21
valid_sources[0x3a]	2369	1			T4	30		T5	48		T6	22
valid_sources[0x3b]	8116	1			T4	34		T5	45		T6	13
valid_sources[0x3c]	2469	1			T4	28		T5	32		T6	7
valid_sources[0x3d]	2393	1			T4	21		T5	62		T6	24
valid_sources[0x3e]	2617	1			T4	21		T5	51		T6	15
valid_sources[0x3f]	2449	1			T4	32		T5	55		T6	20
valid_sources[0x40]	2291	1			T4	19		T5	44		T6	21
valid_sources[0x41]	2335	1			T4	22		T5	51		T6	22
valid_sources[0x42]	2372	1			T4	23		T5	48		T6	16
valid_sources[0x43]	2430	1			T4	37		T5	47		T6	26
valid_sources[0x44]	3874	1			T4	14		T5	55		T6	22
valid_sources[0x45]	110737	1			T4	41		T5	57		T6	32
valid_sources[0x46]	2672	1			T4	13		T5	58		T6	22
valid_sources[0x47]	6953	1			T4	30		T5	53		T6	22
valid_sources[0x48]	2403	1			T4	28		T5	50		T6	15
valid_sources[0x49]	2376	1			T4	35		T5	52		T6	17
valid_sources[0x4a]	2366	1			T4	33		T5	70		T6	23
valid_sources[0x4b]	2578	1			T4	27		T5	34		T6	23
valid_sources[0x4c]	2410	1			T4	18		T5	36		T6	26
valid_sources[0x4d]	2577	1			T4	30		T5	29		T6	20
valid_sources[0x4e]	2633	1			T3	40		T4	23		T5	52
valid_sources[0x4f]	2633	1			T4	27		T5	50		T6	23
valid_sources[0x50]	2148	1			T4	29		T5	36		T6	23
valid_sources[0x51]	2751	1			T4	19		T5	51		T6	18
valid_sources[0x52]	2248	1			T4	27		T5	45		T6	23
valid_sources[0x53]	6046	1			T4	27		T5	31		T6	26
valid_sources[0x54]	2444	1			T4	28		T5	57		T6	18
valid_sources[0x55]	2663	1			T4	37		T5	49		T6	29
valid_sources[0x56]	2319	1			T4	24		T5	46		T6	18
valid_sources[0x57]	2366	1			T4	32		T5	57		T6	17
valid_sources[0x58]	2371	1			T4	13		T5	39		T6	14
valid_sources[0x59]	2612	1			T4	26		T5	61		T6	25
valid_sources[0x5a]	2340	1			T4	31		T5	51		T6	19
valid_sources[0x5b]	2480	1			T2	2		T4	39		T5	58
valid_sources[0x5c]	2563	1			T4	27		T5	52		T6	17
valid_sources[0x5d]	2712	1			T4	20		T5	44		T6	16
valid_sources[0x5e]	2346	1			T4	12		T5	48		T6	24
valid_sources[0x5f]	2409	1			T4	27		T5	75		T6	31
valid_sources[0x60]	2638	1			T4	34		T5	53		T6	19
valid_sources[0x61]	2250	1			T4	34		T5	62		T6	17
valid_sources[0x62]	2352	1			T4	19		T5	44		T6	26
valid_sources[0x63]	2512	1			T4	15		T5	32		T6	23
valid_sources[0x64]	2334	1			T4	20		T5	47		T6	17
valid_sources[0x65]	2429	1			T4	23		T5	48		T6	30
valid_sources[0x66]	2571	1			T4	21		T5	50		T6	23
valid_sources[0x67]	2456	1			T4	31		T5	61		T6	26
valid_sources[0x68]	2687	1			T4	14		T5	56		T6	20
valid_sources[0x69]	2370	1			T4	35		T5	31		T6	32
valid_sources[0x6a]	2884	1			T4	27		T5	46		T6	33
valid_sources[0x6b]	2418	1			T4	28		T5	52		T6	34
valid_sources[0x6c]	2325	1			T4	24		T5	41		T6	25
valid_sources[0x6d]	2393	1			T4	16		T5	42		T6	21
valid_sources[0x6e]	2308	1			T4	22		T5	52		T6	23
valid_sources[0x6f]	2549	1			T4	27		T5	61		T6	19
valid_sources[0x70]	2411	1			T4	26		T5	37		T6	25
valid_sources[0x71]	2287	1			T4	20		T5	51		T6	13
valid_sources[0x72]	2667	1			T4	19		T5	52		T6	11
valid_sources[0x73]	6968	1			T4	27		T5	64		T6	19
valid_sources[0x74]	2476	1			T4	21		T5	44		T6	22
valid_sources[0x75]	2626	1			T4	20		T5	44		T6	17
valid_sources[0x76]	2450	1			T4	19		T5	37		T6	14
valid_sources[0x77]	2304	1			T4	16		T5	41		T6	27
valid_sources[0x78]	13508	1			T4	30		T5	39		T6	22
valid_sources[0x79]	4275	1			T4	21		T5	55		T6	15
valid_sources[0x7a]	11865	1			T4	21		T5	32		T6	25
valid_sources[0x7b]	2417	1			T4	28		T5	60		T6	14
valid_sources[0x7c]	23870	1			T4	19		T5	59		T6	13
valid_sources[0x7d]	2301	1			T4	25		T5	44		T6	21
valid_sources[0x7e]	2369	1			T4	32		T5	35		T6	16
valid_sources[0x7f]	2521	1			T4	14		T5	42		T6	27
valid_sources[0x80]	2505	1			T4	16		T5	53		T6	22

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

138673

1

T3

1

T4

1715

T5

1566

values[0x0]

all_enables

biggest_size

59911

1

T2

6

T3

9

T4

498

values[0x1]

all_enables

biggest_size

52970

1

T2

5

T3

2

T4

402