Group : dv_base_reg_pkg::dv_base_lockable_field_cov::regwen_val_when_new_value_written_cg
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Group : dv_base_reg_pkg::dv_base_lockable_field_cov::regwen_val_when_new_value_written_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
50.00 48.21 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_dv_base_reg_0/dv_base_lockable_field_cov.sv

28 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
lockable_field_cov_of_keymgr_dpe_reg_block.start.en 0.00 1 100 1 64 64
lockable_field_cov_of_keymgr_dpe_reg_block.control_shadowed.dest_sel 50.00 1 100 1 64 64
lockable_field_cov_of_keymgr_dpe_reg_block.control_shadowed.operation 50.00 1 100 1 64 64
lockable_field_cov_of_keymgr_dpe_reg_block.control_shadowed.slot_dst_sel 50.00 1 100 1 64 64
lockable_field_cov_of_keymgr_dpe_reg_block.control_shadowed.slot_src_sel 50.00 1 100 1 64 64
lockable_field_cov_of_keymgr_dpe_reg_block.key_version.val_0 50.00 1 100 1 64 64
lockable_field_cov_of_keymgr_dpe_reg_block.max_key_ver_shadowed.val 50.00 1 100 1 64 64
lockable_field_cov_of_keymgr_dpe_reg_block.reseed_interval_shadowed.val 50.00 1 100 1 64 64
lockable_field_cov_of_keymgr_dpe_reg_block.salt_0.val_0 50.00 1 100 1 64 64
lockable_field_cov_of_keymgr_dpe_reg_block.salt_1.val_0 50.00 1 100 1 64 64
lockable_field_cov_of_keymgr_dpe_reg_block.salt_2.val_0 50.00 1 100 1 64 64
lockable_field_cov_of_keymgr_dpe_reg_block.salt_3.val_0 50.00 1 100 1 64 64
lockable_field_cov_of_keymgr_dpe_reg_block.salt_4.val_0 50.00 1 100 1 64 64
lockable_field_cov_of_keymgr_dpe_reg_block.salt_5.val_0 50.00 1 100 1 64 64
lockable_field_cov_of_keymgr_dpe_reg_block.salt_6.val_0 50.00 1 100 1 64 64
lockable_field_cov_of_keymgr_dpe_reg_block.salt_7.val_0 50.00 1 100 1 64 64
lockable_field_cov_of_keymgr_dpe_reg_block.sideload_clear.val 50.00 1 100 1 64 64
lockable_field_cov_of_keymgr_dpe_reg_block.slot_policy.allow_child 50.00 1 100 1 64 64
lockable_field_cov_of_keymgr_dpe_reg_block.slot_policy.exportable 50.00 1 100 1 64 64
lockable_field_cov_of_keymgr_dpe_reg_block.slot_policy.retain_parent 50.00 1 100 1 64 64
lockable_field_cov_of_keymgr_dpe_reg_block.sw_binding_0.val_0 50.00 1 100 1 64 64
lockable_field_cov_of_keymgr_dpe_reg_block.sw_binding_1.val_0 50.00 1 100 1 64 64
lockable_field_cov_of_keymgr_dpe_reg_block.sw_binding_2.val_0 50.00 1 100 1 64 64
lockable_field_cov_of_keymgr_dpe_reg_block.sw_binding_3.val_0 50.00 1 100 1 64 64
lockable_field_cov_of_keymgr_dpe_reg_block.sw_binding_4.val_0 50.00 1 100 1 64 64
lockable_field_cov_of_keymgr_dpe_reg_block.sw_binding_5.val_0 50.00 1 100 1 64 64
lockable_field_cov_of_keymgr_dpe_reg_block.sw_binding_6.val_0 50.00 1 100 1 64 64
lockable_field_cov_of_keymgr_dpe_reg_block.sw_binding_7.val_0 50.00 1 100 1 64 64




Group Instance : lockable_field_cov_of_keymgr_dpe_reg_block.start.en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
0.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_dpe_reg_block.start.en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 2 0 0.00


Variables for Group Instance lockable_field_cov_of_keymgr_dpe_reg_block.start.en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 2 0 0.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_dpe_reg_block.control_shadowed.dest_sel
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_dpe_reg_block.control_shadowed.dest_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance lockable_field_cov_of_keymgr_dpe_reg_block.control_shadowed.dest_sel
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 1 1 50.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_dpe_reg_block.control_shadowed.operation
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_dpe_reg_block.control_shadowed.operation

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance lockable_field_cov_of_keymgr_dpe_reg_block.control_shadowed.operation
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 1 1 50.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_dpe_reg_block.control_shadowed.slot_dst_sel
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_dpe_reg_block.control_shadowed.slot_dst_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance lockable_field_cov_of_keymgr_dpe_reg_block.control_shadowed.slot_dst_sel
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 1 1 50.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_dpe_reg_block.control_shadowed.slot_src_sel
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_dpe_reg_block.control_shadowed.slot_src_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance lockable_field_cov_of_keymgr_dpe_reg_block.control_shadowed.slot_src_sel
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 1 1 50.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_dpe_reg_block.key_version.val_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_dpe_reg_block.key_version.val_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance lockable_field_cov_of_keymgr_dpe_reg_block.key_version.val_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 1 1 50.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_dpe_reg_block.max_key_ver_shadowed.val
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_dpe_reg_block.max_key_ver_shadowed.val

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance lockable_field_cov_of_keymgr_dpe_reg_block.max_key_ver_shadowed.val
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 1 1 50.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_dpe_reg_block.reseed_interval_shadowed.val
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_dpe_reg_block.reseed_interval_shadowed.val

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance lockable_field_cov_of_keymgr_dpe_reg_block.reseed_interval_shadowed.val
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 1 1 50.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_dpe_reg_block.salt_0.val_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_dpe_reg_block.salt_0.val_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance lockable_field_cov_of_keymgr_dpe_reg_block.salt_0.val_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 1 1 50.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_dpe_reg_block.salt_1.val_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_dpe_reg_block.salt_1.val_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance lockable_field_cov_of_keymgr_dpe_reg_block.salt_1.val_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 1 1 50.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_dpe_reg_block.salt_2.val_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_dpe_reg_block.salt_2.val_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance lockable_field_cov_of_keymgr_dpe_reg_block.salt_2.val_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 1 1 50.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_dpe_reg_block.salt_3.val_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_dpe_reg_block.salt_3.val_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance lockable_field_cov_of_keymgr_dpe_reg_block.salt_3.val_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 1 1 50.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_dpe_reg_block.salt_4.val_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_dpe_reg_block.salt_4.val_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance lockable_field_cov_of_keymgr_dpe_reg_block.salt_4.val_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 1 1 50.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_dpe_reg_block.salt_5.val_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_dpe_reg_block.salt_5.val_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance lockable_field_cov_of_keymgr_dpe_reg_block.salt_5.val_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 1 1 50.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_dpe_reg_block.salt_6.val_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_dpe_reg_block.salt_6.val_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance lockable_field_cov_of_keymgr_dpe_reg_block.salt_6.val_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 1 1 50.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_dpe_reg_block.salt_7.val_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_dpe_reg_block.salt_7.val_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance lockable_field_cov_of_keymgr_dpe_reg_block.salt_7.val_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 1 1 50.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_dpe_reg_block.sideload_clear.val
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_dpe_reg_block.sideload_clear.val

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance lockable_field_cov_of_keymgr_dpe_reg_block.sideload_clear.val
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 1 1 50.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_dpe_reg_block.slot_policy.allow_child
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_dpe_reg_block.slot_policy.allow_child

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance lockable_field_cov_of_keymgr_dpe_reg_block.slot_policy.allow_child
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 1 1 50.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_dpe_reg_block.slot_policy.exportable
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_dpe_reg_block.slot_policy.exportable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance lockable_field_cov_of_keymgr_dpe_reg_block.slot_policy.exportable
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 1 1 50.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_dpe_reg_block.slot_policy.retain_parent
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_dpe_reg_block.slot_policy.retain_parent

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance lockable_field_cov_of_keymgr_dpe_reg_block.slot_policy.retain_parent
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 1 1 50.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_dpe_reg_block.sw_binding_0.val_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_dpe_reg_block.sw_binding_0.val_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance lockable_field_cov_of_keymgr_dpe_reg_block.sw_binding_0.val_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 1 1 50.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_dpe_reg_block.sw_binding_1.val_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_dpe_reg_block.sw_binding_1.val_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance lockable_field_cov_of_keymgr_dpe_reg_block.sw_binding_1.val_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 1 1 50.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_dpe_reg_block.sw_binding_2.val_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_dpe_reg_block.sw_binding_2.val_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance lockable_field_cov_of_keymgr_dpe_reg_block.sw_binding_2.val_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 1 1 50.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_dpe_reg_block.sw_binding_3.val_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_dpe_reg_block.sw_binding_3.val_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance lockable_field_cov_of_keymgr_dpe_reg_block.sw_binding_3.val_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 1 1 50.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_dpe_reg_block.sw_binding_4.val_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_dpe_reg_block.sw_binding_4.val_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance lockable_field_cov_of_keymgr_dpe_reg_block.sw_binding_4.val_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 1 1 50.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_dpe_reg_block.sw_binding_5.val_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_dpe_reg_block.sw_binding_5.val_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance lockable_field_cov_of_keymgr_dpe_reg_block.sw_binding_5.val_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 1 1 50.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_dpe_reg_block.sw_binding_6.val_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_dpe_reg_block.sw_binding_6.val_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance lockable_field_cov_of_keymgr_dpe_reg_block.sw_binding_6.val_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 1 1 50.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_dpe_reg_block.sw_binding_7.val_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_dpe_reg_block.sw_binding_7.val_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance lockable_field_cov_of_keymgr_dpe_reg_block.sw_binding_7.val_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 1 1 50.00 100 1 1 2


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0] - auto[1]] -- -- 2


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1153 1 T37 3 T49 7 T39 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1308 1 T37 3 T49 7 T39 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1131 1 T37 2 T49 7 T39 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1196 1 T37 3 T49 7 T39 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1626 1 T37 15 T39 1 T66 30


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1480 1 T37 5 T49 6 T39 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1436 1 T37 6 T49 7 T39 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1617 1 T37 15 T39 1 T66 30


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1652 1 T37 15 T39 1 T66 30


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1627 1 T37 15 T39 1 T66 30


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1643 1 T37 15 T39 1 T66 30


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1652 1 T37 15 T39 1 T66 30


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1642 1 T37 15 T39 1 T66 30


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1616 1 T37 15 T39 1 T66 30


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1650 1 T37 15 T39 1 T66 30


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1579 1 T37 15 T39 1 T66 28


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1229 1 T37 10 T66 18 T67 26


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1292 1 T37 11 T39 1 T66 24


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1163 1 T37 12 T39 1 T66 26


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1610 1 T37 15 T39 1 T66 30


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1611 1 T37 15 T39 1 T66 30


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1665 1 T37 15 T39 1 T66 30


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1678 1 T37 15 T39 1 T66 30


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1626 1 T37 15 T39 1 T66 30


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1606 1 T37 15 T39 1 T66 30


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1601 1 T37 15 T39 1 T66 30


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1593 1 T37 15 T39 1 T66 30

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%