Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	941251	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

241571

1

T1

2394

T2

2441

T3

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1042240	1			T1	15243		T2	24642		T3	1
values[0x0]	69640	1			T1	603		T2	591		T3	3
values[0x1]	70942	1			T1	534		T2	577		T3	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	643665	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

539157

1

T1

6775

T2

9933

T3

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2857	1			T4	2		T7	52		T13	233
valid_sources[0x01]	2938	1			T4	12		T7	57		T69	1
valid_sources[0x02]	3007	1			T4	6		T7	58		T13	236
valid_sources[0x03]	3033	1			T4	27		T7	74		T13	187
valid_sources[0x04]	2809	1			T4	21		T7	60		T13	219
valid_sources[0x05]	3160	1			T4	3		T7	54		T13	196
valid_sources[0x06]	3046	1			T4	5		T7	77		T13	209
valid_sources[0x07]	3049	1			T7	83		T13	199		T14	32
valid_sources[0x08]	2819	1			T4	2		T7	59		T13	213
valid_sources[0x09]	2998	1			T4	10		T7	71		T13	205
valid_sources[0x0a]	8118	1			T4	9		T7	49		T10	5124
valid_sources[0x0b]	4076	1			T4	2		T7	68		T13	207
valid_sources[0x0c]	2612	1			T4	19		T7	76		T13	205
valid_sources[0x0d]	3222	1			T4	15		T7	81		T13	196
valid_sources[0x0e]	2724	1			T15	1		T4	10		T7	59
valid_sources[0x0f]	3118	1			T4	4		T7	73		T13	182
valid_sources[0x10]	2798	1			T4	39		T7	46		T13	207
valid_sources[0x11]	2726	1			T4	2		T7	68		T13	215
valid_sources[0x12]	3105	1			T4	12		T7	81		T13	203
valid_sources[0x13]	3035	1			T4	2		T7	63		T13	217
valid_sources[0x14]	2833	1			T4	1		T7	54		T13	188
valid_sources[0x15]	2611	1			T7	52		T13	201		T14	42
valid_sources[0x16]	2658	1			T4	4		T7	57		T13	193
valid_sources[0x17]	3074	1			T4	25		T7	54		T13	240
valid_sources[0x18]	8548	1			T1	5794		T4	12		T7	42
valid_sources[0x19]	2716	1			T4	7		T7	67		T13	220
valid_sources[0x1a]	3172	1			T7	45		T13	190		T14	32
valid_sources[0x1b]	2697	1			T4	18		T7	50		T13	207
valid_sources[0x1c]	2796	1			T4	11		T7	43		T31	1
valid_sources[0x1d]	2663	1			T4	6		T7	67		T13	180
valid_sources[0x1e]	4034	1			T4	5		T7	67		T10	1146
valid_sources[0x1f]	2927	1			T4	2		T7	68		T13	183
valid_sources[0x20]	2916	1			T4	23		T7	52		T31	1
valid_sources[0x21]	3084	1			T4	13		T7	50		T69	1
valid_sources[0x22]	2674	1			T4	1		T7	59		T13	196
valid_sources[0x23]	15068	1			T2	1484		T15	2		T4	11
valid_sources[0x24]	3005	1			T4	6		T7	59		T13	207
valid_sources[0x25]	2665	1			T4	21		T7	84		T13	206
valid_sources[0x26]	3126	1			T4	11		T7	77		T13	210
valid_sources[0x27]	10466	1			T2	7514		T4	15		T7	50
valid_sources[0x28]	3120	1			T4	3		T7	55		T13	203
valid_sources[0x29]	2931	1			T4	4		T7	58		T69	1
valid_sources[0x2a]	2755	1			T15	2		T4	13		T7	76
valid_sources[0x2b]	2850	1			T4	16		T7	73		T13	203
valid_sources[0x2c]	2902	1			T4	20		T7	72		T68	1
valid_sources[0x2d]	3819	1			T4	11		T7	69		T10	925
valid_sources[0x2e]	2728	1			T4	9		T7	59		T13	221
valid_sources[0x2f]	2735	1			T4	2		T7	76		T13	219
valid_sources[0x30]	2990	1			T4	9		T7	68		T13	210
valid_sources[0x31]	3240	1			T4	4		T7	87		T13	195
valid_sources[0x32]	2967	1			T4	10		T7	47		T13	226
valid_sources[0x33]	3123	1			T4	1		T7	58		T13	205
valid_sources[0x34]	2766	1			T4	19		T7	58		T13	155
valid_sources[0x35]	2893	1			T4	10		T7	65		T13	218
valid_sources[0x36]	3021	1			T4	13		T7	54		T13	186
valid_sources[0x37]	2531	1			T7	77		T13	194		T14	28
valid_sources[0x38]	2989	1			T4	4		T7	62		T13	192
valid_sources[0x39]	3118	1			T4	2		T7	47		T31	1
valid_sources[0x3a]	2785	1			T4	6		T7	58		T13	211
valid_sources[0x3b]	3227	1			T4	2		T7	51		T13	236
valid_sources[0x3c]	2878	1			T4	7		T7	68		T13	196
valid_sources[0x3d]	2977	1			T4	16		T7	87		T13	235
valid_sources[0x3e]	2806	1			T4	11		T7	43		T13	202
valid_sources[0x3f]	2909	1			T15	4		T4	6		T7	57
valid_sources[0x40]	2738	1			T4	5		T7	66		T31	2
valid_sources[0x41]	12009	1			T7	66		T10	9496		T13	169
valid_sources[0x42]	2948	1			T4	9		T7	57		T13	205
valid_sources[0x43]	3213	1			T4	3		T7	64		T13	212
valid_sources[0x44]	27058	1			T4	1		T7	65		T11	23957
valid_sources[0x45]	2765	1			T4	15		T7	64		T13	188
valid_sources[0x46]	2886	1			T4	9		T7	61		T68	2
valid_sources[0x47]	2848	1			T4	4		T7	57		T31	1
valid_sources[0x48]	8619	1			T4	15		T7	57		T11	5633
valid_sources[0x49]	2631	1			T4	11		T7	82		T13	172
valid_sources[0x4a]	2920	1			T4	9		T7	47		T13	211
valid_sources[0x4b]	3634	1			T1	750		T4	5		T7	59
valid_sources[0x4c]	3264	1			T4	10		T7	56		T13	191
valid_sources[0x4d]	2783	1			T4	10		T7	61		T13	217
valid_sources[0x4e]	2869	1			T7	88		T13	193		T14	17
valid_sources[0x4f]	2796	1			T4	12		T7	44		T13	193
valid_sources[0x50]	2652	1			T4	7		T7	62		T13	240
valid_sources[0x51]	2843	1			T7	52		T31	1		T13	192
valid_sources[0x52]	2961	1			T4	5		T7	53		T13	210
valid_sources[0x53]	2726	1			T15	1		T4	12		T7	79
valid_sources[0x54]	2884	1			T4	12		T7	65		T69	1
valid_sources[0x55]	20852	1			T4	4		T7	64		T9	17662
valid_sources[0x56]	2661	1			T4	4		T7	37		T13	245
valid_sources[0x57]	2650	1			T4	2		T7	38		T13	194
valid_sources[0x58]	2956	1			T4	1		T7	63		T13	189
valid_sources[0x59]	2716	1			T4	17		T7	45		T13	185
valid_sources[0x5a]	2802	1			T15	1		T4	17		T7	72
valid_sources[0x5b]	2508	1			T4	6		T7	70		T13	192
valid_sources[0x5c]	3092	1			T4	9		T7	52		T13	213
valid_sources[0x5d]	2708	1			T4	22		T7	71		T13	204
valid_sources[0x5e]	18417	1			T2	15617		T4	11		T7	61
valid_sources[0x5f]	2791	1			T4	4		T7	41		T13	203
valid_sources[0x60]	2775	1			T4	18		T7	64		T13	178
valid_sources[0x61]	2705	1			T4	6		T7	50		T13	237
valid_sources[0x62]	3149	1			T4	13		T7	59		T13	197
valid_sources[0x63]	2714	1			T4	1		T7	89		T13	216
valid_sources[0x64]	2862	1			T4	19		T7	59		T34	1
valid_sources[0x65]	3058	1			T4	18		T7	66		T13	182
valid_sources[0x66]	2733	1			T4	31		T7	64		T13	206
valid_sources[0x67]	2782	1			T4	7		T7	61		T13	204
valid_sources[0x68]	2852	1			T7	44		T13	233		T14	28
valid_sources[0x69]	2660	1			T4	9		T7	42		T13	206
valid_sources[0x6a]	3213	1			T4	7		T7	52		T13	186
valid_sources[0x6b]	2889	1			T4	21		T7	57		T13	191
valid_sources[0x6c]	2700	1			T4	5		T7	53		T13	197
valid_sources[0x6d]	2963	1			T4	4		T7	60		T13	229
valid_sources[0x6e]	2989	1			T3	1		T15	3		T4	1
valid_sources[0x6f]	3186	1			T4	3		T7	86		T13	211
valid_sources[0x70]	2786	1			T15	1		T4	9		T7	65
valid_sources[0x71]	20311	1			T4	26		T7	70		T12	17441
valid_sources[0x72]	2658	1			T4	6		T7	68		T31	1
valid_sources[0x73]	9413	1			T4	8		T7	67		T13	201
valid_sources[0x74]	2886	1			T4	16		T7	73		T13	213
valid_sources[0x75]	3037	1			T15	1		T4	12		T7	60
valid_sources[0x76]	3025	1			T4	3		T7	73		T13	178
valid_sources[0x77]	2795	1			T4	3		T7	63		T13	225
valid_sources[0x78]	2648	1			T4	5		T7	50		T13	215
valid_sources[0x79]	2783	1			T4	20		T7	64		T13	222
valid_sources[0x7a]	3136	1			T4	14		T7	86		T13	218
valid_sources[0x7b]	2872	1			T4	14		T7	67		T13	195
valid_sources[0x7c]	2830	1			T4	9		T7	69		T13	218
valid_sources[0x7d]	3744	1			T4	26		T7	51		T13	179
valid_sources[0x7e]	3215	1			T4	16		T7	41		T24	5
valid_sources[0x7f]	2832	1			T4	8		T7	74		T13	234
valid_sources[0x80]	3311	1			T4	4		T7	56		T69	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

133727

1

T1

1607

T2

1629

T15

1

values[0x0]

all_enables

biggest_size

57374

1

T1

459

T2

457

T3

1

values[0x1]

all_enables

biggest_size

50470

1

T1

328

T2

355

T3

1