Unified Coverage Report :: Module :: keymgr_sideload_key_ctrl

Module : keymgr_sideload_key_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
76.51	90.00	75.86		33.33	83.33	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_common_0.1/rtl/keymgr_sideload_key_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sideload_ctrl	76.51	90.00	75.86		33.33	83.33	100.00

---

Module Instance : tb.dut.u_sideload_ctrl

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
76.51	90.00	75.86		33.33	83.33	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.42	96.30	75.47		33.33	92.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.39	100.00	80.22	53.88		97.83	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_aes_key	91.67	100.00	75.00			100.00
u_kmac_key	91.67	100.00	75.00			100.00
u_mubi_buf	100.00	100.00					100.00
u_otbn_key	91.67	100.00	75.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : keymgr_sideload_key_ctrl

	Line No.	Total	Covered	Percent
TOTAL		50	45	90.00
ALWAYS	65	3	3	100.00
CONT_ASSIGN	70	1	1	100.00
CONT_ASSIGN	70	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
ALWAYS	91	13	8	61.54
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
ALWAYS	192	6	6	100.00
ALWAYS	192	6	6	100.00
ALWAYS	192	6	6	100.00
CONT_ASSIGN	204	1	1	100.00
CONT_ASSIGN	205	1	1	100.00
CONT_ASSIGN	206	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	216	1	1	100.00
CONT_ASSIGN	219	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_common_0.1/rtl/keymgr_sideload_key_ctrl.sv' or '../src/lowrisc_ip_keymgr_common_0.1/rtl/keymgr_sideload_key_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	3	3
70	2	2
77	1	1
83	1	1
84	1	1
85	1	1
88	1	1
91	1	1
92	1	1
93	1	1
95	1	1
97	1	1
98	1	1
			MISSING_ELSE
105	1	1
106	1	1
107	0	1
			MISSING_ELSE
112	0	1
113	0	1
114	0	1
			==> MISSING_ELSE
120	0	1
143	1	1
144	1	1
145	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
213	1	1
216	1	1
219	1	1

---

Cond Coverage for Module : keymgr_sideload_key_ctrl

	Total	Covered	Percent
Conditions	29	22	75.86
Logical	29	22	75.86
Non-Logical	0	0
Event	0	0

 LINE       77
 EXPRESSION (wipe_key_i | ((!(clr_key_i inside {SideLoadClrIdle, SideLoadClrAes, SideLoadClrKmac, SideLoadClrOtbn}))))
             -----1----   ---------------------------------------------2---------------------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T4,T5,T6

 LINE       83
 EXPRESSION (clr_all_keys | (clr_key_i == SideLoadClrAes))
             ------1-----   --------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T4,T5,T6

 LINE       83
 SUB-EXPRESSION (clr_key_i == SideLoadClrAes)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (clr_all_keys | (clr_key_i == SideLoadClrKmac))
             ------1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T4,T5,T6

 LINE       84
 SUB-EXPRESSION (clr_key_i == SideLoadClrKmac)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       85
 EXPRESSION (clr_all_keys | (clr_key_i == SideLoadClrOtbn))
             ------1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T4,T5,T6

 LINE       85
 SUB-EXPRESSION (clr_key_i == SideLoadClrOtbn)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       147
 EXPRESSION (data_valid_i & slot_sel[AesIdx])
             ------1-----   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T7

 LINE       162
 EXPRESSION (data_valid_i & slot_sel[OtbnIdx])
             ------1-----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T7

 LINE       176
 EXPRESSION (data_valid_i & slot_sel[KmacIdx])
             ------1-----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       216
 EXPRESSION (key_i.valid ? key_i : kmac_sideload_key)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

---

FSM Coverage for Module : keymgr_sideload_key_ctrl

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	2	50.00	(Not included in score)
Transitions	3	1	33.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StSideloadIdle	98	Covered	T1,T2,T7
StSideloadReset	96	Covered	T1,T2,T3
StSideloadStop	114	Not Covered
StSideloadWipe	107	Not Covered

transitions	Line No.	Covered	Tests
StSideloadIdle->StSideloadWipe	107	Not Covered
StSideloadReset->StSideloadIdle	98	Covered	T1,T2,T7
StSideloadWipe->StSideloadStop	114	Not Covered

---

Branch Coverage for Module : keymgr_sideload_key_ctrl

	Line No.	Total	Covered	Percent
Branches		24	20	83.33
TERNARY	216	2	2	100.00
IF	65	2	2	100.00
CASE	95	8	4	50.00
IF	192	4	4	100.00
IF	192	4	4	100.00
IF	192	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_common_0.1/rtl/keymgr_sideload_key_ctrl.sv' or '../src/lowrisc_ip_keymgr_common_0.1/rtl/keymgr_sideload_key_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	216	(key_i.valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	65	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	95	case (state_q)
-2-:	97	if (init_i)
-3-:	106	if (wipe_key_i)
-4-:	113	if ((!wipe_key_i))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
StSideloadReset	1	-	-	Covered	T1,T2,T7
StSideloadReset	0	-	-	Covered	T1,T2,T3
StSideloadIdle	-	1	-	Not Covered
StSideloadIdle	-	0	-	Covered	T1,T2,T7
StSideloadWipe	-	-	1	Not Covered
StSideloadWipe	-	-	0	Not Covered
StSideloadStop	-	-	-	Not Covered
default	-	-	-	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	192	if ((!rst_ni))
-2-:	194	if (slot_clr[0])
-3-:	196	if (slot_sel[0])

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T5,T6
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	192	if ((!rst_ni))
-2-:	194	if (slot_clr[1])
-3-:	196	if (slot_sel[1])

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T5,T6
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	192	if ((!rst_ni))
-2-:	194	if (slot_clr[2])
-3-:	196	if (slot_sel[2])

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T5,T6
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : keymgr_sideload_key_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
KmacKeySource_a	7831697	3139	0	0
u_state_regs_A	7919067	7843849	0	0

KmacKeySource_a

Name	Attempts	Real Successes	Failures	Incomplete
Total	7831697	3139	0	0
T1	209870	57	0	0
T2	77954	103	0	0
T3	1138	0	0	0
T4	39726	0	0	0
T7	130580	18	0	0
T8	960766	62	0	0
T9	0	27	0	0
T10	0	31	0	0
T11	0	53	0	0
T12	0	59	0	0
T13	0	95	0	0
T14	0	46	0	0
T15	1502	0	0	0
T16	791	0	0	0
T17	1282	0	0	0
T18	1042	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7919067	7843849	0	0
T1	209870	209771	0	0
T2	77954	77856	0	0
T3	1138	1038	0	0
T4	60248	46301	0	0
T7	130580	130483	0	0
T8	960766	960711	0	0
T15	1502	1430	0	0
T16	791	701	0	0
T17	1282	1214	0	0
T18	1042	977	0	0