Unified Coverage Report :: Module :: keymgr_dpe_csr_assert_fpv

Module : keymgr_dpe_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_dpe_csr_assert_0/keymgr_dpe_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_dpe_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_dpe_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.39	100.00	80.22	53.88		97.83	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_dpe_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	22	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	22	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	9221962	9867	0	0
intr_enable_rd_A	9221962	1591	0	0
key_version_rd_A	9221962	1643	0	0
reseed_interval_regwen_rd_A	9221962	500	0	0
salt_0_rd_A	9221962	1486	0	0
salt_1_rd_A	9221962	1566	0	0
salt_2_rd_A	9221962	1511	0	0
salt_3_rd_A	9221962	1534	0	0
salt_4_rd_A	9221962	1545	0	0
salt_5_rd_A	9221962	1589	0	0
salt_6_rd_A	9221962	1459	0	0
salt_7_rd_A	9221962	1437	0	0
sideload_clear_rd_A	9221962	1496	0	0
slot_policy_rd_A	9221962	2411	0	0
sw_binding_0_rd_A	9221962	1517	0	0
sw_binding_1_rd_A	9221962	1464	0	0
sw_binding_2_rd_A	9221962	1598	0	0
sw_binding_3_rd_A	9221962	1473	0	0
sw_binding_4_rd_A	9221962	1552	0	0
sw_binding_5_rd_A	9221962	1466	0	0
sw_binding_6_rd_A	9221962	1491	0	0
sw_binding_7_rd_A	9221962	1492	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9221962	9867	0	0
T19	4504	751	0	0
T20	21194	5	0	0
T21	9031	2	0	0
T25	9037	442	0	0
T26	0	4	0	0
T27	9864	522	0	0
T36	0	152	0	0
T37	0	512	0	0
T43	0	3	0	0
T62	6392	0	0	0
T63	9192	0	0	0
T64	13360	0	0	0
T65	2381	5	0	0
T66	1043	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9221962	1591	0	0
T20	21194	85	0	0
T25	9037	10	0	0
T27	9864	8	0	0
T29	24640	120	0	0
T41	1556	8	0	0
T60	6562	2	0	0
T62	6392	0	0	0
T63	9192	0	0	0
T65	0	20	0	0
T66	0	7	0	0
T72	5369	7	0	0
T82	1597	19	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9221962	1643	0	0
T20	21194	103	0	0
T25	9037	26	0	0
T26	0	39	0	0
T27	9864	1	0	0
T28	5282	33	0	0
T29	24640	175	0	0
T60	6562	17	0	0
T62	6392	0	0	0
T63	9192	0	0	0
T64	13360	0	0	0
T65	0	14	0	0
T72	5369	36	0	0
T83	0	6	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9221962	500	0	0
T25	9037	6	0	0
T27	9864	8	0	0
T28	5282	39	0	0
T29	24640	23	0	0
T49	0	5	0	0
T60	6562	12	0	0
T62	6392	0	0	0
T63	9192	0	0	0
T64	13360	0	0	0
T65	2381	7	0	0
T72	5369	21	0	0
T74	0	25	0	0
T84	0	50	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9221962	1486	0	0
T20	21194	78	0	0
T25	9037	4	0	0
T26	0	45	0	0
T27	9864	0	0	0
T28	5282	4	0	0
T29	24640	144	0	0
T49	0	56	0	0
T62	6392	0	0	0
T63	9192	0	0	0
T64	13360	0	0	0
T65	2381	6	0	0
T67	0	33	0	0
T72	5369	18	0	0
T74	0	86	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9221962	1566	0	0
T20	21194	91	0	0
T25	9037	9	0	0
T26	0	48	0	0
T27	9864	14	0	0
T28	5282	15	0	0
T29	24640	155	0	0
T60	6562	9	0	0
T62	6392	0	0	0
T63	9192	0	0	0
T64	13360	0	0	0
T65	0	10	0	0
T72	5369	35	0	0
T83	0	3	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9221962	1511	0	0
T20	21194	75	0	0
T25	9037	15	0	0
T26	0	21	0	0
T27	9864	0	0	0
T28	5282	27	0	0
T29	24640	167	0	0
T60	6562	13	0	0
T62	6392	0	0	0
T63	9192	0	0	0
T64	13360	0	0	0
T65	0	19	0	0
T72	5369	23	0	0
T74	0	80	0	0
T83	0	9	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9221962	1534	0	0
T20	21194	88	0	0
T25	9037	16	0	0
T26	0	52	0	0
T27	9864	9	0	0
T28	5282	14	0	0
T29	24640	113	0	0
T60	6562	15	0	0
T62	6392	0	0	0
T63	9192	0	0	0
T64	13360	0	0	0
T65	0	9	0	0
T72	5369	20	0	0
T74	0	74	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9221962	1545	0	0
T20	21194	72	0	0
T25	9037	17	0	0
T26	0	44	0	0
T27	9864	0	0	0
T28	5282	8	0	0
T29	24640	148	0	0
T49	0	22	0	0
T60	6562	12	0	0
T62	6392	0	0	0
T63	9192	0	0	0
T64	13360	0	0	0
T65	2381	18	0	0
T67	0	36	0	0
T74	0	80	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9221962	1589	0	0
T20	21194	89	0	0
T25	9037	1	0	0
T26	0	54	0	0
T27	9864	0	0	0
T28	5282	32	0	0
T29	24640	130	0	0
T60	6562	10	0	0
T62	6392	0	0	0
T63	9192	0	0	0
T64	13360	0	0	0
T65	0	10	0	0
T72	5369	33	0	0
T74	0	77	0	0
T83	0	4	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9221962	1459	0	0
T20	21194	80	0	0
T25	9037	0	0	0
T26	0	42	0	0
T27	9864	8	0	0
T28	5282	39	0	0
T29	24640	170	0	0
T60	6562	5	0	0
T62	6392	0	0	0
T63	9192	0	0	0
T64	13360	0	0	0
T65	0	9	0	0
T72	5369	27	0	0
T74	0	74	0	0
T83	0	5	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9221962	1437	0	0
T20	21194	76	0	0
T25	9037	7	0	0
T26	0	45	0	0
T27	9864	0	0	0
T28	5282	23	0	0
T29	24640	137	0	0
T60	6562	5	0	0
T62	6392	0	0	0
T63	9192	0	0	0
T64	13360	0	0	0
T65	0	11	0	0
T72	5369	12	0	0
T74	0	56	0	0
T83	0	6	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9221962	1496	0	0
T20	21194	100	0	0
T25	9037	4	0	0
T26	0	35	0	0
T27	9864	8	0	0
T28	5282	30	0	0
T29	24640	115	0	0
T60	6562	6	0	0
T62	6392	0	0	0
T63	9192	0	0	0
T64	13360	0	0	0
T65	0	13	0	0
T72	5369	13	0	0
T74	0	96	0	0

slot_policy_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9221962	2411	0	0
T20	21194	134	0	0
T25	9037	19	0	0
T26	0	90	0	0
T27	9864	0	0	0
T28	5282	25	0	0
T29	24640	271	0	0
T49	0	56	0	0
T62	6392	0	0	0
T63	9192	0	0	0
T64	13360	0	0	0
T65	2381	10	0	0
T67	0	49	0	0
T72	5369	31	0	0
T74	0	111	0	0

sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9221962	1517	0	0
T20	21194	78	0	0
T25	9037	9	0	0
T26	0	50	0	0
T27	9864	6	0	0
T28	5282	8	0	0
T29	24640	126	0	0
T60	6562	10	0	0
T62	6392	0	0	0
T63	9192	0	0	0
T64	13360	0	0	0
T65	0	10	0	0
T72	5369	21	0	0
T74	0	78	0	0

sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9221962	1464	0	0
T20	21194	78	0	0
T25	9037	4	0	0
T26	0	40	0	0
T27	9864	0	0	0
T28	5282	6	0	0
T29	24640	162	0	0
T60	6562	6	0	0
T62	6392	0	0	0
T63	9192	0	0	0
T64	13360	0	0	0
T65	0	13	0	0
T72	5369	18	0	0
T74	0	77	0	0
T83	0	4	0	0

sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9221962	1598	0	0
T20	21194	72	0	0
T25	9037	8	0	0
T26	0	25	0	0
T27	9864	0	0	0
T28	5282	12	0	0
T29	24640	177	0	0
T49	0	34	0	0
T60	6562	6	0	0
T62	6392	0	0	0
T63	9192	0	0	0
T64	13360	0	0	0
T65	0	12	0	0
T72	5369	26	0	0
T74	0	104	0	0

sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9221962	1473	0	0
T20	21194	84	0	0
T25	9037	5	0	0
T26	0	31	0	0
T27	9864	0	0	0
T28	5282	29	0	0
T29	24640	116	0	0
T60	6562	4	0	0
T62	6392	0	0	0
T63	9192	0	0	0
T64	13360	0	0	0
T65	0	5	0	0
T72	5369	18	0	0
T74	0	64	0	0
T83	0	8	0	0

sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9221962	1552	0	0
T20	21194	100	0	0
T25	9037	8	0	0
T26	0	53	0	0
T27	9864	21	0	0
T28	5282	8	0	0
T29	24640	151	0	0
T62	6392	0	0	0
T63	9192	0	0	0
T64	13360	0	0	0
T65	2381	9	0	0
T72	5369	28	0	0
T74	0	94	0	0
T83	0	4	0	0

sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9221962	1466	0	0
T20	21194	88	0	0
T25	9037	10	0	0
T26	0	47	0	0
T27	9864	5	0	0
T28	5282	12	0	0
T29	24640	134	0	0
T60	6562	2	0	0
T62	6392	0	0	0
T63	9192	0	0	0
T64	13360	0	0	0
T65	0	5	0	0
T72	5369	18	0	0
T83	0	9	0	0

sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9221962	1491	0	0
T20	21194	101	0	0
T25	9037	0	0	0
T26	0	49	0	0
T27	9864	0	0	0
T28	5282	8	0	0
T29	24640	188	0	0
T49	0	34	0	0
T60	6562	2	0	0
T62	6392	0	0	0
T63	9192	0	0	0
T64	13360	0	0	0
T65	0	8	0	0
T67	0	41	0	0
T72	5369	2	0	0
T74	0	97	0	0

sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9221962	1492	0	0
T20	21194	76	0	0
T25	9037	3	0	0
T26	0	51	0	0
T27	9864	0	0	0
T28	5282	14	0	0
T29	24640	132	0	0
T49	0	43	0	0
T60	6562	4	0	0
T62	6392	0	0	0
T63	9192	0	0	0
T64	13360	0	0	0
T65	0	8	0	0
T72	5369	10	0	0
T74	0	77	0	0