Unified Coverage Report :: Group :: keymgr_dpe_env_pkg::keymgr_dpe_env_cov::lc_disable_cg

Group : keymgr_dpe_env_pkg::keymgr_dpe_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
7.69	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_dpe_env_0.1/keymgr_dpe_env_cov.sv

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Summary for Group keymgr_dpe_env_pkg::keymgr_dpe_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	9	2	18.18
Crosses	28	27	1	3.57

Variables for Group keymgr_dpe_env_pkg::keymgr_dpe_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	5	0	0.00	100	1	1	0
state_cp	4	3	1	25.00	100	1	1	0
wip_cp	2	1	1	50.00	100	1	1	2

Crosses for Group keymgr_dpe_env_pkg::keymgr_dpe_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	8	7	1	12.50	100	1	1	0
state_x_op_cross	20	20	0	0.00	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	5	0	0.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDpeAdvance]	0	1	1
auto[OpDpeErase]	0	1	1
auto[OpDpeGenSwOut]	0	1	1
auto[OpDpeGenHwOut]	0	1	1
auto[OpDpeDisable]	0	1	1

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Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	3	1	25.00

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StWorkDpeAvailable]	0	1	1
auto[StWorkDpeDisabled]	0	1	1
auto[StWorkDpeInvalid]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[StWorkDpeReset]

1502

1

T7

180

T8

180

T9

90

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for wip_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1812

1

T1

1

T2

1

T3

1

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	7	1	12.50	7

Automatically Generated Cross Bins for state_x_wip_cross

Element holes

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StWorkDpeAvailable] , auto[StWorkDpeDisabled] , auto[StWorkDpeInvalid]]	*	--	--	6

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StWorkDpeReset]]	[auto[1]]	0	1	1

Covered bins

state_cp

wip_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[StWorkDpeReset]

auto[0]

1502

1

T7

180

T8

180

T9

90

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	20	20	0	0.00	20

Automatically Generated Cross Bins for state_x_op_cross

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	20