Unified Coverage Report :: Group :: keymgr_dpe_env_pkg::keymgr_dpe_env_cov::state_and_op_cg

Group : keymgr_dpe_env_pkg::keymgr_dpe_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
17.51	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_dpe_env_0.1/keymgr_dpe_env_cov.sv

---

Summary for Group keymgr_dpe_env_pkg::keymgr_dpe_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	17	4	13	76.47
Crosses	240	208	32	13.33

Variables for Group keymgr_dpe_env_pkg::keymgr_dpe_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	1	1	50.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	1	4	80.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	4	2	2	50.00	100	1	1	0

Crosses for Group keymgr_dpe_env_pkg::keymgr_dpe_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	160	144	16	10.00	100	1	1	0
op_x_status_cross	80	64	16	20.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cdi_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[Attestation]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

6843

1

T4

133

T5

150

T6

122

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	1646	1			T4	33		T5	34		T6	30
auto[Aes]	1743	1			T4	35		T5	38		T6	35
auto[Kmac]	1695	1			T4	42		T5	35		T6	32
auto[Otbn]	1759	1			T4	23		T5	43		T6	25

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDpeErase]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpDpeAdvance]	1545	1			T4	31		T5	31		T6	30
auto[OpDpeGenSwOut]	3439	1			T4	66		T5	85		T6	64
auto[OpDpeGenHwOut]	3404	1			T4	67		T5	65		T6	58
auto[OpDpeDisable]	100	1			T4	2		T5	2		T6	2

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

3604

1

T4

62

T5

100

T6

79

auto[OpDoneFail]

4884

1

T4

104

T5

83

T6

75

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	2	2	50.00

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StWorkDpeDisabled]	0	1	1
auto[StWorkDpeInvalid]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[StWorkDpeReset]

285

1

T4

9

T5

7

T6

2

auto[StWorkDpeAvailable]

8203

1

T4

157

T5

176

T6

152

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	160	144	16	10.00	144

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpDpeAdvance] , auto[OpDpeErase]]	*	*	*	--	--	64
[auto[OpDpeGenSwOut] , auto[OpDpeGenHwOut]]	[auto[Sealing]]	*	[auto[StWorkDpeDisabled] , auto[StWorkDpeInvalid]]	--	--	16
[auto[OpDpeGenSwOut] , auto[OpDpeGenHwOut]]	[auto[Attestation]]	*	*	--	--	32
[auto[OpDpeDisable]]	*	*	*	--	--	32

Covered bins

op_cp

cdi_cp

dest_cp

state_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDpeGenSwOut]

auto[Sealing]

auto[None]

auto[StWorkDpeReset]

26

1

T5

1

T12

2

T14

1

auto[OpDpeGenSwOut]

auto[Sealing]

auto[None]

auto[StWorkDpeAvailable]

785

1

T4

17

T5

20

T6

15

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Aes]

auto[StWorkDpeReset]

18

1

T12

1

T13

1

T16

1

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Aes]

auto[StWorkDpeAvailable]

861

1

T4

17

T5

23

T6

11

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Kmac]

auto[StWorkDpeReset]

33

1

T4

3

T12

2

T13

1

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Kmac]

auto[StWorkDpeAvailable]

837

1

T4

18

T5

21

T6

24

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Otbn]

auto[StWorkDpeReset]

23

1

T4

1

T5

1

T13

1

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Otbn]

auto[StWorkDpeAvailable]

856

1

T4

10

T5

19

T6

14

auto[OpDpeGenHwOut]

auto[Sealing]

auto[None]

auto[StWorkDpeReset]

19

1

T4

1

T5

1

T12

1

auto[OpDpeGenHwOut]

auto[Sealing]

auto[None]

auto[StWorkDpeAvailable]

816

1

T4

15

T5

12

T6

15

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Aes]

auto[StWorkDpeReset]

18

1

T5

1

T12

1

T13

1

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Aes]

auto[StWorkDpeAvailable]

846

1

T4

18

T5

14

T6

24

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Kmac]

auto[StWorkDpeReset]

30

1

T4

2

T5

1

T12

2

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Kmac]

auto[StWorkDpeAvailable]

795

1

T4

19

T5

13

T6

8

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Otbn]

auto[StWorkDpeReset]

18

1

T13

1

T16

4

T102

1

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Otbn]

auto[StWorkDpeAvailable]

862

1

T4

12

T5

23

T6

11

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	64	16	20.00	64

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpDpeAdvance] , auto[OpDpeErase]]	*	*	*	--	--	32
[auto[OpDpeGenSwOut] , auto[OpDpeGenHwOut]]	[auto[Attestation]]	*	*	--	--	16
[auto[OpDpeDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpDpeAdvance] , auto[OpDpeErase] , auto[OpDpeGenSwOut] , auto[OpDpeGenHwOut] , auto[OpDpeDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp

cdi_cp

dest_cp

op_status_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDpeGenSwOut]

auto[Sealing]

auto[None]

auto[OpDoneSuccess]

354

1

T4

7

T5

12

T6

9

auto[OpDpeGenSwOut]

auto[Sealing]

auto[None]

auto[OpDoneFail]

457

1

T4

10

T5

9

T6

6

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Aes]

auto[OpDoneSuccess]

394

1

T4

9

T5

15

T6

2

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Aes]

auto[OpDoneFail]

485

1

T4

8

T5

8

T6

9

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Kmac]

auto[OpDoneSuccess]

403

1

T4

9

T5

12

T6

13

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Kmac]

auto[OpDoneFail]

467

1

T4

12

T5

9

T6

11

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Otbn]

auto[OpDoneSuccess]

410

1

T4

4

T5

9

T6

7

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Otbn]

auto[OpDoneFail]

469

1

T4

7

T5

11

T6

7

auto[OpDpeGenHwOut]

auto[Sealing]

auto[None]

auto[OpDoneSuccess]

383

1

T4

5

T5

7

T6

9

auto[OpDpeGenHwOut]

auto[Sealing]

auto[None]

auto[OpDoneFail]

452

1

T4

11

T5

6

T6

6

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Aes]

auto[OpDoneSuccess]

424

1

T4

8

T5

12

T6

19

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Aes]

auto[OpDoneFail]

440

1

T4

10

T5

3

T6

5

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Kmac]

auto[OpDoneSuccess]

360

1

T4

6

T5

8

T6

7

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Kmac]

auto[OpDoneFail]

465

1

T4

15

T5

6

T6

1

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Otbn]

auto[OpDoneSuccess]

400

1

T4

4

T5

16

T6

3

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Otbn]

auto[OpDoneFail]

480

1

T4

8

T5

7

T6

8