Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
76.26 97.70 90.54 57.52 76.92 94.94 98.34 17.85


Total test records in report: 310
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html
T257 /workspace/coverage/cover_reg_top/1.keymgr_dpe_intr_test.293884856 Feb 22 12:33:14 PM PST 24 Feb 22 12:33:15 PM PST 24 36535282 ps
T258 /workspace/coverage/cover_reg_top/3.keymgr_dpe_intr_test.67758437 Feb 22 12:33:09 PM PST 24 Feb 22 12:33:11 PM PST 24 35419138 ps
T259 /workspace/coverage/cover_reg_top/11.keymgr_dpe_intr_test.2470985835 Feb 22 12:33:12 PM PST 24 Feb 22 12:33:14 PM PST 24 13347151 ps
T260 /workspace/coverage/cover_reg_top/0.keymgr_dpe_intr_test.3653234899 Feb 22 12:33:12 PM PST 24 Feb 22 12:33:13 PM PST 24 67602754 ps
T261 /workspace/coverage/cover_reg_top/17.keymgr_dpe_tl_errors.2956326148 Feb 22 12:33:17 PM PST 24 Feb 22 12:33:19 PM PST 24 18945003 ps
T55 /workspace/coverage/cover_reg_top/18.keymgr_dpe_tl_intg_err.1228154228 Feb 22 12:33:22 PM PST 24 Feb 22 12:33:24 PM PST 24 172409795 ps
T262 /workspace/coverage/cover_reg_top/15.keymgr_dpe_csr_rw.2482844647 Feb 22 12:33:37 PM PST 24 Feb 22 12:33:38 PM PST 24 28333181 ps
T263 /workspace/coverage/cover_reg_top/49.keymgr_dpe_intr_test.1884840944 Feb 22 12:33:40 PM PST 24 Feb 22 12:33:41 PM PST 24 14126473 ps
T264 /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors.22922957 Feb 22 12:33:26 PM PST 24 Feb 22 12:33:28 PM PST 24 866406095 ps
T265 /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_aliasing.1111969665 Feb 22 12:33:11 PM PST 24 Feb 22 12:33:17 PM PST 24 599989748 ps
T67 /workspace/coverage/cover_reg_top/11.keymgr_dpe_tl_intg_err.525877967 Feb 22 12:33:32 PM PST 24 Feb 22 12:33:35 PM PST 24 91825561 ps
T266 /workspace/coverage/cover_reg_top/3.keymgr_dpe_same_csr_outstanding.1397519341 Feb 22 12:33:07 PM PST 24 Feb 22 12:33:09 PM PST 24 111494265 ps
T267 /workspace/coverage/cover_reg_top/29.keymgr_dpe_intr_test.4000493360 Feb 22 12:33:34 PM PST 24 Feb 22 12:33:35 PM PST 24 51864474 ps
T64 /workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_intg_err.3300424056 Feb 22 12:33:14 PM PST 24 Feb 22 12:33:16 PM PST 24 50705473 ps
T268 /workspace/coverage/cover_reg_top/5.keymgr_dpe_tl_errors.1519292212 Feb 22 12:33:03 PM PST 24 Feb 22 12:33:05 PM PST 24 221414807 ps
T269 /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_aliasing.2932469955 Feb 22 12:33:13 PM PST 24 Feb 22 12:33:18 PM PST 24 236075932 ps
T270 /workspace/coverage/cover_reg_top/19.keymgr_dpe_csr_mem_rw_with_rand_reset.1083235583 Feb 22 12:33:23 PM PST 24 Feb 22 12:33:25 PM PST 24 26522686 ps
T271 /workspace/coverage/cover_reg_top/11.keymgr_dpe_tl_errors.1660263399 Feb 22 12:33:26 PM PST 24 Feb 22 12:33:35 PM PST 24 290760148 ps
T272 /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors_with_csr_rw.3405833495 Feb 22 12:33:31 PM PST 24 Feb 22 12:33:35 PM PST 24 279950772 ps
T273 /workspace/coverage/cover_reg_top/8.keymgr_dpe_same_csr_outstanding.1210811871 Feb 22 12:33:16 PM PST 24 Feb 22 12:33:17 PM PST 24 156336307 ps
T274 /workspace/coverage/cover_reg_top/6.keymgr_dpe_intr_test.896769160 Feb 22 12:33:26 PM PST 24 Feb 22 12:33:27 PM PST 24 8304310 ps
T69 /workspace/coverage/cover_reg_top/14.keymgr_dpe_tl_intg_err.1284902813 Feb 22 12:33:18 PM PST 24 Feb 22 12:33:27 PM PST 24 791286761 ps
T275 /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_mem_rw_with_rand_reset.3717423515 Feb 22 12:33:16 PM PST 24 Feb 22 12:33:17 PM PST 24 75463375 ps
T276 /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_mem_rw_with_rand_reset.1286937227 Feb 22 12:33:08 PM PST 24 Feb 22 12:33:10 PM PST 24 31008727 ps
T277 /workspace/coverage/cover_reg_top/41.keymgr_dpe_intr_test.3026181406 Feb 22 12:33:44 PM PST 24 Feb 22 12:33:45 PM PST 24 13743164 ps
T278 /workspace/coverage/cover_reg_top/16.keymgr_dpe_shadow_reg_errors_with_csr_rw.3328422912 Feb 22 12:33:20 PM PST 24 Feb 22 12:33:23 PM PST 24 238966393 ps
T279 /workspace/coverage/cover_reg_top/4.keymgr_dpe_shadow_reg_errors.121320980 Feb 22 12:33:11 PM PST 24 Feb 22 12:33:14 PM PST 24 75544939 ps
T280 /workspace/coverage/cover_reg_top/9.keymgr_dpe_csr_mem_rw_with_rand_reset.1035889175 Feb 22 12:33:20 PM PST 24 Feb 22 12:33:22 PM PST 24 228637489 ps
T281 /workspace/coverage/cover_reg_top/16.keymgr_dpe_intr_test.138406721 Feb 22 12:33:39 PM PST 24 Feb 22 12:33:40 PM PST 24 10801959 ps
T282 /workspace/coverage/cover_reg_top/22.keymgr_dpe_intr_test.621802009 Feb 22 12:33:13 PM PST 24 Feb 22 12:33:14 PM PST 24 36021262 ps
T283 /workspace/coverage/cover_reg_top/14.keymgr_dpe_intr_test.609216214 Feb 22 12:33:14 PM PST 24 Feb 22 12:33:15 PM PST 24 23323623 ps
T284 /workspace/coverage/cover_reg_top/10.keymgr_dpe_intr_test.663797854 Feb 22 12:33:49 PM PST 24 Feb 22 12:33:50 PM PST 24 47367018 ps
T285 /workspace/coverage/cover_reg_top/18.keymgr_dpe_same_csr_outstanding.130474358 Feb 22 12:33:21 PM PST 24 Feb 22 12:33:23 PM PST 24 68167467 ps
T286 /workspace/coverage/cover_reg_top/18.keymgr_dpe_csr_mem_rw_with_rand_reset.2713177611 Feb 22 12:33:21 PM PST 24 Feb 22 12:33:23 PM PST 24 19516379 ps
T287 /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_bit_bash.652014164 Feb 22 12:33:07 PM PST 24 Feb 22 12:33:19 PM PST 24 429412955 ps
T288 /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_bit_bash.2960340342 Feb 22 12:33:09 PM PST 24 Feb 22 12:33:13 PM PST 24 734812248 ps
T289 /workspace/coverage/cover_reg_top/13.keymgr_dpe_intr_test.2734868506 Feb 22 12:33:37 PM PST 24 Feb 22 12:33:39 PM PST 24 10905627 ps
T290 /workspace/coverage/cover_reg_top/8.keymgr_dpe_tl_errors.2419646574 Feb 22 12:33:11 PM PST 24 Feb 22 12:33:13 PM PST 24 253383179 ps
T291 /workspace/coverage/cover_reg_top/11.keymgr_dpe_csr_rw.927122561 Feb 22 12:33:14 PM PST 24 Feb 22 12:33:15 PM PST 24 39335595 ps
T292 /workspace/coverage/cover_reg_top/15.keymgr_dpe_intr_test.2046347212 Feb 22 12:33:27 PM PST 24 Feb 22 12:33:28 PM PST 24 22836070 ps
T293 /workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_intg_err.1843433983 Feb 22 12:33:19 PM PST 24 Feb 22 12:33:23 PM PST 24 92615794 ps
T294 /workspace/coverage/cover_reg_top/34.keymgr_dpe_intr_test.2195052813 Feb 22 12:33:42 PM PST 24 Feb 22 12:33:43 PM PST 24 28548218 ps
T65 /workspace/coverage/cover_reg_top/13.keymgr_dpe_tl_intg_err.2962737074 Feb 22 12:33:18 PM PST 24 Feb 22 12:33:20 PM PST 24 166360896 ps
T53 /workspace/coverage/cover_reg_top/19.keymgr_dpe_tl_intg_err.2609933191 Feb 22 12:33:19 PM PST 24 Feb 22 12:33:25 PM PST 24 466598830 ps
T295 /workspace/coverage/cover_reg_top/7.keymgr_dpe_intr_test.1478246103 Feb 22 12:33:16 PM PST 24 Feb 22 12:33:22 PM PST 24 39658932 ps
T296 /workspace/coverage/cover_reg_top/10.keymgr_dpe_csr_rw.2383500521 Feb 22 12:33:42 PM PST 24 Feb 22 12:33:43 PM PST 24 37233491 ps
T297 /workspace/coverage/cover_reg_top/37.keymgr_dpe_intr_test.2045504264 Feb 22 12:33:36 PM PST 24 Feb 22 12:33:37 PM PST 24 19701448 ps
T298 /workspace/coverage/cover_reg_top/12.keymgr_dpe_tl_errors.683315103 Feb 22 12:33:21 PM PST 24 Feb 22 12:33:24 PM PST 24 69991496 ps
T299 /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_bit_bash.1621214015 Feb 22 12:33:06 PM PST 24 Feb 22 12:33:17 PM PST 24 1393994034 ps
T300 /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_hw_reset.3910252286 Feb 22 12:33:07 PM PST 24 Feb 22 12:33:08 PM PST 24 85496140 ps
T301 /workspace/coverage/cover_reg_top/9.keymgr_dpe_shadow_reg_errors.1991547326 Feb 22 12:33:26 PM PST 24 Feb 22 12:33:29 PM PST 24 309314677 ps
T302 /workspace/coverage/cover_reg_top/43.keymgr_dpe_intr_test.684664166 Feb 22 12:33:50 PM PST 24 Feb 22 12:33:52 PM PST 24 16453036 ps
T303 /workspace/coverage/cover_reg_top/7.keymgr_dpe_csr_mem_rw_with_rand_reset.2548246980 Feb 22 12:33:05 PM PST 24 Feb 22 12:33:06 PM PST 24 126719763 ps
T304 /workspace/coverage/cover_reg_top/1.keymgr_dpe_tl_errors.2156038783 Feb 22 12:33:16 PM PST 24 Feb 22 12:33:18 PM PST 24 87009725 ps
T305 /workspace/coverage/cover_reg_top/6.keymgr_dpe_same_csr_outstanding.1300969505 Feb 22 12:33:10 PM PST 24 Feb 22 12:33:12 PM PST 24 175714935 ps
T306 /workspace/coverage/cover_reg_top/19.keymgr_dpe_shadow_reg_errors_with_csr_rw.570960717 Feb 22 12:33:38 PM PST 24 Feb 22 12:33:43 PM PST 24 283446370 ps
T307 /workspace/coverage/cover_reg_top/17.keymgr_dpe_csr_rw.2234694740 Feb 22 12:33:13 PM PST 24 Feb 22 12:33:15 PM PST 24 25927442 ps
T308 /workspace/coverage/cover_reg_top/2.keymgr_dpe_shadow_reg_errors_with_csr_rw.3349620006 Feb 22 12:33:07 PM PST 24 Feb 22 12:33:12 PM PST 24 132581435 ps
T309 /workspace/coverage/cover_reg_top/32.keymgr_dpe_intr_test.2599450757 Feb 22 12:33:48 PM PST 24 Feb 22 12:33:49 PM PST 24 12315063 ps
T310 /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_rw.2600803570 Feb 22 12:33:11 PM PST 24 Feb 22 12:33:12 PM PST 24 51350074 ps

Test location /workspace/coverage/default/20.keymgr_dpe_alert_test.714489788
Short name T2
Test name
Test status
Simulation time 71382453 ps
CPU time 0.87 seconds
Started Feb 22 12:25:52 PM PST 24
Finished Feb 22 12:25:53 PM PST 24
Peak memory 205096 kb
Host smart-c536b35d-4783-4cdc-bd07-4135d7f2bd17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714489788 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_alert_test.714489788
Directory /workspace/20.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_dpe_smoke.3867145744
Short name T13
Test name
Test status
Simulation time 13002864490 ps
CPU time 270.39 seconds
Started Feb 22 12:25:44 PM PST 24
Finished Feb 22 12:30:14 PM PST 24
Peak memory 208324 kb
Host smart-c107e4c6-63c2-4697-b148-df8dd48dc13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867145744 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_smoke.3867145744
Directory /workspace/3.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_tl_intg_err.3184308340
Short name T42
Test name
Test status
Simulation time 141058573 ps
CPU time 4.16 seconds
Started Feb 22 12:33:07 PM PST 24
Finished Feb 22 12:33:11 PM PST 24
Peak memory 213816 kb
Host smart-1711ebe4-9d71-4f0b-b0d9-f1e33ea6827d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184308340 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe
_tl_intg_err.3184308340
Directory /workspace/3.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/default/4.keymgr_dpe_sec_cm.635467707
Short name T7
Test name
Test status
Simulation time 3320162816 ps
CPU time 23.02 seconds
Started Feb 22 12:25:47 PM PST 24
Finished Feb 22 12:26:11 PM PST 24
Peak memory 231576 kb
Host smart-61740d5d-b9b9-481c-aca5-c643ab635eb9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635467707 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_sec_cm.635467707
Directory /workspace/4.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_tl_errors.4037343934
Short name T41
Test name
Test status
Simulation time 1154602617 ps
CPU time 5.04 seconds
Started Feb 22 12:33:09 PM PST 24
Finished Feb 22 12:33:15 PM PST 24
Peak memory 212640 kb
Host smart-1cf2f1e1-50b0-4495-b4f0-0f9f194ca3de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037343934 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_tl_errors.4
037343934
Directory /workspace/3.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_shadow_reg_errors_with_csr_rw.490530587
Short name T72
Test name
Test status
Simulation time 241243539 ps
CPU time 4.11 seconds
Started Feb 22 12:33:16 PM PST 24
Finished Feb 22 12:33:20 PM PST 24
Peak memory 213004 kb
Host smart-e643d322-5fc1-4bed-a71d-02b5cc20f525
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490530587 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 6.keymgr_dpe_shadow_reg_errors_with_csr_rw.490530587
Directory /workspace/6.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/11.keymgr_dpe_smoke.383081463
Short name T6
Test name
Test status
Simulation time 502753537 ps
CPU time 9.03 seconds
Started Feb 22 12:26:05 PM PST 24
Finished Feb 22 12:26:14 PM PST 24
Peak memory 206000 kb
Host smart-43494e2a-6f18-42f4-b075-e3b7416e660a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383081463 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_smoke.383081463
Directory /workspace/11.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_shadow_reg_errors.2352961238
Short name T74
Test name
Test status
Simulation time 205140308 ps
CPU time 1.77 seconds
Started Feb 22 12:33:19 PM PST 24
Finished Feb 22 12:33:21 PM PST 24
Peak memory 212808 kb
Host smart-57cb8303-4b6e-4d80-b3d6-a8b87d3ff97b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352961238 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.key
mgr_dpe_shadow_reg_errors.2352961238
Directory /workspace/16.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_intr_test.1711123428
Short name T104
Test name
Test status
Simulation time 26059404 ps
CPU time 0.88 seconds
Started Feb 22 12:33:17 PM PST 24
Finished Feb 22 12:33:19 PM PST 24
Peak memory 204276 kb
Host smart-ab19df08-c11f-4649-baa4-6f784e535f55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711123428 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_intr_test.
1711123428
Directory /workspace/17.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/default/0.keymgr_dpe_smoke.57815944
Short name T12
Test name
Test status
Simulation time 3160613205 ps
CPU time 28.63 seconds
Started Feb 22 12:25:55 PM PST 24
Finished Feb 22 12:26:23 PM PST 24
Peak memory 208028 kb
Host smart-7bce8360-f2cb-40f4-98c9-79175203e5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57815944 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_smoke.57815944
Directory /workspace/0.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_tl_intg_err.2788258410
Short name T43
Test name
Test status
Simulation time 995296366 ps
CPU time 5.57 seconds
Started Feb 22 12:33:11 PM PST 24
Finished Feb 22 12:33:17 PM PST 24
Peak memory 213816 kb
Host smart-93922fff-ffe7-4554-8c7d-d7176fee05a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788258410 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe
_tl_intg_err.2788258410
Directory /workspace/5.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_csr_mem_rw_with_rand_reset.2402724703
Short name T49
Test name
Test status
Simulation time 47580600 ps
CPU time 1.58 seconds
Started Feb 22 12:33:21 PM PST 24
Finished Feb 22 12:33:23 PM PST 24
Peak memory 212656 kb
Host smart-5301c817-31f8-43eb-a3df-18cf7184c72a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402724703 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_csr_mem_rw_with_rand_reset.2402724703
Directory /workspace/17.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_tl_intg_err.3197079702
Short name T57
Test name
Test status
Simulation time 315627133 ps
CPU time 3.75 seconds
Started Feb 22 12:33:13 PM PST 24
Finished Feb 22 12:33:18 PM PST 24
Peak memory 213948 kb
Host smart-02b4054d-aea6-4de3-ac9e-03cd5d30f138
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197079702 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe
_tl_intg_err.3197079702
Directory /workspace/2.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/default/16.keymgr_dpe_smoke.959212005
Short name T4
Test name
Test status
Simulation time 12658792853 ps
CPU time 188.68 seconds
Started Feb 22 12:25:58 PM PST 24
Finished Feb 22 12:29:07 PM PST 24
Peak memory 237372 kb
Host smart-bbc35aee-fd6b-47a4-982f-352dba6c371d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959212005 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_smoke.959212005
Directory /workspace/16.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_shadow_reg_errors.973399477
Short name T75
Test name
Test status
Simulation time 108391896 ps
CPU time 1.85 seconds
Started Feb 22 12:33:01 PM PST 24
Finished Feb 22 12:33:03 PM PST 24
Peak memory 212940 kb
Host smart-7d155c2a-1b0e-446b-96ce-be18ec9561e4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973399477 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymg
r_dpe_shadow_reg_errors.973399477
Directory /workspace/0.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_tl_intg_err.4151102173
Short name T70
Test name
Test status
Simulation time 403714946 ps
CPU time 2.94 seconds
Started Feb 22 12:33:16 PM PST 24
Finished Feb 22 12:33:21 PM PST 24
Peak memory 213864 kb
Host smart-c0cb506c-bd6a-4503-80e7-4c2db5f267af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151102173 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dp
e_tl_intg_err.4151102173
Directory /workspace/17.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_tl_intg_err.2609933191
Short name T53
Test name
Test status
Simulation time 466598830 ps
CPU time 6.12 seconds
Started Feb 22 12:33:19 PM PST 24
Finished Feb 22 12:33:25 PM PST 24
Peak memory 214292 kb
Host smart-1d6175ae-34b7-400c-950f-21de12b2cfb3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609933191 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dp
e_tl_intg_err.2609933191
Directory /workspace/19.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_intr_test.505991740
Short name T176
Test name
Test status
Simulation time 33914550 ps
CPU time 0.7 seconds
Started Feb 22 12:33:26 PM PST 24
Finished Feb 22 12:33:27 PM PST 24
Peak memory 204228 kb
Host smart-deddf574-8ed0-4c45-9fd0-09f9fd18ae75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505991740 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_intr_test.505991740
Directory /workspace/18.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_tl_intg_err.1613775324
Short name T68
Test name
Test status
Simulation time 161466375 ps
CPU time 2.25 seconds
Started Feb 22 12:33:17 PM PST 24
Finished Feb 22 12:33:19 PM PST 24
Peak memory 212528 kb
Host smart-b068fc53-11f0-4b27-9e50-693865aeb3b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613775324 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dp
e_tl_intg_err.1613775324
Directory /workspace/10.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_tl_intg_err.2962737074
Short name T65
Test name
Test status
Simulation time 166360896 ps
CPU time 1.97 seconds
Started Feb 22 12:33:18 PM PST 24
Finished Feb 22 12:33:20 PM PST 24
Peak memory 212548 kb
Host smart-a9f0e17f-01d9-4cd2-bfec-933ff0639feb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962737074 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dp
e_tl_intg_err.2962737074
Directory /workspace/13.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_tl_intg_err.1284902813
Short name T69
Test name
Test status
Simulation time 791286761 ps
CPU time 8.7 seconds
Started Feb 22 12:33:18 PM PST 24
Finished Feb 22 12:33:27 PM PST 24
Peak memory 214588 kb
Host smart-f101e607-6f6c-459a-9ad7-408e312dce19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284902813 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dp
e_tl_intg_err.1284902813
Directory /workspace/14.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_tl_intg_err.1228154228
Short name T55
Test name
Test status
Simulation time 172409795 ps
CPU time 2.39 seconds
Started Feb 22 12:33:22 PM PST 24
Finished Feb 22 12:33:24 PM PST 24
Peak memory 213964 kb
Host smart-7d20c1d3-fa90-41b4-84af-28a0451f5688
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228154228 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dp
e_tl_intg_err.1228154228
Directory /workspace/18.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_tl_intg_err.2642614593
Short name T44
Test name
Test status
Simulation time 215413816 ps
CPU time 5.51 seconds
Started Feb 22 12:33:06 PM PST 24
Finished Feb 22 12:33:12 PM PST 24
Peak memory 212564 kb
Host smart-15b54250-a5f8-41b5-856f-4f8074e50a29
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642614593 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe
_tl_intg_err.2642614593
Directory /workspace/4.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/default/1.keymgr_dpe_smoke.182288394
Short name T114
Test name
Test status
Simulation time 167690188 ps
CPU time 10.14 seconds
Started Feb 22 12:25:55 PM PST 24
Finished Feb 22 12:26:05 PM PST 24
Peak memory 206352 kb
Host smart-0a27fa6e-a401-4005-989b-928799d16654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182288394 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_smoke.182288394
Directory /workspace/1.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/13.keymgr_dpe_smoke.1756925471
Short name T86
Test name
Test status
Simulation time 833307091 ps
CPU time 15.43 seconds
Started Feb 22 12:25:47 PM PST 24
Finished Feb 22 12:26:03 PM PST 24
Peak memory 205868 kb
Host smart-e1e00b0d-8ee3-49be-ba2d-7adf6669388f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756925471 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_smoke.1756925471
Directory /workspace/13.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/14.keymgr_dpe_smoke.4235986099
Short name T118
Test name
Test status
Simulation time 4087871472 ps
CPU time 34.77 seconds
Started Feb 22 12:25:59 PM PST 24
Finished Feb 22 12:26:34 PM PST 24
Peak memory 207684 kb
Host smart-436ddfed-c7d1-4f83-b39b-07b9f912ce5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235986099 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_smoke.4235986099
Directory /workspace/14.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/19.keymgr_dpe_smoke.756311787
Short name T95
Test name
Test status
Simulation time 1088926866 ps
CPU time 12.96 seconds
Started Feb 22 12:25:45 PM PST 24
Finished Feb 22 12:25:58 PM PST 24
Peak memory 207724 kb
Host smart-ef23f26f-115f-47bd-94dc-284ad81f4dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756311787 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_smoke.756311787
Directory /workspace/19.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/2.keymgr_dpe_smoke.4031061944
Short name T93
Test name
Test status
Simulation time 7473191959 ps
CPU time 161.22 seconds
Started Feb 22 12:25:33 PM PST 24
Finished Feb 22 12:28:14 PM PST 24
Peak memory 208156 kb
Host smart-bc8ff568-af6a-4492-9e29-98b6cc7a5a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031061944 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_smoke.4031061944
Directory /workspace/2.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/20.keymgr_dpe_smoke.2656887402
Short name T160
Test name
Test status
Simulation time 1814243666 ps
CPU time 20 seconds
Started Feb 22 12:25:54 PM PST 24
Finished Feb 22 12:26:15 PM PST 24
Peak memory 207164 kb
Host smart-1e2ae4b8-ba34-4416-828a-99765af67ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656887402 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_smoke.2656887402
Directory /workspace/20.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/22.keymgr_dpe_smoke.965215215
Short name T113
Test name
Test status
Simulation time 3301259135 ps
CPU time 24.29 seconds
Started Feb 22 12:25:51 PM PST 24
Finished Feb 22 12:26:16 PM PST 24
Peak memory 208032 kb
Host smart-1a42d4ec-558d-4be4-a6c2-127ec53fca10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965215215 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_smoke.965215215
Directory /workspace/22.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/24.keymgr_dpe_smoke.3251803081
Short name T119
Test name
Test status
Simulation time 179506269 ps
CPU time 9.6 seconds
Started Feb 22 12:25:40 PM PST 24
Finished Feb 22 12:25:51 PM PST 24
Peak memory 206388 kb
Host smart-b69383be-2256-4bfa-b680-33a0024b9138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251803081 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_smoke.3251803081
Directory /workspace/24.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/25.keymgr_dpe_smoke.2318960526
Short name T39
Test name
Test status
Simulation time 3772499513 ps
CPU time 30.46 seconds
Started Feb 22 12:25:44 PM PST 24
Finished Feb 22 12:26:16 PM PST 24
Peak memory 208124 kb
Host smart-f37b6903-1e4a-4940-8868-ddedd6b530c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318960526 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_smoke.2318960526
Directory /workspace/25.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/26.keymgr_dpe_smoke.2978262469
Short name T34
Test name
Test status
Simulation time 230578544 ps
CPU time 11.24 seconds
Started Feb 22 12:25:56 PM PST 24
Finished Feb 22 12:26:13 PM PST 24
Peak memory 205884 kb
Host smart-e5af747c-7e9a-4d59-a3c5-84bcf2ec154d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978262469 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_smoke.2978262469
Directory /workspace/26.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/27.keymgr_dpe_smoke.1482594165
Short name T116
Test name
Test status
Simulation time 8172557565 ps
CPU time 108.63 seconds
Started Feb 22 12:25:56 PM PST 24
Finished Feb 22 12:27:45 PM PST 24
Peak memory 207668 kb
Host smart-45c17c40-5a22-4229-a8ec-deff34048c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482594165 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_smoke.1482594165
Directory /workspace/27.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/31.keymgr_dpe_smoke.3139515803
Short name T36
Test name
Test status
Simulation time 980132215 ps
CPU time 20.47 seconds
Started Feb 22 12:26:04 PM PST 24
Finished Feb 22 12:26:25 PM PST 24
Peak memory 207088 kb
Host smart-0c5917ef-ea44-4750-9f64-04b1903efbdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139515803 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_smoke.3139515803
Directory /workspace/31.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/38.keymgr_dpe_smoke.2898055051
Short name T120
Test name
Test status
Simulation time 164169006 ps
CPU time 10.05 seconds
Started Feb 22 12:26:10 PM PST 24
Finished Feb 22 12:26:20 PM PST 24
Peak memory 207940 kb
Host smart-d6c30f04-f4b2-4b99-a463-e58c6f857db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898055051 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_smoke.2898055051
Directory /workspace/38.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/45.keymgr_dpe_smoke.649670865
Short name T92
Test name
Test status
Simulation time 1891152814 ps
CPU time 16.56 seconds
Started Feb 22 12:25:52 PM PST 24
Finished Feb 22 12:26:08 PM PST 24
Peak memory 206076 kb
Host smart-de41ed50-3ea7-475b-a97e-18adfa685b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649670865 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_smoke.649670865
Directory /workspace/45.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/46.keymgr_dpe_smoke.2009056587
Short name T87
Test name
Test status
Simulation time 1149987326 ps
CPU time 28.57 seconds
Started Feb 22 12:25:43 PM PST 24
Finished Feb 22 12:26:12 PM PST 24
Peak memory 207668 kb
Host smart-10be1aa3-2e30-4ed0-b8b9-266763b695eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009056587 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_smoke.2009056587
Directory /workspace/46.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/1.keymgr_dpe_sec_cm.2319967176
Short name T31
Test name
Test status
Simulation time 885836099 ps
CPU time 20.13 seconds
Started Feb 22 12:25:52 PM PST 24
Finished Feb 22 12:26:12 PM PST 24
Peak memory 230976 kb
Host smart-98b73780-b1fc-4dcd-8682-a758ccd4c97e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319967176 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_sec_cm.2319967176
Directory /workspace/1.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_aliasing.547027524
Short name T191
Test name
Test status
Simulation time 222238700 ps
CPU time 5.55 seconds
Started Feb 22 12:33:08 PM PST 24
Finished Feb 22 12:33:14 PM PST 24
Peak memory 204436 kb
Host smart-5765a93e-e3c3-41fc-b773-1094ff2fb46c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547027524 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr
_aliasing.547027524
Directory /workspace/0.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_bit_bash.1621214015
Short name T299
Test name
Test status
Simulation time 1393994034 ps
CPU time 10 seconds
Started Feb 22 12:33:06 PM PST 24
Finished Feb 22 12:33:17 PM PST 24
Peak memory 204496 kb
Host smart-7408df66-9d80-43a2-8c01-0080e7aeed3b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621214015 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_cs
r_bit_bash.1621214015
Directory /workspace/0.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_hw_reset.2130995521
Short name T233
Test name
Test status
Simulation time 35106409 ps
CPU time 1.03 seconds
Started Feb 22 12:33:36 PM PST 24
Finished Feb 22 12:33:38 PM PST 24
Peak memory 204416 kb
Host smart-b4434fab-2f93-4e49-b56a-6548d7b791d1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130995521 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_cs
r_hw_reset.2130995521
Directory /workspace/0.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_mem_rw_with_rand_reset.3486723735
Short name T231
Test name
Test status
Simulation time 21274129 ps
CPU time 1.3 seconds
Started Feb 22 12:33:05 PM PST 24
Finished Feb 22 12:33:06 PM PST 24
Peak memory 204416 kb
Host smart-3afd5ad6-deb7-44fe-a0a3-ebc08a62479b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486723735 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr_mem_rw_with_rand_reset.3486723735
Directory /workspace/0.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_rw.2600803570
Short name T310
Test name
Test status
Simulation time 51350074 ps
CPU time 0.88 seconds
Started Feb 22 12:33:11 PM PST 24
Finished Feb 22 12:33:12 PM PST 24
Peak memory 204148 kb
Host smart-a4b986b6-97cc-4369-99ef-fd944e3433a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600803570 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr_rw.2
600803570
Directory /workspace/0.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_intr_test.3653234899
Short name T260
Test name
Test status
Simulation time 67602754 ps
CPU time 0.73 seconds
Started Feb 22 12:33:12 PM PST 24
Finished Feb 22 12:33:13 PM PST 24
Peak memory 204228 kb
Host smart-e30c89ad-6981-4c4f-bc80-d12af30d2b3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653234899 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_intr_test.3
653234899
Directory /workspace/0.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_same_csr_outstanding.3321294174
Short name T196
Test name
Test status
Simulation time 261201370 ps
CPU time 2.92 seconds
Started Feb 22 12:33:26 PM PST 24
Finished Feb 22 12:33:29 PM PST 24
Peak memory 204400 kb
Host smart-91787ed0-ae7f-4567-b637-718e46e14056
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321294174 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.k
eymgr_dpe_same_csr_outstanding.3321294174
Directory /workspace/0.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_shadow_reg_errors_with_csr_rw.2117978326
Short name T97
Test name
Test status
Simulation time 254450799 ps
CPU time 5.33 seconds
Started Feb 22 12:32:55 PM PST 24
Finished Feb 22 12:33:00 PM PST 24
Peak memory 212932 kb
Host smart-e3a48d35-4f51-4192-a608-3b678d722726
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117978326 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.keymgr_dpe_shadow_reg_errors_with_csr_rw.2117978326
Directory /workspace/0.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_tl_errors.2037377200
Short name T249
Test name
Test status
Simulation time 133834099 ps
CPU time 2.87 seconds
Started Feb 22 12:33:03 PM PST 24
Finished Feb 22 12:33:07 PM PST 24
Peak memory 212608 kb
Host smart-04dee9c4-7414-487d-a155-c526390bb78e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037377200 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_tl_errors.2
037377200
Directory /workspace/0.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_tl_intg_err.3052444670
Short name T256
Test name
Test status
Simulation time 56570588 ps
CPU time 2.8 seconds
Started Feb 22 12:32:58 PM PST 24
Finished Feb 22 12:33:01 PM PST 24
Peak memory 213084 kb
Host smart-7cf4cc14-e33f-463d-8966-55a802aa0867
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052444670 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe
_tl_intg_err.3052444670
Directory /workspace/0.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_aliasing.2932469955
Short name T269
Test name
Test status
Simulation time 236075932 ps
CPU time 3.61 seconds
Started Feb 22 12:33:13 PM PST 24
Finished Feb 22 12:33:18 PM PST 24
Peak memory 204388 kb
Host smart-df94bd8e-71bb-4afd-b965-be608edc4bec
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932469955 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_cs
r_aliasing.2932469955
Directory /workspace/1.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_bit_bash.2960340342
Short name T288
Test name
Test status
Simulation time 734812248 ps
CPU time 4.39 seconds
Started Feb 22 12:33:09 PM PST 24
Finished Feb 22 12:33:13 PM PST 24
Peak memory 204356 kb
Host smart-5e5727b6-e104-4118-920b-5ee403839b79
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960340342 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_cs
r_bit_bash.2960340342
Directory /workspace/1.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_hw_reset.2268988323
Short name T252
Test name
Test status
Simulation time 101356422 ps
CPU time 0.94 seconds
Started Feb 22 12:33:06 PM PST 24
Finished Feb 22 12:33:07 PM PST 24
Peak memory 204252 kb
Host smart-f7f17d1e-fe23-49ee-819f-be1585ee2c1f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268988323 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_cs
r_hw_reset.2268988323
Directory /workspace/1.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_mem_rw_with_rand_reset.3717423515
Short name T275
Test name
Test status
Simulation time 75463375 ps
CPU time 1.38 seconds
Started Feb 22 12:33:16 PM PST 24
Finished Feb 22 12:33:17 PM PST 24
Peak memory 212668 kb
Host smart-05fbfb60-99f3-44ba-83c6-0a4994724b1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717423515 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_csr_mem_rw_with_rand_reset.3717423515
Directory /workspace/1.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_rw.771791090
Short name T213
Test name
Test status
Simulation time 23388312 ps
CPU time 1.02 seconds
Started Feb 22 12:33:08 PM PST 24
Finished Feb 22 12:33:09 PM PST 24
Peak memory 204188 kb
Host smart-9f340800-146b-4b7e-b826-d9baf8960184
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771791090 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_csr_rw.771791090
Directory /workspace/1.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_intr_test.293884856
Short name T257
Test name
Test status
Simulation time 36535282 ps
CPU time 0.73 seconds
Started Feb 22 12:33:14 PM PST 24
Finished Feb 22 12:33:15 PM PST 24
Peak memory 204256 kb
Host smart-f635efdd-bb1d-4c3c-a0d2-8fd5d62b4ce5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293884856 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_intr_test.293884856
Directory /workspace/1.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_same_csr_outstanding.3328152523
Short name T235
Test name
Test status
Simulation time 54518108 ps
CPU time 1.97 seconds
Started Feb 22 12:33:07 PM PST 24
Finished Feb 22 12:33:10 PM PST 24
Peak memory 204380 kb
Host smart-72be5ea2-ca4b-44fe-a3b2-1b5292ea41d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328152523 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.k
eymgr_dpe_same_csr_outstanding.3328152523
Directory /workspace/1.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_shadow_reg_errors.2091828393
Short name T180
Test name
Test status
Simulation time 94525881 ps
CPU time 1.89 seconds
Started Feb 22 12:33:11 PM PST 24
Finished Feb 22 12:33:13 PM PST 24
Peak memory 212996 kb
Host smart-bff905b9-8026-437b-84f1-ddbd9a975675
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091828393 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keym
gr_dpe_shadow_reg_errors.2091828393
Directory /workspace/1.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_shadow_reg_errors_with_csr_rw.3471495245
Short name T110
Test name
Test status
Simulation time 485663574 ps
CPU time 8.6 seconds
Started Feb 22 12:33:06 PM PST 24
Finished Feb 22 12:33:15 PM PST 24
Peak memory 212888 kb
Host smart-4a720591-73fa-40a1-b41c-50a4cdb17de1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471495245 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.keymgr_dpe_shadow_reg_errors_with_csr_rw.3471495245
Directory /workspace/1.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_tl_errors.2156038783
Short name T304
Test name
Test status
Simulation time 87009725 ps
CPU time 2.24 seconds
Started Feb 22 12:33:16 PM PST 24
Finished Feb 22 12:33:18 PM PST 24
Peak memory 212664 kb
Host smart-8b8b53fd-d3c1-4519-ad61-9d54922cfa20
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156038783 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_tl_errors.2
156038783
Directory /workspace/1.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_tl_intg_err.3738207748
Short name T50
Test name
Test status
Simulation time 73108022 ps
CPU time 2.23 seconds
Started Feb 22 12:33:09 PM PST 24
Finished Feb 22 12:33:11 PM PST 24
Peak memory 212576 kb
Host smart-e8dcc735-a42d-4026-b0ac-9972f0819e20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738207748 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe
_tl_intg_err.3738207748
Directory /workspace/1.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_csr_mem_rw_with_rand_reset.1701006311
Short name T237
Test name
Test status
Simulation time 522726282 ps
CPU time 1.54 seconds
Started Feb 22 12:33:32 PM PST 24
Finished Feb 22 12:33:34 PM PST 24
Peak memory 212696 kb
Host smart-d22f9543-9241-41a4-850c-d3dc664e669f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701006311 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_csr_mem_rw_with_rand_reset.1701006311
Directory /workspace/10.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_csr_rw.2383500521
Short name T296
Test name
Test status
Simulation time 37233491 ps
CPU time 0.98 seconds
Started Feb 22 12:33:42 PM PST 24
Finished Feb 22 12:33:43 PM PST 24
Peak memory 204416 kb
Host smart-29e0b30c-0137-4b7d-a8fe-016e1fb52f6c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383500521 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_csr_rw.
2383500521
Directory /workspace/10.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_intr_test.663797854
Short name T284
Test name
Test status
Simulation time 47367018 ps
CPU time 0.85 seconds
Started Feb 22 12:33:49 PM PST 24
Finished Feb 22 12:33:50 PM PST 24
Peak memory 204208 kb
Host smart-0ace92c1-d695-4ce4-b814-d9214a815103
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663797854 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_intr_test.663797854
Directory /workspace/10.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_same_csr_outstanding.2969606116
Short name T172
Test name
Test status
Simulation time 19179327 ps
CPU time 1.24 seconds
Started Feb 22 12:33:07 PM PST 24
Finished Feb 22 12:33:09 PM PST 24
Peak memory 204472 kb
Host smart-b2eb6aca-c493-42f9-a8de-6df96a807fec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969606116 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
keymgr_dpe_same_csr_outstanding.2969606116
Directory /workspace/10.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_shadow_reg_errors.1527819521
Short name T230
Test name
Test status
Simulation time 27144275 ps
CPU time 1.35 seconds
Started Feb 22 12:33:19 PM PST 24
Finished Feb 22 12:33:20 PM PST 24
Peak memory 212940 kb
Host smart-848c15d6-71d5-49b7-a286-f3e56d5038df
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527819521 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.key
mgr_dpe_shadow_reg_errors.1527819521
Directory /workspace/10.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_shadow_reg_errors_with_csr_rw.911177327
Short name T175
Test name
Test status
Simulation time 650410081 ps
CPU time 4.88 seconds
Started Feb 22 12:33:21 PM PST 24
Finished Feb 22 12:33:26 PM PST 24
Peak memory 212956 kb
Host smart-e93349a6-f3d0-4ba5-bf82-c95393235d0b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911177327 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 10.keymgr_dpe_shadow_reg_errors_with_csr_rw.911177327
Directory /workspace/10.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_tl_errors.2330370496
Short name T245
Test name
Test status
Simulation time 318704217 ps
CPU time 2.89 seconds
Started Feb 22 12:33:12 PM PST 24
Finished Feb 22 12:33:16 PM PST 24
Peak memory 215016 kb
Host smart-228cbfe4-648d-43b4-8a71-2a4747c80252
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330370496 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_tl_errors.
2330370496
Directory /workspace/10.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_csr_mem_rw_with_rand_reset.924355311
Short name T219
Test name
Test status
Simulation time 34205065 ps
CPU time 1.44 seconds
Started Feb 22 12:33:19 PM PST 24
Finished Feb 22 12:33:20 PM PST 24
Peak memory 220276 kb
Host smart-fc6cf7f9-5c0c-40e0-baf3-3de64587b1e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924355311 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_csr_mem_rw_with_rand_reset.924355311
Directory /workspace/11.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_csr_rw.927122561
Short name T291
Test name
Test status
Simulation time 39335595 ps
CPU time 0.91 seconds
Started Feb 22 12:33:14 PM PST 24
Finished Feb 22 12:33:15 PM PST 24
Peak memory 204236 kb
Host smart-269a2c48-7028-456b-bd2a-f9ed5f19430f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927122561 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_csr_rw.927122561
Directory /workspace/11.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_intr_test.2470985835
Short name T259
Test name
Test status
Simulation time 13347151 ps
CPU time 0.72 seconds
Started Feb 22 12:33:12 PM PST 24
Finished Feb 22 12:33:14 PM PST 24
Peak memory 204184 kb
Host smart-59d84862-ce2c-497f-94af-3cf864b4da9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470985835 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_intr_test.
2470985835
Directory /workspace/11.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_same_csr_outstanding.4108187883
Short name T54
Test name
Test status
Simulation time 212253060 ps
CPU time 1.69 seconds
Started Feb 22 12:33:26 PM PST 24
Finished Feb 22 12:33:29 PM PST 24
Peak memory 204400 kb
Host smart-7739065a-23ca-41c5-ad88-fceb1aae8506
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108187883 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
keymgr_dpe_same_csr_outstanding.4108187883
Directory /workspace/11.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_shadow_reg_errors.1538009061
Short name T76
Test name
Test status
Simulation time 413268650 ps
CPU time 2.1 seconds
Started Feb 22 12:33:12 PM PST 24
Finished Feb 22 12:33:15 PM PST 24
Peak memory 212948 kb
Host smart-2010877a-0920-42dd-9445-ee0cadfab889
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538009061 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.key
mgr_dpe_shadow_reg_errors.1538009061
Directory /workspace/11.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_shadow_reg_errors_with_csr_rw.1869744437
Short name T227
Test name
Test status
Simulation time 106771200 ps
CPU time 4.09 seconds
Started Feb 22 12:33:13 PM PST 24
Finished Feb 22 12:33:18 PM PST 24
Peak memory 212960 kb
Host smart-c86b0f59-b3bc-40cf-8ae0-0a92dda7e3b1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869744437 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 11.keymgr_dpe_shadow_reg_errors_with_csr_rw.1869744437
Directory /workspace/11.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_tl_errors.1660263399
Short name T271
Test name
Test status
Simulation time 290760148 ps
CPU time 3.67 seconds
Started Feb 22 12:33:26 PM PST 24
Finished Feb 22 12:33:35 PM PST 24
Peak memory 214936 kb
Host smart-022ad5ae-f5b2-4bcd-ad15-b1d0eb7c7538
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660263399 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_tl_errors.
1660263399
Directory /workspace/11.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_tl_intg_err.525877967
Short name T67
Test name
Test status
Simulation time 91825561 ps
CPU time 2.19 seconds
Started Feb 22 12:33:32 PM PST 24
Finished Feb 22 12:33:35 PM PST 24
Peak memory 213528 kb
Host smart-874dd94f-9ee7-4f08-9024-68cb41978454
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525877967 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe
_tl_intg_err.525877967
Directory /workspace/11.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_csr_mem_rw_with_rand_reset.2515733442
Short name T190
Test name
Test status
Simulation time 113189465 ps
CPU time 1.61 seconds
Started Feb 22 12:33:20 PM PST 24
Finished Feb 22 12:33:22 PM PST 24
Peak memory 212604 kb
Host smart-eb981c53-77ac-49aa-8fe4-9335ef664ad9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515733442 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_csr_mem_rw_with_rand_reset.2515733442
Directory /workspace/12.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_csr_rw.2423946267
Short name T211
Test name
Test status
Simulation time 24972183 ps
CPU time 0.93 seconds
Started Feb 22 12:33:14 PM PST 24
Finished Feb 22 12:33:15 PM PST 24
Peak memory 204296 kb
Host smart-68cd34ec-01b4-4f66-9116-248c0f2de6a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423946267 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_csr_rw.
2423946267
Directory /workspace/12.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_intr_test.4056201664
Short name T250
Test name
Test status
Simulation time 29197842 ps
CPU time 0.7 seconds
Started Feb 22 12:33:19 PM PST 24
Finished Feb 22 12:33:20 PM PST 24
Peak memory 204208 kb
Host smart-735f6452-6e02-450f-9cb0-5073645bf6ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056201664 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_intr_test.
4056201664
Directory /workspace/12.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_same_csr_outstanding.2781326286
Short name T251
Test name
Test status
Simulation time 81367403 ps
CPU time 1.75 seconds
Started Feb 22 12:33:37 PM PST 24
Finished Feb 22 12:33:39 PM PST 24
Peak memory 204312 kb
Host smart-498f72a7-2f81-41b8-be21-3808047c1c8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781326286 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
keymgr_dpe_same_csr_outstanding.2781326286
Directory /workspace/12.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_shadow_reg_errors.1130585252
Short name T78
Test name
Test status
Simulation time 68477271 ps
CPU time 2.38 seconds
Started Feb 22 12:33:12 PM PST 24
Finished Feb 22 12:33:15 PM PST 24
Peak memory 212988 kb
Host smart-ebfc94b4-70a1-4774-ae2f-ca257260270b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130585252 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.key
mgr_dpe_shadow_reg_errors.1130585252
Directory /workspace/12.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_shadow_reg_errors_with_csr_rw.4238979071
Short name T241
Test name
Test status
Simulation time 855151788 ps
CPU time 8.63 seconds
Started Feb 22 12:33:33 PM PST 24
Finished Feb 22 12:33:42 PM PST 24
Peak memory 218164 kb
Host smart-ddb96cd5-8278-469f-b312-20ccc3cb49d3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238979071 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.keymgr_dpe_shadow_reg_errors_with_csr_rw.4238979071
Directory /workspace/12.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_tl_errors.683315103
Short name T298
Test name
Test status
Simulation time 69991496 ps
CPU time 2.15 seconds
Started Feb 22 12:33:21 PM PST 24
Finished Feb 22 12:33:24 PM PST 24
Peak memory 212748 kb
Host smart-cfe394b8-44aa-4885-bdb0-458bf0eef99c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683315103 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_tl_errors.683315103
Directory /workspace/12.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_tl_intg_err.563876131
Short name T66
Test name
Test status
Simulation time 702032284 ps
CPU time 6.88 seconds
Started Feb 22 12:33:12 PM PST 24
Finished Feb 22 12:33:20 PM PST 24
Peak memory 213536 kb
Host smart-53ad7152-2546-4858-ad5f-c83799bf9fa0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563876131 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe
_tl_intg_err.563876131
Directory /workspace/12.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_csr_mem_rw_with_rand_reset.4168956139
Short name T80
Test name
Test status
Simulation time 32364009 ps
CPU time 1.64 seconds
Started Feb 22 12:33:26 PM PST 24
Finished Feb 22 12:33:28 PM PST 24
Peak memory 212756 kb
Host smart-e0f79c93-aa62-4157-beff-39ffb61e4edc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168956139 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_csr_mem_rw_with_rand_reset.4168956139
Directory /workspace/13.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_csr_rw.4230617822
Short name T242
Test name
Test status
Simulation time 25520310 ps
CPU time 1.02 seconds
Started Feb 22 12:33:37 PM PST 24
Finished Feb 22 12:33:39 PM PST 24
Peak memory 204076 kb
Host smart-6564af63-3bcf-47e0-854d-04d142f4ad9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230617822 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_csr_rw.
4230617822
Directory /workspace/13.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_intr_test.2734868506
Short name T289
Test name
Test status
Simulation time 10905627 ps
CPU time 0.85 seconds
Started Feb 22 12:33:37 PM PST 24
Finished Feb 22 12:33:39 PM PST 24
Peak memory 204236 kb
Host smart-9a421033-4432-4aa6-8ad0-8b6345d30827
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734868506 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_intr_test.
2734868506
Directory /workspace/13.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_same_csr_outstanding.2770357032
Short name T189
Test name
Test status
Simulation time 67712562 ps
CPU time 1.49 seconds
Started Feb 22 12:33:23 PM PST 24
Finished Feb 22 12:33:25 PM PST 24
Peak memory 204448 kb
Host smart-54fba85b-b3f3-4dd3-bdef-77a4c3d01e07
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770357032 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
keymgr_dpe_same_csr_outstanding.2770357032
Directory /workspace/13.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors.22922957
Short name T264
Test name
Test status
Simulation time 866406095 ps
CPU time 1.74 seconds
Started Feb 22 12:33:26 PM PST 24
Finished Feb 22 12:33:28 PM PST 24
Peak memory 212912 kb
Host smart-ce1617dd-a5e6-4972-a11e-5ad248875bdc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22922957 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keym
gr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymg
r_dpe_shadow_reg_errors.22922957
Directory /workspace/13.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors_with_csr_rw.3405833495
Short name T272
Test name
Test status
Simulation time 279950772 ps
CPU time 3.07 seconds
Started Feb 22 12:33:31 PM PST 24
Finished Feb 22 12:33:35 PM PST 24
Peak memory 212964 kb
Host smart-a0d69d5c-1b82-41f1-9f6a-cb060a21577c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405833495 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.keymgr_dpe_shadow_reg_errors_with_csr_rw.3405833495
Directory /workspace/13.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_tl_errors.453245590
Short name T197
Test name
Test status
Simulation time 116562323 ps
CPU time 4.52 seconds
Started Feb 22 12:33:18 PM PST 24
Finished Feb 22 12:33:22 PM PST 24
Peak memory 215948 kb
Host smart-f20916d4-a8d3-43f6-961c-02d66debec0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453245590 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_tl_errors.453245590
Directory /workspace/13.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_csr_mem_rw_with_rand_reset.504142284
Short name T112
Test name
Test status
Simulation time 74514244 ps
CPU time 1.23 seconds
Started Feb 22 12:33:17 PM PST 24
Finished Feb 22 12:33:18 PM PST 24
Peak memory 204496 kb
Host smart-bdb9a3de-81cb-44a4-9d9a-6b63e894ee50
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504142284 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_csr_mem_rw_with_rand_reset.504142284
Directory /workspace/14.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_csr_rw.2576039083
Short name T82
Test name
Test status
Simulation time 20385079 ps
CPU time 0.85 seconds
Started Feb 22 12:33:31 PM PST 24
Finished Feb 22 12:33:32 PM PST 24
Peak memory 204280 kb
Host smart-a1aac654-5b7d-4c7b-963e-02ed89e1ce19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576039083 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_csr_rw.
2576039083
Directory /workspace/14.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_intr_test.609216214
Short name T283
Test name
Test status
Simulation time 23323623 ps
CPU time 0.71 seconds
Started Feb 22 12:33:14 PM PST 24
Finished Feb 22 12:33:15 PM PST 24
Peak memory 204228 kb
Host smart-da675832-fc7f-4f48-a13d-e9a65f026527
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609216214 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_intr_test.609216214
Directory /workspace/14.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_same_csr_outstanding.1216136609
Short name T83
Test name
Test status
Simulation time 484243143 ps
CPU time 1.94 seconds
Started Feb 22 12:33:18 PM PST 24
Finished Feb 22 12:33:20 PM PST 24
Peak memory 204308 kb
Host smart-341c10c8-271c-4ab6-9922-cdd5f90bd083
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216136609 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
keymgr_dpe_same_csr_outstanding.1216136609
Directory /workspace/14.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_shadow_reg_errors.4089256448
Short name T194
Test name
Test status
Simulation time 150790665 ps
CPU time 1.44 seconds
Started Feb 22 12:33:25 PM PST 24
Finished Feb 22 12:33:26 PM PST 24
Peak memory 213088 kb
Host smart-3767404f-1938-4f92-8115-d0c7531ec65e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089256448 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.key
mgr_dpe_shadow_reg_errors.4089256448
Directory /workspace/14.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_shadow_reg_errors_with_csr_rw.3064840043
Short name T206
Test name
Test status
Simulation time 105787418 ps
CPU time 4.21 seconds
Started Feb 22 12:33:18 PM PST 24
Finished Feb 22 12:33:22 PM PST 24
Peak memory 212960 kb
Host smart-1222e7b3-503a-4cec-b488-7b6ca04378f1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064840043 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.keymgr_dpe_shadow_reg_errors_with_csr_rw.3064840043
Directory /workspace/14.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_tl_errors.2492111104
Short name T60
Test name
Test status
Simulation time 379418166 ps
CPU time 2.51 seconds
Started Feb 22 12:33:17 PM PST 24
Finished Feb 22 12:33:21 PM PST 24
Peak memory 212636 kb
Host smart-2ae7b57f-6720-4d89-9c4c-4ebb3437c5e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492111104 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_tl_errors.
2492111104
Directory /workspace/14.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_csr_mem_rw_with_rand_reset.1853135104
Short name T208
Test name
Test status
Simulation time 25371756 ps
CPU time 1.82 seconds
Started Feb 22 12:33:23 PM PST 24
Finished Feb 22 12:33:25 PM PST 24
Peak memory 212616 kb
Host smart-867285ff-d93c-476e-857a-89f4ab623ebe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853135104 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_csr_mem_rw_with_rand_reset.1853135104
Directory /workspace/15.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_csr_rw.2482844647
Short name T262
Test name
Test status
Simulation time 28333181 ps
CPU time 1.06 seconds
Started Feb 22 12:33:37 PM PST 24
Finished Feb 22 12:33:38 PM PST 24
Peak memory 204328 kb
Host smart-31889de9-a400-4cff-9df0-2f8d5264f712
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482844647 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_csr_rw.
2482844647
Directory /workspace/15.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_intr_test.2046347212
Short name T292
Test name
Test status
Simulation time 22836070 ps
CPU time 0.85 seconds
Started Feb 22 12:33:27 PM PST 24
Finished Feb 22 12:33:28 PM PST 24
Peak memory 204228 kb
Host smart-19dccf38-d13a-4172-809b-4134f77e13b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046347212 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_intr_test.
2046347212
Directory /workspace/15.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_same_csr_outstanding.973867590
Short name T188
Test name
Test status
Simulation time 293550699 ps
CPU time 2.68 seconds
Started Feb 22 12:33:18 PM PST 24
Finished Feb 22 12:33:26 PM PST 24
Peak memory 204404 kb
Host smart-f91fbfda-af7c-4bd6-ac2e-248fbbc48899
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973867590 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.k
eymgr_dpe_same_csr_outstanding.973867590
Directory /workspace/15.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors.3981151844
Short name T220
Test name
Test status
Simulation time 80978205 ps
CPU time 1.91 seconds
Started Feb 22 12:33:22 PM PST 24
Finished Feb 22 12:33:24 PM PST 24
Peak memory 212996 kb
Host smart-7958074a-d97a-43df-9d33-a53f2885db4f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981151844 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.key
mgr_dpe_shadow_reg_errors.3981151844
Directory /workspace/15.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors_with_csr_rw.979678323
Short name T198
Test name
Test status
Simulation time 237747370 ps
CPU time 5.69 seconds
Started Feb 22 12:33:44 PM PST 24
Finished Feb 22 12:33:50 PM PST 24
Peak memory 212872 kb
Host smart-8d74d19e-b7f3-42bf-85b5-945cce0120ad
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979678323 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 15.keymgr_dpe_shadow_reg_errors_with_csr_rw.979678323
Directory /workspace/15.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_tl_errors.4260903507
Short name T236
Test name
Test status
Simulation time 26413958 ps
CPU time 1.86 seconds
Started Feb 22 12:33:37 PM PST 24
Finished Feb 22 12:33:40 PM PST 24
Peak memory 212564 kb
Host smart-8e690c52-f06f-418f-a8a8-e6ec65ed8833
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260903507 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_tl_errors.
4260903507
Directory /workspace/15.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_tl_intg_err.1815329371
Short name T71
Test name
Test status
Simulation time 525874519 ps
CPU time 2.76 seconds
Started Feb 22 12:33:32 PM PST 24
Finished Feb 22 12:33:35 PM PST 24
Peak memory 213676 kb
Host smart-9f309cc8-6553-49ac-90a7-8ab30805d49e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815329371 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dp
e_tl_intg_err.1815329371
Directory /workspace/15.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_csr_mem_rw_with_rand_reset.3248004222
Short name T59
Test name
Test status
Simulation time 51445968 ps
CPU time 1.25 seconds
Started Feb 22 12:33:24 PM PST 24
Finished Feb 22 12:33:30 PM PST 24
Peak memory 212612 kb
Host smart-ce3cde98-da05-4646-b8fd-9d7b4b4f9496
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248004222 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_csr_mem_rw_with_rand_reset.3248004222
Directory /workspace/16.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_csr_rw.4135642991
Short name T174
Test name
Test status
Simulation time 412441897 ps
CPU time 1.08 seconds
Started Feb 22 12:33:18 PM PST 24
Finished Feb 22 12:33:19 PM PST 24
Peak memory 204160 kb
Host smart-d7dc6fc5-16ec-43b2-9044-c83b7e4655e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135642991 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_csr_rw.
4135642991
Directory /workspace/16.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_intr_test.138406721
Short name T281
Test name
Test status
Simulation time 10801959 ps
CPU time 0.74 seconds
Started Feb 22 12:33:39 PM PST 24
Finished Feb 22 12:33:40 PM PST 24
Peak memory 204248 kb
Host smart-6ed00691-2e0b-4de1-beff-c8f997625339
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138406721 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_intr_test.138406721
Directory /workspace/16.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_same_csr_outstanding.1600287261
Short name T98
Test name
Test status
Simulation time 27838844 ps
CPU time 1.77 seconds
Started Feb 22 12:33:27 PM PST 24
Finished Feb 22 12:33:29 PM PST 24
Peak memory 204440 kb
Host smart-6552bb31-1014-4dd8-9609-f0ea89bc9707
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600287261 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
keymgr_dpe_same_csr_outstanding.1600287261
Directory /workspace/16.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_shadow_reg_errors_with_csr_rw.3328422912
Short name T278
Test name
Test status
Simulation time 238966393 ps
CPU time 3.06 seconds
Started Feb 22 12:33:20 PM PST 24
Finished Feb 22 12:33:23 PM PST 24
Peak memory 212760 kb
Host smart-cd15efdc-a972-48d9-ba0a-4fa5d53a3ff0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328422912 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.keymgr_dpe_shadow_reg_errors_with_csr_rw.3328422912
Directory /workspace/16.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_errors.3153352945
Short name T27
Test name
Test status
Simulation time 366445757 ps
CPU time 1.95 seconds
Started Feb 22 12:33:14 PM PST 24
Finished Feb 22 12:33:16 PM PST 24
Peak memory 220608 kb
Host smart-b086196b-f03c-4234-b0d6-32b2813cb83e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153352945 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_tl_errors.
3153352945
Directory /workspace/16.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_intg_err.1843433983
Short name T293
Test name
Test status
Simulation time 92615794 ps
CPU time 4.02 seconds
Started Feb 22 12:33:19 PM PST 24
Finished Feb 22 12:33:23 PM PST 24
Peak memory 212688 kb
Host smart-86c360bb-5760-4ccd-ac68-005632b31f8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843433983 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dp
e_tl_intg_err.1843433983
Directory /workspace/16.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_csr_rw.2234694740
Short name T307
Test name
Test status
Simulation time 25927442 ps
CPU time 0.89 seconds
Started Feb 22 12:33:13 PM PST 24
Finished Feb 22 12:33:15 PM PST 24
Peak memory 204540 kb
Host smart-6bb3ff42-0db1-49a4-b267-e1ef5c83f4ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234694740 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_csr_rw.
2234694740
Directory /workspace/17.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_same_csr_outstanding.2468772980
Short name T185
Test name
Test status
Simulation time 182288596 ps
CPU time 2.14 seconds
Started Feb 22 12:33:18 PM PST 24
Finished Feb 22 12:33:20 PM PST 24
Peak memory 204336 kb
Host smart-391e576e-cb28-4261-ab41-8046643d28a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468772980 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
keymgr_dpe_same_csr_outstanding.2468772980
Directory /workspace/17.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_shadow_reg_errors.3138186906
Short name T183
Test name
Test status
Simulation time 60865447 ps
CPU time 2.38 seconds
Started Feb 22 12:33:36 PM PST 24
Finished Feb 22 12:33:39 PM PST 24
Peak memory 212976 kb
Host smart-7158cb45-afbb-4877-aba1-99c744caf449
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138186906 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.key
mgr_dpe_shadow_reg_errors.3138186906
Directory /workspace/17.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_shadow_reg_errors_with_csr_rw.3355959751
Short name T222
Test name
Test status
Simulation time 54156810 ps
CPU time 2.2 seconds
Started Feb 22 12:33:27 PM PST 24
Finished Feb 22 12:33:29 PM PST 24
Peak memory 212968 kb
Host smart-1f435c5e-6add-44e0-8b1c-dcfc449281fd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355959751 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.keymgr_dpe_shadow_reg_errors_with_csr_rw.3355959751
Directory /workspace/17.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_tl_errors.2956326148
Short name T261
Test name
Test status
Simulation time 18945003 ps
CPU time 1.53 seconds
Started Feb 22 12:33:17 PM PST 24
Finished Feb 22 12:33:19 PM PST 24
Peak memory 220824 kb
Host smart-fe2cec0d-541b-4e0b-a3ad-ee8315dfed11
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956326148 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_tl_errors.
2956326148
Directory /workspace/17.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_csr_mem_rw_with_rand_reset.2713177611
Short name T286
Test name
Test status
Simulation time 19516379 ps
CPU time 1.53 seconds
Started Feb 22 12:33:21 PM PST 24
Finished Feb 22 12:33:23 PM PST 24
Peak memory 212648 kb
Host smart-af3b1f6a-3008-4e1f-82f7-09d2ff1a9150
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713177611 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_csr_mem_rw_with_rand_reset.2713177611
Directory /workspace/18.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_csr_rw.96291003
Short name T216
Test name
Test status
Simulation time 22055572 ps
CPU time 0.9 seconds
Started Feb 22 12:33:29 PM PST 24
Finished Feb 22 12:33:30 PM PST 24
Peak memory 204196 kb
Host smart-ab932e4b-7453-464e-bbf0-d8fd101a74e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96291003 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_csr_rw.96291003
Directory /workspace/18.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_same_csr_outstanding.130474358
Short name T285
Test name
Test status
Simulation time 68167467 ps
CPU time 1.85 seconds
Started Feb 22 12:33:21 PM PST 24
Finished Feb 22 12:33:23 PM PST 24
Peak memory 204424 kb
Host smart-7500117a-43c7-4214-9cfd-214377c1115f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130474358 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.k
eymgr_dpe_same_csr_outstanding.130474358
Directory /workspace/18.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_shadow_reg_errors.3051904498
Short name T238
Test name
Test status
Simulation time 78308390 ps
CPU time 1.8 seconds
Started Feb 22 12:33:26 PM PST 24
Finished Feb 22 12:33:28 PM PST 24
Peak memory 212844 kb
Host smart-b124187b-625d-4b9c-bbb7-403637df5157
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051904498 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.key
mgr_dpe_shadow_reg_errors.3051904498
Directory /workspace/18.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_shadow_reg_errors_with_csr_rw.2371262349
Short name T201
Test name
Test status
Simulation time 876945815 ps
CPU time 4.88 seconds
Started Feb 22 12:33:42 PM PST 24
Finished Feb 22 12:33:47 PM PST 24
Peak memory 212952 kb
Host smart-e4b93d26-726a-4e69-83bd-035abe655f54
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371262349 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.keymgr_dpe_shadow_reg_errors_with_csr_rw.2371262349
Directory /workspace/18.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_tl_errors.320045087
Short name T28
Test name
Test status
Simulation time 884137007 ps
CPU time 1.87 seconds
Started Feb 22 12:33:36 PM PST 24
Finished Feb 22 12:33:39 PM PST 24
Peak memory 220804 kb
Host smart-b6d58fa1-2d6b-4189-a546-5165ca24a3c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320045087 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_tl_errors.320045087
Directory /workspace/18.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_csr_mem_rw_with_rand_reset.1083235583
Short name T270
Test name
Test status
Simulation time 26522686 ps
CPU time 1.48 seconds
Started Feb 22 12:33:23 PM PST 24
Finished Feb 22 12:33:25 PM PST 24
Peak memory 220872 kb
Host smart-2852c09a-fab6-47a2-8b2e-1e481a25421b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083235583 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_csr_mem_rw_with_rand_reset.1083235583
Directory /workspace/19.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_csr_rw.2492774171
Short name T179
Test name
Test status
Simulation time 163602532 ps
CPU time 1.12 seconds
Started Feb 22 12:33:22 PM PST 24
Finished Feb 22 12:33:24 PM PST 24
Peak memory 204364 kb
Host smart-2b0238ef-d764-4857-9123-822862df211b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492774171 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_csr_rw.
2492774171
Directory /workspace/19.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_intr_test.1424684737
Short name T243
Test name
Test status
Simulation time 13949799 ps
CPU time 0.77 seconds
Started Feb 22 12:33:11 PM PST 24
Finished Feb 22 12:33:13 PM PST 24
Peak memory 204220 kb
Host smart-9a043240-a48a-4100-851f-b54c224d9c20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424684737 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_intr_test.
1424684737
Directory /workspace/19.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_same_csr_outstanding.94715773
Short name T100
Test name
Test status
Simulation time 22175660 ps
CPU time 1.23 seconds
Started Feb 22 12:33:19 PM PST 24
Finished Feb 22 12:33:20 PM PST 24
Peak memory 204460 kb
Host smart-b1bab193-08a9-4aa2-9a2e-97a8a2d5fdd4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94715773 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=k
eymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ke
ymgr_dpe_same_csr_outstanding.94715773
Directory /workspace/19.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_shadow_reg_errors.1455589804
Short name T221
Test name
Test status
Simulation time 47994174 ps
CPU time 1.88 seconds
Started Feb 22 12:33:34 PM PST 24
Finished Feb 22 12:33:36 PM PST 24
Peak memory 212956 kb
Host smart-eba45437-dab6-4daa-aa5c-49aa00e07685
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455589804 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.key
mgr_dpe_shadow_reg_errors.1455589804
Directory /workspace/19.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_shadow_reg_errors_with_csr_rw.570960717
Short name T306
Test name
Test status
Simulation time 283446370 ps
CPU time 4.71 seconds
Started Feb 22 12:33:38 PM PST 24
Finished Feb 22 12:33:43 PM PST 24
Peak memory 212868 kb
Host smart-397e703d-003b-426c-aacf-28f8f0d642ea
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570960717 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 19.keymgr_dpe_shadow_reg_errors_with_csr_rw.570960717
Directory /workspace/19.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_tl_errors.177247399
Short name T56
Test name
Test status
Simulation time 134414652 ps
CPU time 1.89 seconds
Started Feb 22 12:33:21 PM PST 24
Finished Feb 22 12:33:23 PM PST 24
Peak memory 212640 kb
Host smart-9f0c1bc8-2ea2-495b-bb84-ece7a05ba80e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177247399 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_tl_errors.177247399
Directory /workspace/19.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_aliasing.669240205
Short name T234
Test name
Test status
Simulation time 279713576 ps
CPU time 5.12 seconds
Started Feb 22 12:33:06 PM PST 24
Finished Feb 22 12:33:11 PM PST 24
Peak memory 204348 kb
Host smart-28c7cd9b-b5b2-4bf6-bd16-15b4cb22a2b0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669240205 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr
_aliasing.669240205
Directory /workspace/2.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_bit_bash.652014164
Short name T287
Test name
Test status
Simulation time 429412955 ps
CPU time 11.47 seconds
Started Feb 22 12:33:07 PM PST 24
Finished Feb 22 12:33:19 PM PST 24
Peak memory 204464 kb
Host smart-aefb0aa9-0a6a-48b5-a935-510f13cb21cf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652014164 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr
_bit_bash.652014164
Directory /workspace/2.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_hw_reset.125074318
Short name T215
Test name
Test status
Simulation time 89303177 ps
CPU time 1.02 seconds
Started Feb 22 12:33:13 PM PST 24
Finished Feb 22 12:33:15 PM PST 24
Peak memory 204284 kb
Host smart-ffe680f3-1dc3-4495-ad83-61eeaa881a21
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125074318 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr
_hw_reset.125074318
Directory /workspace/2.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_mem_rw_with_rand_reset.1286937227
Short name T276
Test name
Test status
Simulation time 31008727 ps
CPU time 1.58 seconds
Started Feb 22 12:33:08 PM PST 24
Finished Feb 22 12:33:10 PM PST 24
Peak memory 212688 kb
Host smart-d8ae93ce-c95a-49e5-a7ae-4091e1dea3ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286937227 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr_mem_rw_with_rand_reset.1286937227
Directory /workspace/2.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_rw.3548645966
Short name T239
Test name
Test status
Simulation time 30542836 ps
CPU time 1.02 seconds
Started Feb 22 12:33:07 PM PST 24
Finished Feb 22 12:33:09 PM PST 24
Peak memory 204256 kb
Host smart-62e39cfa-3c31-4425-ad67-ac820f82220b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548645966 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr_rw.3
548645966
Directory /workspace/2.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_intr_test.3768212267
Short name T51
Test name
Test status
Simulation time 12023669 ps
CPU time 0.69 seconds
Started Feb 22 12:33:11 PM PST 24
Finished Feb 22 12:33:12 PM PST 24
Peak memory 204244 kb
Host smart-061634ef-ef8b-4fad-abe6-7580ee96ce8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768212267 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_intr_test.3
768212267
Directory /workspace/2.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_same_csr_outstanding.1564290205
Short name T46
Test name
Test status
Simulation time 50986430 ps
CPU time 1.6 seconds
Started Feb 22 12:33:06 PM PST 24
Finished Feb 22 12:33:07 PM PST 24
Peak memory 204348 kb
Host smart-735569ad-ba35-429a-82c3-2198a7dd4c7c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564290205 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.k
eymgr_dpe_same_csr_outstanding.1564290205
Directory /workspace/2.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_shadow_reg_errors.3706142026
Short name T187
Test name
Test status
Simulation time 128433432 ps
CPU time 2.08 seconds
Started Feb 22 12:33:08 PM PST 24
Finished Feb 22 12:33:11 PM PST 24
Peak memory 212864 kb
Host smart-74b40c51-03b1-496c-85a1-dd4a64ff17f4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706142026 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keym
gr_dpe_shadow_reg_errors.3706142026
Directory /workspace/2.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_shadow_reg_errors_with_csr_rw.3349620006
Short name T308
Test name
Test status
Simulation time 132581435 ps
CPU time 4.44 seconds
Started Feb 22 12:33:07 PM PST 24
Finished Feb 22 12:33:12 PM PST 24
Peak memory 213008 kb
Host smart-4d326a2f-7fdb-40ce-b741-99343d55899a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349620006 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.keymgr_dpe_shadow_reg_errors_with_csr_rw.3349620006
Directory /workspace/2.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_tl_errors.1083542618
Short name T254
Test name
Test status
Simulation time 117472141 ps
CPU time 1.98 seconds
Started Feb 22 12:33:11 PM PST 24
Finished Feb 22 12:33:14 PM PST 24
Peak memory 212644 kb
Host smart-073b9720-9ed5-426f-aaf0-db8607a7605c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083542618 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_tl_errors.1
083542618
Directory /workspace/2.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_dpe_intr_test.3678448667
Short name T52
Test name
Test status
Simulation time 38781345 ps
CPU time 0.7 seconds
Started Feb 22 12:33:23 PM PST 24
Finished Feb 22 12:33:24 PM PST 24
Peak memory 204200 kb
Host smart-dd1b7295-4eab-48d8-80f6-bba47a60a754
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678448667 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_intr_test.
3678448667
Directory /workspace/20.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_dpe_intr_test.1561279253
Short name T126
Test name
Test status
Simulation time 10812045 ps
CPU time 0.71 seconds
Started Feb 22 12:33:25 PM PST 24
Finished Feb 22 12:33:25 PM PST 24
Peak memory 204276 kb
Host smart-6550a9f1-b8f6-43f6-9d49-c95d7b1e9cd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561279253 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_intr_test.
1561279253
Directory /workspace/21.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_dpe_intr_test.621802009
Short name T282
Test name
Test status
Simulation time 36021262 ps
CPU time 0.73 seconds
Started Feb 22 12:33:13 PM PST 24
Finished Feb 22 12:33:14 PM PST 24
Peak memory 204152 kb
Host smart-fff39ea5-3d10-4b6f-a6a2-c276b221e69a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621802009 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_intr_test.621802009
Directory /workspace/22.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_dpe_intr_test.3721007942
Short name T81
Test name
Test status
Simulation time 38734017 ps
CPU time 0.74 seconds
Started Feb 22 12:33:18 PM PST 24
Finished Feb 22 12:33:19 PM PST 24
Peak memory 204188 kb
Host smart-04c5987f-53e1-47e5-bb11-c1e6ee13fd58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721007942 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_intr_test.
3721007942
Directory /workspace/23.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_dpe_intr_test.1794433610
Short name T223
Test name
Test status
Simulation time 46284075 ps
CPU time 0.82 seconds
Started Feb 22 12:33:17 PM PST 24
Finished Feb 22 12:33:18 PM PST 24
Peak memory 204276 kb
Host smart-024263a7-759e-4642-8cb9-dcc9de1dc8a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794433610 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_intr_test.
1794433610
Directory /workspace/24.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_dpe_intr_test.2852935080
Short name T217
Test name
Test status
Simulation time 10833981 ps
CPU time 0.72 seconds
Started Feb 22 12:33:18 PM PST 24
Finished Feb 22 12:33:19 PM PST 24
Peak memory 204144 kb
Host smart-9d63ed8b-0e18-44b2-91ea-98efca2c3691
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852935080 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_intr_test.
2852935080
Directory /workspace/25.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_dpe_intr_test.3275801534
Short name T214
Test name
Test status
Simulation time 16281295 ps
CPU time 0.79 seconds
Started Feb 22 12:33:27 PM PST 24
Finished Feb 22 12:33:28 PM PST 24
Peak memory 204236 kb
Host smart-eebfd048-bcbe-43c4-8aa3-bb1cd4151439
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275801534 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_intr_test.
3275801534
Directory /workspace/26.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_dpe_intr_test.3061387895
Short name T203
Test name
Test status
Simulation time 12360522 ps
CPU time 0.88 seconds
Started Feb 22 12:33:54 PM PST 24
Finished Feb 22 12:33:55 PM PST 24
Peak memory 204240 kb
Host smart-e3a54e88-1605-4da9-89a4-031c3776bca7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061387895 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_intr_test.
3061387895
Directory /workspace/27.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_dpe_intr_test.708121211
Short name T105
Test name
Test status
Simulation time 152737035 ps
CPU time 0.72 seconds
Started Feb 22 12:33:23 PM PST 24
Finished Feb 22 12:33:24 PM PST 24
Peak memory 204160 kb
Host smart-8574b6a0-1e0c-4daa-b289-35e3eb1aaafb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708121211 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_intr_test.708121211
Directory /workspace/28.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_dpe_intr_test.4000493360
Short name T267
Test name
Test status
Simulation time 51864474 ps
CPU time 0.73 seconds
Started Feb 22 12:33:34 PM PST 24
Finished Feb 22 12:33:35 PM PST 24
Peak memory 204208 kb
Host smart-0e22985e-74ac-4c15-91aa-b082d6c7c7fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000493360 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_intr_test.
4000493360
Directory /workspace/29.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_aliasing.1111969665
Short name T265
Test name
Test status
Simulation time 599989748 ps
CPU time 5.7 seconds
Started Feb 22 12:33:11 PM PST 24
Finished Feb 22 12:33:17 PM PST 24
Peak memory 204284 kb
Host smart-9861bda6-64a4-47c6-82d5-88b8be673a12
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111969665 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_cs
r_aliasing.1111969665
Directory /workspace/3.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_bit_bash.306825768
Short name T228
Test name
Test status
Simulation time 916624643 ps
CPU time 11.8 seconds
Started Feb 22 12:33:11 PM PST 24
Finished Feb 22 12:33:24 PM PST 24
Peak memory 204444 kb
Host smart-6eecc19f-f55a-4d36-91b6-15c4c89a9c78
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306825768 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_csr
_bit_bash.306825768
Directory /workspace/3.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_hw_reset.1049157695
Short name T47
Test name
Test status
Simulation time 15769735 ps
CPU time 0.97 seconds
Started Feb 22 12:33:04 PM PST 24
Finished Feb 22 12:33:05 PM PST 24
Peak memory 204288 kb
Host smart-429f55f8-3d49-4a49-a1eb-8037419af9af
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049157695 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_cs
r_hw_reset.1049157695
Directory /workspace/3.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_mem_rw_with_rand_reset.1429728226
Short name T61
Test name
Test status
Simulation time 29751289 ps
CPU time 1.3 seconds
Started Feb 22 12:33:13 PM PST 24
Finished Feb 22 12:33:19 PM PST 24
Peak memory 220272 kb
Host smart-c0601278-ea3f-4787-b931-c48a652b71ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429728226 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_csr_mem_rw_with_rand_reset.1429728226
Directory /workspace/3.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_rw.275777233
Short name T96
Test name
Test status
Simulation time 113568342 ps
CPU time 0.96 seconds
Started Feb 22 12:33:13 PM PST 24
Finished Feb 22 12:33:15 PM PST 24
Peak memory 204164 kb
Host smart-9b2dac97-8da5-4d5b-a948-d574754d84c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275777233 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_csr_rw.275777233
Directory /workspace/3.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_intr_test.67758437
Short name T258
Test name
Test status
Simulation time 35419138 ps
CPU time 0.79 seconds
Started Feb 22 12:33:09 PM PST 24
Finished Feb 22 12:33:11 PM PST 24
Peak memory 204208 kb
Host smart-3a8ce352-fcc0-4a4f-99fd-d8fcabe1edfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67758437 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_intr_test.67758437
Directory /workspace/3.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_same_csr_outstanding.1397519341
Short name T266
Test name
Test status
Simulation time 111494265 ps
CPU time 2.15 seconds
Started Feb 22 12:33:07 PM PST 24
Finished Feb 22 12:33:09 PM PST 24
Peak memory 204500 kb
Host smart-87d296af-80de-43f9-adb1-7db93d3ad06e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397519341 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.k
eymgr_dpe_same_csr_outstanding.1397519341
Directory /workspace/3.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_shadow_reg_errors.2344581263
Short name T79
Test name
Test status
Simulation time 100314643 ps
CPU time 1.28 seconds
Started Feb 22 12:33:09 PM PST 24
Finished Feb 22 12:33:11 PM PST 24
Peak memory 212984 kb
Host smart-b1b07c1d-3767-4a1c-99ec-c1058318f7d8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344581263 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keym
gr_dpe_shadow_reg_errors.2344581263
Directory /workspace/3.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_shadow_reg_errors_with_csr_rw.737916408
Short name T195
Test name
Test status
Simulation time 1107097494 ps
CPU time 6.15 seconds
Started Feb 22 12:33:03 PM PST 24
Finished Feb 22 12:33:09 PM PST 24
Peak memory 212860 kb
Host smart-734b6970-d3a1-47d5-a378-82c8b8d71e92
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737916408 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 3.keymgr_dpe_shadow_reg_errors_with_csr_rw.737916408
Directory /workspace/3.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_dpe_intr_test.3439363771
Short name T193
Test name
Test status
Simulation time 12801232 ps
CPU time 0.73 seconds
Started Feb 22 12:33:41 PM PST 24
Finished Feb 22 12:33:42 PM PST 24
Peak memory 204220 kb
Host smart-b93f16d5-5e62-4ba4-9983-ffa95944e3fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439363771 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_intr_test.
3439363771
Directory /workspace/30.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_dpe_intr_test.1443379772
Short name T108
Test name
Test status
Simulation time 10939734 ps
CPU time 0.75 seconds
Started Feb 22 12:33:47 PM PST 24
Finished Feb 22 12:33:47 PM PST 24
Peak memory 204280 kb
Host smart-00611e89-c6a0-4dda-86e0-03ac65bdccae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443379772 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_intr_test.
1443379772
Directory /workspace/31.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_dpe_intr_test.2599450757
Short name T309
Test name
Test status
Simulation time 12315063 ps
CPU time 0.89 seconds
Started Feb 22 12:33:48 PM PST 24
Finished Feb 22 12:33:49 PM PST 24
Peak memory 204244 kb
Host smart-a86f1fdd-f112-40e8-9f93-d8899766687f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599450757 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_intr_test.
2599450757
Directory /workspace/32.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_dpe_intr_test.2146007843
Short name T210
Test name
Test status
Simulation time 13593302 ps
CPU time 0.87 seconds
Started Feb 22 12:33:45 PM PST 24
Finished Feb 22 12:33:47 PM PST 24
Peak memory 204264 kb
Host smart-89502827-120a-4c24-828a-024e6c2f0d8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146007843 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_intr_test.
2146007843
Directory /workspace/33.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_dpe_intr_test.2195052813
Short name T294
Test name
Test status
Simulation time 28548218 ps
CPU time 0.84 seconds
Started Feb 22 12:33:42 PM PST 24
Finished Feb 22 12:33:43 PM PST 24
Peak memory 204260 kb
Host smart-c5bf1678-c79b-4121-b891-fac0b2dcfffe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195052813 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_intr_test.
2195052813
Directory /workspace/34.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_dpe_intr_test.4079370897
Short name T244
Test name
Test status
Simulation time 10066484 ps
CPU time 0.74 seconds
Started Feb 22 12:33:50 PM PST 24
Finished Feb 22 12:33:51 PM PST 24
Peak memory 204228 kb
Host smart-926d880a-85a4-47a8-b0e3-d394d14910ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079370897 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_intr_test.
4079370897
Directory /workspace/35.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_dpe_intr_test.3559337039
Short name T253
Test name
Test status
Simulation time 173620989 ps
CPU time 0.8 seconds
Started Feb 22 12:33:44 PM PST 24
Finished Feb 22 12:33:45 PM PST 24
Peak memory 204240 kb
Host smart-2c89761f-67cf-4b4d-aaf2-98b910c23a38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559337039 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_intr_test.
3559337039
Directory /workspace/36.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_dpe_intr_test.2045504264
Short name T297
Test name
Test status
Simulation time 19701448 ps
CPU time 0.82 seconds
Started Feb 22 12:33:36 PM PST 24
Finished Feb 22 12:33:37 PM PST 24
Peak memory 204236 kb
Host smart-c110a225-288e-4672-b681-2cbc6d151e5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045504264 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_intr_test.
2045504264
Directory /workspace/37.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_dpe_intr_test.3143971305
Short name T107
Test name
Test status
Simulation time 12811538 ps
CPU time 0.76 seconds
Started Feb 22 12:33:39 PM PST 24
Finished Feb 22 12:33:40 PM PST 24
Peak memory 204180 kb
Host smart-1f368f31-9907-4a10-aa34-b4992971a27d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143971305 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_intr_test.
3143971305
Directory /workspace/38.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_dpe_intr_test.3413014330
Short name T240
Test name
Test status
Simulation time 10278227 ps
CPU time 0.78 seconds
Started Feb 22 12:33:41 PM PST 24
Finished Feb 22 12:33:42 PM PST 24
Peak memory 204136 kb
Host smart-540daa92-585d-4897-bd16-ad22b6ffebc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413014330 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_intr_test.
3413014330
Directory /workspace/39.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_aliasing.1230839430
Short name T181
Test name
Test status
Simulation time 236051838 ps
CPU time 4.47 seconds
Started Feb 22 12:33:16 PM PST 24
Finished Feb 22 12:33:20 PM PST 24
Peak memory 204444 kb
Host smart-0ab4893a-e1ec-451f-8894-753caea8964c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230839430 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_cs
r_aliasing.1230839430
Directory /workspace/4.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_bit_bash.367728959
Short name T225
Test name
Test status
Simulation time 1799439436 ps
CPU time 10.45 seconds
Started Feb 22 12:33:13 PM PST 24
Finished Feb 22 12:33:25 PM PST 24
Peak memory 204372 kb
Host smart-84da6b17-b6a1-4e7c-b572-116142d55261
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367728959 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_csr
_bit_bash.367728959
Directory /workspace/4.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_hw_reset.3910252286
Short name T300
Test name
Test status
Simulation time 85496140 ps
CPU time 0.96 seconds
Started Feb 22 12:33:07 PM PST 24
Finished Feb 22 12:33:08 PM PST 24
Peak memory 204288 kb
Host smart-41ec3fb2-6f9d-4efc-b9d6-bc7c0a0fc0ce
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910252286 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_cs
r_hw_reset.3910252286
Directory /workspace/4.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_mem_rw_with_rand_reset.1242258024
Short name T199
Test name
Test status
Simulation time 15708707 ps
CPU time 1.46 seconds
Started Feb 22 12:33:12 PM PST 24
Finished Feb 22 12:33:14 PM PST 24
Peak memory 212736 kb
Host smart-c33c6dbe-47e0-4561-a2b4-bd663d71b7d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242258024 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_csr_mem_rw_with_rand_reset.1242258024
Directory /workspace/4.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_rw.1625861123
Short name T204
Test name
Test status
Simulation time 44463761 ps
CPU time 1.06 seconds
Started Feb 22 12:33:13 PM PST 24
Finished Feb 22 12:33:15 PM PST 24
Peak memory 204400 kb
Host smart-9c96d0c6-2f86-4441-9678-9ceafec8f9ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625861123 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_csr_rw.1
625861123
Directory /workspace/4.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_intr_test.4066929405
Short name T255
Test name
Test status
Simulation time 51458899 ps
CPU time 0.73 seconds
Started Feb 22 12:33:06 PM PST 24
Finished Feb 22 12:33:07 PM PST 24
Peak memory 204212 kb
Host smart-9df11666-4e8e-42f2-859e-f47369057a88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066929405 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_intr_test.4
066929405
Directory /workspace/4.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_same_csr_outstanding.4113214123
Short name T246
Test name
Test status
Simulation time 44452675 ps
CPU time 1.6 seconds
Started Feb 22 12:33:16 PM PST 24
Finished Feb 22 12:33:18 PM PST 24
Peak memory 204464 kb
Host smart-50f6cf26-de5d-411d-8dd9-56997bf4e494
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113214123 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.k
eymgr_dpe_same_csr_outstanding.4113214123
Directory /workspace/4.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_shadow_reg_errors.121320980
Short name T279
Test name
Test status
Simulation time 75544939 ps
CPU time 1.73 seconds
Started Feb 22 12:33:11 PM PST 24
Finished Feb 22 12:33:14 PM PST 24
Peak memory 212964 kb
Host smart-29cd6511-d800-4562-9bff-a6188465e2e2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121320980 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymg
r_dpe_shadow_reg_errors.121320980
Directory /workspace/4.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_shadow_reg_errors_with_csr_rw.3064521556
Short name T209
Test name
Test status
Simulation time 124456185 ps
CPU time 3.14 seconds
Started Feb 22 12:33:06 PM PST 24
Finished Feb 22 12:33:09 PM PST 24
Peak memory 212920 kb
Host smart-aeb1f1c4-a6e7-404f-a06e-ef3faadf564e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064521556 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.keymgr_dpe_shadow_reg_errors_with_csr_rw.3064521556
Directory /workspace/4.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_tl_errors.499247503
Short name T247
Test name
Test status
Simulation time 93431100 ps
CPU time 3.49 seconds
Started Feb 22 12:33:12 PM PST 24
Finished Feb 22 12:33:16 PM PST 24
Peak memory 215012 kb
Host smart-7b6fedf1-3f67-4a75-bd56-e3bcda120e71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499247503 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_tl_errors.499247503
Directory /workspace/4.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_dpe_intr_test.2326199962
Short name T109
Test name
Test status
Simulation time 39077660 ps
CPU time 0.73 seconds
Started Feb 22 12:33:59 PM PST 24
Finished Feb 22 12:34:00 PM PST 24
Peak memory 204108 kb
Host smart-8968337c-e992-479a-b13e-51246d1df404
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326199962 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_intr_test.
2326199962
Directory /workspace/40.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_dpe_intr_test.3026181406
Short name T277
Test name
Test status
Simulation time 13743164 ps
CPU time 0.83 seconds
Started Feb 22 12:33:44 PM PST 24
Finished Feb 22 12:33:45 PM PST 24
Peak memory 204196 kb
Host smart-0470ede8-e769-464b-bed9-a6256f22499b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026181406 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_intr_test.
3026181406
Directory /workspace/41.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_dpe_intr_test.2040425177
Short name T173
Test name
Test status
Simulation time 36522648 ps
CPU time 0.8 seconds
Started Feb 22 12:33:51 PM PST 24
Finished Feb 22 12:33:52 PM PST 24
Peak memory 204244 kb
Host smart-46ffb70f-d773-443a-9c7f-5ba3dd352684
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040425177 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_intr_test.
2040425177
Directory /workspace/42.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_dpe_intr_test.684664166
Short name T302
Test name
Test status
Simulation time 16453036 ps
CPU time 0.98 seconds
Started Feb 22 12:33:50 PM PST 24
Finished Feb 22 12:33:52 PM PST 24
Peak memory 204324 kb
Host smart-56524341-fd63-4491-90f6-c6414ca9668a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684664166 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_intr_test.684664166
Directory /workspace/43.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_dpe_intr_test.1735858047
Short name T248
Test name
Test status
Simulation time 24593896 ps
CPU time 0.77 seconds
Started Feb 22 12:33:57 PM PST 24
Finished Feb 22 12:33:57 PM PST 24
Peak memory 204228 kb
Host smart-8e9c45c5-2210-48f3-bcb3-ada7a68813a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735858047 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_intr_test.
1735858047
Directory /workspace/44.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_dpe_intr_test.116226824
Short name T84
Test name
Test status
Simulation time 13750627 ps
CPU time 0.87 seconds
Started Feb 22 12:33:57 PM PST 24
Finished Feb 22 12:33:58 PM PST 24
Peak memory 204336 kb
Host smart-7a148bfd-2aed-48eb-b368-23151e46cb67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116226824 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_intr_test.116226824
Directory /workspace/45.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_dpe_intr_test.4149776297
Short name T232
Test name
Test status
Simulation time 41449702 ps
CPU time 0.71 seconds
Started Feb 22 12:33:42 PM PST 24
Finished Feb 22 12:33:43 PM PST 24
Peak memory 204236 kb
Host smart-8a673b02-bc9f-4146-812f-bebc8390860a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149776297 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_intr_test.
4149776297
Directory /workspace/46.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_dpe_intr_test.1613411544
Short name T200
Test name
Test status
Simulation time 51828896 ps
CPU time 0.74 seconds
Started Feb 22 12:33:29 PM PST 24
Finished Feb 22 12:33:30 PM PST 24
Peak memory 204236 kb
Host smart-614f50fa-95d5-4a91-92ee-571167bfd77c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613411544 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_intr_test.
1613411544
Directory /workspace/47.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_dpe_intr_test.1201292224
Short name T171
Test name
Test status
Simulation time 42967937 ps
CPU time 0.71 seconds
Started Feb 22 12:33:39 PM PST 24
Finished Feb 22 12:33:40 PM PST 24
Peak memory 204212 kb
Host smart-38743e8f-d078-46a3-af16-8a606376b3e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201292224 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_intr_test.
1201292224
Directory /workspace/48.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_dpe_intr_test.1884840944
Short name T263
Test name
Test status
Simulation time 14126473 ps
CPU time 0.89 seconds
Started Feb 22 12:33:40 PM PST 24
Finished Feb 22 12:33:41 PM PST 24
Peak memory 204260 kb
Host smart-5427d57c-5658-4ca1-a96d-fa7d824163e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884840944 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_intr_test.
1884840944
Directory /workspace/49.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_csr_mem_rw_with_rand_reset.1784182374
Short name T226
Test name
Test status
Simulation time 47921466 ps
CPU time 1.16 seconds
Started Feb 22 12:33:11 PM PST 24
Finished Feb 22 12:33:13 PM PST 24
Peak memory 204456 kb
Host smart-186c66c4-8373-4559-8048-43dc9613861a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784182374 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_csr_mem_rw_with_rand_reset.1784182374
Directory /workspace/5.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_csr_rw.4001254498
Short name T224
Test name
Test status
Simulation time 160334758 ps
CPU time 0.84 seconds
Started Feb 22 12:33:16 PM PST 24
Finished Feb 22 12:33:17 PM PST 24
Peak memory 204244 kb
Host smart-6e6a3227-d8b5-4298-8b78-7a8e7b65aeaa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001254498 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_csr_rw.4
001254498
Directory /workspace/5.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_intr_test.3850947803
Short name T178
Test name
Test status
Simulation time 12961589 ps
CPU time 0.77 seconds
Started Feb 22 12:33:08 PM PST 24
Finished Feb 22 12:33:09 PM PST 24
Peak memory 204116 kb
Host smart-61b0489e-681f-4da2-b2d3-323af1c4ed31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850947803 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_intr_test.3
850947803
Directory /workspace/5.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_same_csr_outstanding.1229875289
Short name T182
Test name
Test status
Simulation time 163194070 ps
CPU time 1.51 seconds
Started Feb 22 12:33:16 PM PST 24
Finished Feb 22 12:33:17 PM PST 24
Peak memory 204452 kb
Host smart-f51b29b5-84b9-4e5f-bc2b-ffe21da340ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229875289 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.k
eymgr_dpe_same_csr_outstanding.1229875289
Directory /workspace/5.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_shadow_reg_errors.2514487740
Short name T170
Test name
Test status
Simulation time 67444738 ps
CPU time 2.5 seconds
Started Feb 22 12:33:06 PM PST 24
Finished Feb 22 12:33:08 PM PST 24
Peak memory 212908 kb
Host smart-b70659f5-a115-4dc4-a5a4-073882fe4925
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514487740 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keym
gr_dpe_shadow_reg_errors.2514487740
Directory /workspace/5.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_shadow_reg_errors_with_csr_rw.2819142745
Short name T184
Test name
Test status
Simulation time 242799458 ps
CPU time 2.8 seconds
Started Feb 22 12:33:15 PM PST 24
Finished Feb 22 12:33:18 PM PST 24
Peak memory 212988 kb
Host smart-20b25ced-207e-4686-af7b-83e8c7a7404a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819142745 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.keymgr_dpe_shadow_reg_errors_with_csr_rw.2819142745
Directory /workspace/5.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_tl_errors.1519292212
Short name T268
Test name
Test status
Simulation time 221414807 ps
CPU time 1.57 seconds
Started Feb 22 12:33:03 PM PST 24
Finished Feb 22 12:33:05 PM PST 24
Peak memory 212624 kb
Host smart-9e1d8df8-7466-4ff9-8192-05cf2e8f0ba6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519292212 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_tl_errors.1
519292212
Directory /workspace/5.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_csr_mem_rw_with_rand_reset.319573259
Short name T48
Test name
Test status
Simulation time 43147811 ps
CPU time 1.75 seconds
Started Feb 22 12:33:13 PM PST 24
Finished Feb 22 12:33:18 PM PST 24
Peak memory 212560 kb
Host smart-7e6e3590-2150-4dde-b8db-6a769422372b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319573259 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_csr_mem_rw_with_rand_reset.319573259
Directory /workspace/6.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_csr_rw.2413867124
Short name T45
Test name
Test status
Simulation time 39054793 ps
CPU time 0.8 seconds
Started Feb 22 12:33:11 PM PST 24
Finished Feb 22 12:33:12 PM PST 24
Peak memory 204216 kb
Host smart-a6802353-aa60-4c4c-aa30-f9f6f3116f8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413867124 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_csr_rw.2
413867124
Directory /workspace/6.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_intr_test.896769160
Short name T274
Test name
Test status
Simulation time 8304310 ps
CPU time 0.73 seconds
Started Feb 22 12:33:26 PM PST 24
Finished Feb 22 12:33:27 PM PST 24
Peak memory 204288 kb
Host smart-02f47b1b-4f72-4a4d-a9b1-aaa3604f3bfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896769160 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_intr_test.896769160
Directory /workspace/6.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_same_csr_outstanding.1300969505
Short name T305
Test name
Test status
Simulation time 175714935 ps
CPU time 1.43 seconds
Started Feb 22 12:33:10 PM PST 24
Finished Feb 22 12:33:12 PM PST 24
Peak memory 204452 kb
Host smart-1b5b68b5-136a-402a-b328-25bd67152e1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300969505 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.k
eymgr_dpe_same_csr_outstanding.1300969505
Directory /workspace/6.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_shadow_reg_errors.163056350
Short name T212
Test name
Test status
Simulation time 40147548 ps
CPU time 1.71 seconds
Started Feb 22 12:33:16 PM PST 24
Finished Feb 22 12:33:18 PM PST 24
Peak memory 212872 kb
Host smart-691dba40-c816-41c5-bfcb-d0ea88e253ea
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163056350 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymg
r_dpe_shadow_reg_errors.163056350
Directory /workspace/6.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_tl_errors.3307644727
Short name T77
Test name
Test status
Simulation time 48611003 ps
CPU time 1.52 seconds
Started Feb 22 12:33:16 PM PST 24
Finished Feb 22 12:33:18 PM PST 24
Peak memory 212680 kb
Host smart-a19079c6-cf4c-44bf-94f8-87d719475986
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307644727 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_tl_errors.3
307644727
Directory /workspace/6.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_tl_intg_err.1805197117
Short name T125
Test name
Test status
Simulation time 350509107 ps
CPU time 2.75 seconds
Started Feb 22 12:33:16 PM PST 24
Finished Feb 22 12:33:19 PM PST 24
Peak memory 212564 kb
Host smart-8712fbdf-02c0-4694-8d88-b150e0bc6e92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805197117 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe
_tl_intg_err.1805197117
Directory /workspace/6.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_csr_mem_rw_with_rand_reset.2548246980
Short name T303
Test name
Test status
Simulation time 126719763 ps
CPU time 1 seconds
Started Feb 22 12:33:05 PM PST 24
Finished Feb 22 12:33:06 PM PST 24
Peak memory 204304 kb
Host smart-09e29499-06e7-4c32-8cdf-02bd84601c4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548246980 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_csr_mem_rw_with_rand_reset.2548246980
Directory /workspace/7.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_csr_rw.1409719844
Short name T99
Test name
Test status
Simulation time 13093309 ps
CPU time 0.86 seconds
Started Feb 22 12:33:12 PM PST 24
Finished Feb 22 12:33:14 PM PST 24
Peak memory 204264 kb
Host smart-58bb8701-b532-4987-bf4a-79f2118b6952
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409719844 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_csr_rw.1
409719844
Directory /workspace/7.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_intr_test.1478246103
Short name T295
Test name
Test status
Simulation time 39658932 ps
CPU time 0.84 seconds
Started Feb 22 12:33:16 PM PST 24
Finished Feb 22 12:33:22 PM PST 24
Peak memory 204236 kb
Host smart-0f7297e5-9cd8-4ff0-b27f-19c10424b95c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478246103 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_intr_test.1
478246103
Directory /workspace/7.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_same_csr_outstanding.1503815852
Short name T205
Test name
Test status
Simulation time 74059795 ps
CPU time 1.38 seconds
Started Feb 22 12:33:09 PM PST 24
Finished Feb 22 12:33:11 PM PST 24
Peak memory 204412 kb
Host smart-87f6b70a-fe9f-4ea5-9309-18e4a628f96e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503815852 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.k
eymgr_dpe_same_csr_outstanding.1503815852
Directory /workspace/7.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_shadow_reg_errors.2584620879
Short name T73
Test name
Test status
Simulation time 204799251 ps
CPU time 2.21 seconds
Started Feb 22 12:33:22 PM PST 24
Finished Feb 22 12:33:24 PM PST 24
Peak memory 212900 kb
Host smart-e35e5773-e351-4354-a59d-4f282b5fa83a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584620879 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keym
gr_dpe_shadow_reg_errors.2584620879
Directory /workspace/7.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_shadow_reg_errors_with_csr_rw.1405684159
Short name T111
Test name
Test status
Simulation time 453940369 ps
CPU time 7.99 seconds
Started Feb 22 12:33:06 PM PST 24
Finished Feb 22 12:33:15 PM PST 24
Peak memory 212920 kb
Host smart-a1dfa129-1f09-402b-ba51-5eb4d86a3f9c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405684159 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.keymgr_dpe_shadow_reg_errors_with_csr_rw.1405684159
Directory /workspace/7.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_errors.3304563135
Short name T218
Test name
Test status
Simulation time 454708211 ps
CPU time 3.04 seconds
Started Feb 22 12:33:36 PM PST 24
Finished Feb 22 12:33:39 PM PST 24
Peak memory 212720 kb
Host smart-0fd70e17-14ff-490f-9d50-586b4ee774d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304563135 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_tl_errors.3
304563135
Directory /workspace/7.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_intg_err.3300424056
Short name T64
Test name
Test status
Simulation time 50705473 ps
CPU time 2.11 seconds
Started Feb 22 12:33:14 PM PST 24
Finished Feb 22 12:33:16 PM PST 24
Peak memory 212528 kb
Host smart-0bf6ce54-7422-44f3-87c8-23d36acceba5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300424056 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe
_tl_intg_err.3300424056
Directory /workspace/7.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_csr_mem_rw_with_rand_reset.2627905544
Short name T29
Test name
Test status
Simulation time 104495789 ps
CPU time 1.21 seconds
Started Feb 22 12:33:19 PM PST 24
Finished Feb 22 12:33:20 PM PST 24
Peak memory 212648 kb
Host smart-25283ec8-9a57-4cb3-b93c-7b77190d5102
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627905544 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_csr_mem_rw_with_rand_reset.2627905544
Directory /workspace/8.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_csr_rw.1612331737
Short name T202
Test name
Test status
Simulation time 33162909 ps
CPU time 0.98 seconds
Started Feb 22 12:33:47 PM PST 24
Finished Feb 22 12:33:48 PM PST 24
Peak memory 204272 kb
Host smart-b7b8a0ca-f376-4c88-8f88-e091af4852b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612331737 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_csr_rw.1
612331737
Directory /workspace/8.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_intr_test.2856828163
Short name T106
Test name
Test status
Simulation time 22685461 ps
CPU time 0.8 seconds
Started Feb 22 12:33:17 PM PST 24
Finished Feb 22 12:33:18 PM PST 24
Peak memory 204232 kb
Host smart-bfa81f57-333e-4aef-90af-a7362ffa5606
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856828163 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_intr_test.2
856828163
Directory /workspace/8.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_same_csr_outstanding.1210811871
Short name T273
Test name
Test status
Simulation time 156336307 ps
CPU time 1.41 seconds
Started Feb 22 12:33:16 PM PST 24
Finished Feb 22 12:33:17 PM PST 24
Peak memory 204332 kb
Host smart-baeb7b7c-b884-4c6a-a96b-b55f1566fded
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210811871 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.k
eymgr_dpe_same_csr_outstanding.1210811871
Directory /workspace/8.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_shadow_reg_errors.3668226907
Short name T192
Test name
Test status
Simulation time 75420055 ps
CPU time 1.78 seconds
Started Feb 22 12:33:09 PM PST 24
Finished Feb 22 12:33:12 PM PST 24
Peak memory 212908 kb
Host smart-4afb2ef9-5cec-4b3f-890f-7a41af89efc2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668226907 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keym
gr_dpe_shadow_reg_errors.3668226907
Directory /workspace/8.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_shadow_reg_errors_with_csr_rw.930055636
Short name T229
Test name
Test status
Simulation time 507990178 ps
CPU time 2.34 seconds
Started Feb 22 12:33:11 PM PST 24
Finished Feb 22 12:33:14 PM PST 24
Peak memory 212552 kb
Host smart-d442d84a-4ae3-45ce-b9dd-21589a92db02
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930055636 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 8.keymgr_dpe_shadow_reg_errors_with_csr_rw.930055636
Directory /workspace/8.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_tl_errors.2419646574
Short name T290
Test name
Test status
Simulation time 253383179 ps
CPU time 1.81 seconds
Started Feb 22 12:33:11 PM PST 24
Finished Feb 22 12:33:13 PM PST 24
Peak memory 212736 kb
Host smart-ccd9baf3-5975-4a3a-bc3b-776b67ee9ee4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419646574 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_tl_errors.2
419646574
Directory /workspace/8.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_tl_intg_err.1784258777
Short name T58
Test name
Test status
Simulation time 227153935 ps
CPU time 5.98 seconds
Started Feb 22 12:33:13 PM PST 24
Finished Feb 22 12:33:20 PM PST 24
Peak memory 212532 kb
Host smart-02e3e45a-3530-4f65-a4a4-bf7a6cd6dfee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784258777 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe
_tl_intg_err.1784258777
Directory /workspace/8.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_csr_mem_rw_with_rand_reset.1035889175
Short name T280
Test name
Test status
Simulation time 228637489 ps
CPU time 1.88 seconds
Started Feb 22 12:33:20 PM PST 24
Finished Feb 22 12:33:22 PM PST 24
Peak memory 212904 kb
Host smart-c8fce0cc-10e3-409a-ae85-45db4e2c7a11
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035889175 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_csr_mem_rw_with_rand_reset.1035889175
Directory /workspace/9.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_csr_rw.3943381944
Short name T177
Test name
Test status
Simulation time 9995959 ps
CPU time 0.94 seconds
Started Feb 22 12:33:15 PM PST 24
Finished Feb 22 12:33:16 PM PST 24
Peak memory 204284 kb
Host smart-1a92d1ec-cb40-4d73-bc9a-deee08a6a2b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943381944 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_csr_rw.3
943381944
Directory /workspace/9.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_intr_test.3191429134
Short name T127
Test name
Test status
Simulation time 84958000 ps
CPU time 0.8 seconds
Started Feb 22 12:33:32 PM PST 24
Finished Feb 22 12:33:33 PM PST 24
Peak memory 204284 kb
Host smart-71242c5a-6fa1-4412-8051-185234c2e299
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191429134 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_intr_test.3
191429134
Directory /workspace/9.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_same_csr_outstanding.1524903655
Short name T207
Test name
Test status
Simulation time 103758232 ps
CPU time 1.61 seconds
Started Feb 22 12:33:22 PM PST 24
Finished Feb 22 12:33:24 PM PST 24
Peak memory 204452 kb
Host smart-fe40313c-7fc2-4553-910d-c80dd9f51f87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524903655 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.k
eymgr_dpe_same_csr_outstanding.1524903655
Directory /workspace/9.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_shadow_reg_errors.1991547326
Short name T301
Test name
Test status
Simulation time 309314677 ps
CPU time 2.66 seconds
Started Feb 22 12:33:26 PM PST 24
Finished Feb 22 12:33:29 PM PST 24
Peak memory 212820 kb
Host smart-375fe1e1-d7b3-4c37-a29e-75a714fe3ab2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991547326 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keym
gr_dpe_shadow_reg_errors.1991547326
Directory /workspace/9.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_shadow_reg_errors_with_csr_rw.2803483593
Short name T186
Test name
Test status
Simulation time 217612847 ps
CPU time 4.37 seconds
Started Feb 22 12:33:11 PM PST 24
Finished Feb 22 12:33:16 PM PST 24
Peak memory 212948 kb
Host smart-aad10408-0f2f-461d-88b6-ec10f234ff29
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803483593 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.keymgr_dpe_shadow_reg_errors_with_csr_rw.2803483593
Directory /workspace/9.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_tl_errors.4273956343
Short name T62
Test name
Test status
Simulation time 699795771 ps
CPU time 2.89 seconds
Started Feb 22 12:33:30 PM PST 24
Finished Feb 22 12:33:33 PM PST 24
Peak memory 215676 kb
Host smart-ecd93253-ea33-446f-84b5-e9bd25eaa3eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273956343 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_tl_errors.4
273956343
Directory /workspace/9.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_tl_intg_err.1101291702
Short name T63
Test name
Test status
Simulation time 305696987 ps
CPU time 2.68 seconds
Started Feb 22 12:33:30 PM PST 24
Finished Feb 22 12:33:33 PM PST 24
Peak memory 213688 kb
Host smart-f2e9a921-1aa6-4b56-aa48-3ab746ec0b31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101291702 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe
_tl_intg_err.1101291702
Directory /workspace/9.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_dpe_alert_test.2877650192
Short name T156
Test name
Test status
Simulation time 33660341 ps
CPU time 0.71 seconds
Started Feb 22 12:25:52 PM PST 24
Finished Feb 22 12:25:53 PM PST 24
Peak memory 205160 kb
Host smart-bb8e968b-eb4f-48a1-876e-0e90167d1a9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877650192 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_alert_test.2
877650192
Directory /workspace/0.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_dpe_sec_cm.2291404690
Short name T9
Test name
Test status
Simulation time 869459311 ps
CPU time 7.52 seconds
Started Feb 22 12:25:55 PM PST 24
Finished Feb 22 12:26:02 PM PST 24
Peak memory 232676 kb
Host smart-195c7c61-7e2a-43a5-bc5e-9dc350bf9ab8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291404690 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_sec_cm.2291404690
Directory /workspace/0.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_dpe_alert_test.932868083
Short name T155
Test name
Test status
Simulation time 50047401 ps
CPU time 0.88 seconds
Started Feb 22 12:25:55 PM PST 24
Finished Feb 22 12:25:56 PM PST 24
Peak memory 205164 kb
Host smart-f0ec4ecd-198b-4cb6-ad84-21528dfdb2a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932868083 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_alert_test.932868083
Directory /workspace/1.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_dpe_alert_test.4085711341
Short name T17
Test name
Test status
Simulation time 12137790 ps
CPU time 0.84 seconds
Started Feb 22 12:25:49 PM PST 24
Finished Feb 22 12:25:50 PM PST 24
Peak memory 205224 kb
Host smart-b9fd1bb2-3fc7-49d3-93da-e73f994983fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085711341 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_alert_test.
4085711341
Directory /workspace/10.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_dpe_smoke.367209655
Short name T149
Test name
Test status
Simulation time 8356624582 ps
CPU time 31.63 seconds
Started Feb 22 12:25:48 PM PST 24
Finished Feb 22 12:26:19 PM PST 24
Peak memory 208008 kb
Host smart-a657dc45-3b4d-48ab-b7a1-501619c14dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367209655 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_smoke.367209655
Directory /workspace/10.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/11.keymgr_dpe_alert_test.425528582
Short name T130
Test name
Test status
Simulation time 44788867 ps
CPU time 0.73 seconds
Started Feb 22 12:25:40 PM PST 24
Finished Feb 22 12:25:42 PM PST 24
Peak memory 205256 kb
Host smart-4733ce0f-c32a-43a7-bf74-9489ff0c36d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425528582 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_alert_test.425528582
Directory /workspace/11.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_dpe_alert_test.1423733401
Short name T20
Test name
Test status
Simulation time 54603042 ps
CPU time 0.75 seconds
Started Feb 22 12:26:00 PM PST 24
Finished Feb 22 12:26:01 PM PST 24
Peak memory 205224 kb
Host smart-bf1c43dd-ed0c-47cc-aae8-91cfaaa941f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423733401 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_alert_test.
1423733401
Directory /workspace/12.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_dpe_smoke.3647406273
Short name T88
Test name
Test status
Simulation time 1046912301 ps
CPU time 20.35 seconds
Started Feb 22 12:26:05 PM PST 24
Finished Feb 22 12:26:26 PM PST 24
Peak memory 207972 kb
Host smart-2411c4dc-3858-4638-b368-5bb4af5e197a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647406273 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_smoke.3647406273
Directory /workspace/12.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/13.keymgr_dpe_alert_test.3585055853
Short name T91
Test name
Test status
Simulation time 37043290 ps
CPU time 0.75 seconds
Started Feb 22 12:26:07 PM PST 24
Finished Feb 22 12:26:08 PM PST 24
Peak memory 205236 kb
Host smart-b7e3fce9-e979-4887-89e7-f08cc6e3d89b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585055853 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_alert_test.
3585055853
Directory /workspace/13.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_dpe_alert_test.16136680
Short name T141
Test name
Test status
Simulation time 56997439 ps
CPU time 0.88 seconds
Started Feb 22 12:25:44 PM PST 24
Finished Feb 22 12:25:46 PM PST 24
Peak memory 205348 kb
Host smart-fdd27a61-8465-4df7-b89a-9d3d00d11fef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16136680 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_alert_test.16136680
Directory /workspace/14.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_dpe_alert_test.807306239
Short name T167
Test name
Test status
Simulation time 12258452 ps
CPU time 0.83 seconds
Started Feb 22 12:29:22 PM PST 24
Finished Feb 22 12:29:24 PM PST 24
Peak memory 204340 kb
Host smart-136ad0fa-2678-4526-9aa4-85d6a2bbb920
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807306239 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_alert_test.807306239
Directory /workspace/15.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_dpe_smoke.3213087158
Short name T14
Test name
Test status
Simulation time 3252707003 ps
CPU time 16.29 seconds
Started Feb 22 12:25:41 PM PST 24
Finished Feb 22 12:25:58 PM PST 24
Peak memory 207876 kb
Host smart-c424a34d-308f-4064-ab97-c1c215f6292c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213087158 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_smoke.3213087158
Directory /workspace/15.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/16.keymgr_dpe_alert_test.2450369586
Short name T154
Test name
Test status
Simulation time 14319411 ps
CPU time 0.9 seconds
Started Feb 22 12:26:06 PM PST 24
Finished Feb 22 12:26:07 PM PST 24
Peak memory 205160 kb
Host smart-f847d74c-866e-4494-bc5e-0520fb790b33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450369586 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_alert_test.
2450369586
Directory /workspace/16.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_dpe_alert_test.3083781744
Short name T153
Test name
Test status
Simulation time 10783728 ps
CPU time 0.78 seconds
Started Feb 22 12:25:45 PM PST 24
Finished Feb 22 12:25:46 PM PST 24
Peak memory 205152 kb
Host smart-e806474c-36ec-4fb4-91f2-10118098873a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083781744 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_alert_test.
3083781744
Directory /workspace/17.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_dpe_smoke.4486780
Short name T166
Test name
Test status
Simulation time 17063473700 ps
CPU time 132.33 seconds
Started Feb 22 12:25:39 PM PST 24
Finished Feb 22 12:27:52 PM PST 24
Peak memory 207772 kb
Host smart-f44882e6-f349-48a7-a4e8-559846fc6825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4486780 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_smoke.4486780
Directory /workspace/17.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/18.keymgr_dpe_alert_test.754347830
Short name T32
Test name
Test status
Simulation time 11411528 ps
CPU time 0.69 seconds
Started Feb 22 12:29:33 PM PST 24
Finished Feb 22 12:29:34 PM PST 24
Peak memory 205200 kb
Host smart-cb1f511e-8219-4150-8ada-44b0d7dc69db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754347830 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_alert_test.754347830
Directory /workspace/18.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_dpe_smoke.1642588073
Short name T142
Test name
Test status
Simulation time 562696235 ps
CPU time 19.69 seconds
Started Feb 22 12:25:45 PM PST 24
Finished Feb 22 12:26:05 PM PST 24
Peak memory 207148 kb
Host smart-1e71e5d2-9e9e-4648-ab76-0ce44e29e3e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642588073 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_smoke.1642588073
Directory /workspace/18.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/19.keymgr_dpe_alert_test.2989262193
Short name T22
Test name
Test status
Simulation time 45511584 ps
CPU time 0.73 seconds
Started Feb 22 12:25:45 PM PST 24
Finished Feb 22 12:25:46 PM PST 24
Peak memory 205152 kb
Host smart-7b54301e-1eb7-4110-b398-2885c404f59c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989262193 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_alert_test.
2989262193
Directory /workspace/19.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_dpe_alert_test.1597115590
Short name T139
Test name
Test status
Simulation time 19207125 ps
CPU time 0.77 seconds
Started Feb 22 12:25:36 PM PST 24
Finished Feb 22 12:25:37 PM PST 24
Peak memory 205228 kb
Host smart-eb815053-4afc-4de5-8e49-960d7e573796
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597115590 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_alert_test.1
597115590
Directory /workspace/2.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_dpe_sec_cm.402771254
Short name T8
Test name
Test status
Simulation time 5389038290 ps
CPU time 14.06 seconds
Started Feb 22 12:25:46 PM PST 24
Finished Feb 22 12:26:01 PM PST 24
Peak memory 235996 kb
Host smart-df45137b-2727-4eb7-a503-5adfab544f41
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402771254 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_sec_cm.402771254
Directory /workspace/2.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/21.keymgr_dpe_alert_test.2962156716
Short name T131
Test name
Test status
Simulation time 18612919 ps
CPU time 0.75 seconds
Started Feb 22 12:25:47 PM PST 24
Finished Feb 22 12:25:48 PM PST 24
Peak memory 205188 kb
Host smart-0378da03-3c1b-4199-8b4a-84311cc7059e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962156716 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_alert_test.
2962156716
Directory /workspace/21.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_dpe_smoke.3908004013
Short name T157
Test name
Test status
Simulation time 14179334277 ps
CPU time 197.87 seconds
Started Feb 22 12:25:52 PM PST 24
Finished Feb 22 12:29:10 PM PST 24
Peak memory 218272 kb
Host smart-322f6abc-ebbf-444b-a7c5-3e813f172644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908004013 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_smoke.3908004013
Directory /workspace/21.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/22.keymgr_dpe_alert_test.3995759150
Short name T169
Test name
Test status
Simulation time 14168635 ps
CPU time 0.74 seconds
Started Feb 22 12:25:32 PM PST 24
Finished Feb 22 12:25:33 PM PST 24
Peak memory 205176 kb
Host smart-af7c9d62-2da5-417f-9066-7c295ef89024
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995759150 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_alert_test.
3995759150
Directory /workspace/22.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_dpe_alert_test.1613648662
Short name T162
Test name
Test status
Simulation time 87993256 ps
CPU time 0.72 seconds
Started Feb 22 12:25:43 PM PST 24
Finished Feb 22 12:25:45 PM PST 24
Peak memory 205256 kb
Host smart-8604a6b9-40ae-4eb9-af5d-868f34ecd9d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613648662 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_alert_test.
1613648662
Directory /workspace/23.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_dpe_smoke.931644058
Short name T102
Test name
Test status
Simulation time 4410010543 ps
CPU time 37.75 seconds
Started Feb 22 12:25:48 PM PST 24
Finished Feb 22 12:26:26 PM PST 24
Peak memory 216432 kb
Host smart-b1cff7c0-4e05-497d-b92c-2f89258a3ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931644058 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_smoke.931644058
Directory /workspace/23.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/24.keymgr_dpe_alert_test.2791367899
Short name T21
Test name
Test status
Simulation time 21091988 ps
CPU time 0.82 seconds
Started Feb 22 12:25:54 PM PST 24
Finished Feb 22 12:25:55 PM PST 24
Peak memory 205168 kb
Host smart-d548cc58-1c4f-4262-b957-4ab7a61e287e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791367899 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_alert_test.
2791367899
Directory /workspace/24.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_dpe_alert_test.1368888105
Short name T144
Test name
Test status
Simulation time 12848986 ps
CPU time 0.73 seconds
Started Feb 22 12:25:48 PM PST 24
Finished Feb 22 12:25:49 PM PST 24
Peak memory 205184 kb
Host smart-5a2f0701-9589-460e-b4ac-11462c67e581
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368888105 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_alert_test.
1368888105
Directory /workspace/25.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_dpe_alert_test.2916239642
Short name T148
Test name
Test status
Simulation time 12134545 ps
CPU time 0.88 seconds
Started Feb 22 12:25:56 PM PST 24
Finished Feb 22 12:25:57 PM PST 24
Peak memory 205140 kb
Host smart-55258502-fdf7-4290-bd50-f91ea2fc57a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916239642 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_alert_test.
2916239642
Directory /workspace/26.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_dpe_alert_test.717829494
Short name T89
Test name
Test status
Simulation time 39311546 ps
CPU time 0.84 seconds
Started Feb 22 12:25:44 PM PST 24
Finished Feb 22 12:25:46 PM PST 24
Peak memory 205196 kb
Host smart-3022a5d9-d9d5-429d-815f-f103cfbe2e88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717829494 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_alert_test.717829494
Directory /workspace/27.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_dpe_alert_test.2008769678
Short name T24
Test name
Test status
Simulation time 12301214 ps
CPU time 0.77 seconds
Started Feb 22 12:25:44 PM PST 24
Finished Feb 22 12:25:45 PM PST 24
Peak memory 205192 kb
Host smart-32aaf62c-d077-4cea-afab-93942f31e99c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008769678 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_alert_test.
2008769678
Directory /workspace/28.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_dpe_smoke.182376704
Short name T124
Test name
Test status
Simulation time 268560828 ps
CPU time 13.47 seconds
Started Feb 22 12:25:52 PM PST 24
Finished Feb 22 12:26:06 PM PST 24
Peak memory 207588 kb
Host smart-77586928-5c3e-4412-9f78-d5890e082453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182376704 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_smoke.182376704
Directory /workspace/28.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/29.keymgr_dpe_alert_test.2343693293
Short name T151
Test name
Test status
Simulation time 10156468 ps
CPU time 0.71 seconds
Started Feb 22 12:25:49 PM PST 24
Finished Feb 22 12:25:50 PM PST 24
Peak memory 205168 kb
Host smart-e0c7311f-5c8a-4506-a302-3523d085a756
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343693293 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_alert_test.
2343693293
Directory /workspace/29.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_dpe_smoke.637473019
Short name T16
Test name
Test status
Simulation time 2161792009 ps
CPU time 19.6 seconds
Started Feb 22 12:25:47 PM PST 24
Finished Feb 22 12:26:07 PM PST 24
Peak memory 208048 kb
Host smart-ae340c94-74b8-446a-a69d-722819395a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637473019 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_smoke.637473019
Directory /workspace/29.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/3.keymgr_dpe_alert_test.984092311
Short name T94
Test name
Test status
Simulation time 24266884 ps
CPU time 0.89 seconds
Started Feb 22 12:25:44 PM PST 24
Finished Feb 22 12:25:45 PM PST 24
Peak memory 205176 kb
Host smart-943e1711-2237-4552-ba45-c74ffbe7083f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984092311 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_alert_test.984092311
Directory /workspace/3.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_dpe_sec_cm.39491206
Short name T30
Test name
Test status
Simulation time 1117359904 ps
CPU time 17.02 seconds
Started Feb 22 12:25:46 PM PST 24
Finished Feb 22 12:26:04 PM PST 24
Peak memory 231604 kb
Host smart-dcd41fa5-fb2c-4f0c-a09b-d7a81903065f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39491206 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_sec_cm.39491206
Directory /workspace/3.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/30.keymgr_dpe_alert_test.1946602372
Short name T23
Test name
Test status
Simulation time 34884279 ps
CPU time 0.85 seconds
Started Feb 22 12:26:07 PM PST 24
Finished Feb 22 12:26:08 PM PST 24
Peak memory 205244 kb
Host smart-b4a407fc-ec23-4a30-bb5e-ea14abb6affd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946602372 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_alert_test.
1946602372
Directory /workspace/30.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_dpe_smoke.2073594950
Short name T129
Test name
Test status
Simulation time 2685497222 ps
CPU time 23.76 seconds
Started Feb 22 12:26:06 PM PST 24
Finished Feb 22 12:26:30 PM PST 24
Peak memory 207932 kb
Host smart-0b3c5978-2c5d-46d0-b168-68bc5af6daeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073594950 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_smoke.2073594950
Directory /workspace/30.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/31.keymgr_dpe_alert_test.3667020346
Short name T19
Test name
Test status
Simulation time 15347007 ps
CPU time 0.76 seconds
Started Feb 22 12:25:55 PM PST 24
Finished Feb 22 12:25:55 PM PST 24
Peak memory 205216 kb
Host smart-4c39916d-bedf-4c04-a1f5-6eadf57b77ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667020346 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_alert_test.
3667020346
Directory /workspace/31.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_dpe_alert_test.3944171982
Short name T40
Test name
Test status
Simulation time 68969970 ps
CPU time 0.77 seconds
Started Feb 22 12:25:48 PM PST 24
Finished Feb 22 12:25:49 PM PST 24
Peak memory 205124 kb
Host smart-3e4ddbc8-d568-465f-a55e-84165b297b62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944171982 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_alert_test.
3944171982
Directory /workspace/32.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_dpe_smoke.698496005
Short name T117
Test name
Test status
Simulation time 3197187236 ps
CPU time 18.5 seconds
Started Feb 22 12:25:49 PM PST 24
Finished Feb 22 12:26:08 PM PST 24
Peak memory 207824 kb
Host smart-4a2a0b9e-0f29-46fd-851b-d296aeacf23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698496005 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_smoke.698496005
Directory /workspace/32.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/33.keymgr_dpe_alert_test.1406235727
Short name T159
Test name
Test status
Simulation time 11504240 ps
CPU time 0.87 seconds
Started Feb 22 12:25:55 PM PST 24
Finished Feb 22 12:25:56 PM PST 24
Peak memory 205140 kb
Host smart-0704f3ea-5f02-48ab-b5d1-24e9ebc33891
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406235727 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_alert_test.
1406235727
Directory /workspace/33.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_dpe_smoke.1513756979
Short name T122
Test name
Test status
Simulation time 1830641370 ps
CPU time 17.82 seconds
Started Feb 22 12:26:05 PM PST 24
Finished Feb 22 12:26:24 PM PST 24
Peak memory 207912 kb
Host smart-5afb10b0-0122-4bb2-9ea5-0886d0e05c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513756979 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_smoke.1513756979
Directory /workspace/33.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/34.keymgr_dpe_alert_test.2834342685
Short name T168
Test name
Test status
Simulation time 11783008 ps
CPU time 0.86 seconds
Started Feb 22 12:25:54 PM PST 24
Finished Feb 22 12:25:55 PM PST 24
Peak memory 205200 kb
Host smart-437dca3f-3d48-4656-b79f-322c21d7fbf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834342685 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_alert_test.
2834342685
Directory /workspace/34.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_dpe_smoke.2137988236
Short name T161
Test name
Test status
Simulation time 846069406 ps
CPU time 12.27 seconds
Started Feb 22 12:25:55 PM PST 24
Finished Feb 22 12:26:07 PM PST 24
Peak memory 207800 kb
Host smart-512d2ac7-e4d0-4485-9d01-eb6298f95164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137988236 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_smoke.2137988236
Directory /workspace/34.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/35.keymgr_dpe_alert_test.3141706212
Short name T18
Test name
Test status
Simulation time 38207549 ps
CPU time 0.73 seconds
Started Feb 22 12:25:59 PM PST 24
Finished Feb 22 12:26:00 PM PST 24
Peak memory 205032 kb
Host smart-f0851a3c-b84b-42ea-91ec-469ff9a6b2a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141706212 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_alert_test.
3141706212
Directory /workspace/35.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_dpe_smoke.2424973334
Short name T158
Test name
Test status
Simulation time 1007313869 ps
CPU time 13.73 seconds
Started Feb 22 12:25:59 PM PST 24
Finished Feb 22 12:26:13 PM PST 24
Peak memory 205920 kb
Host smart-6ede3c26-1388-40b7-9b7c-69e837db2eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424973334 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_smoke.2424973334
Directory /workspace/35.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/36.keymgr_dpe_alert_test.4223572071
Short name T38
Test name
Test status
Simulation time 12920200 ps
CPU time 0.86 seconds
Started Feb 22 12:26:08 PM PST 24
Finished Feb 22 12:26:09 PM PST 24
Peak memory 205156 kb
Host smart-c75c2c7c-f446-445a-9f25-21888abb2247
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223572071 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_alert_test.
4223572071
Directory /workspace/36.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_dpe_smoke.3460401790
Short name T150
Test name
Test status
Simulation time 613362244 ps
CPU time 19.32 seconds
Started Feb 22 12:25:59 PM PST 24
Finished Feb 22 12:26:18 PM PST 24
Peak memory 207160 kb
Host smart-20724684-2082-4bfc-8f99-0934e8294274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460401790 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_smoke.3460401790
Directory /workspace/36.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/37.keymgr_dpe_alert_test.4210638659
Short name T136
Test name
Test status
Simulation time 68900601 ps
CPU time 0.89 seconds
Started Feb 22 12:25:51 PM PST 24
Finished Feb 22 12:25:52 PM PST 24
Peak memory 205304 kb
Host smart-b515c770-0362-4e69-8f7c-8ce86c30ebf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210638659 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_alert_test.
4210638659
Directory /workspace/37.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_dpe_smoke.2781580061
Short name T115
Test name
Test status
Simulation time 457103078 ps
CPU time 16.86 seconds
Started Feb 22 12:25:59 PM PST 24
Finished Feb 22 12:26:16 PM PST 24
Peak memory 206084 kb
Host smart-8ae8bdc5-1160-4900-bb4a-9f7c483157bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781580061 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_smoke.2781580061
Directory /workspace/37.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/38.keymgr_dpe_alert_test.1333073299
Short name T137
Test name
Test status
Simulation time 20271775 ps
CPU time 0.86 seconds
Started Feb 22 12:25:59 PM PST 24
Finished Feb 22 12:26:00 PM PST 24
Peak memory 205244 kb
Host smart-75a0ce0e-d28d-497d-b5e1-cdf5e1d1f263
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333073299 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_alert_test.
1333073299
Directory /workspace/38.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_dpe_alert_test.1347222701
Short name T25
Test name
Test status
Simulation time 60393016 ps
CPU time 0.77 seconds
Started Feb 22 12:25:48 PM PST 24
Finished Feb 22 12:25:49 PM PST 24
Peak memory 205140 kb
Host smart-15e436ca-0ba7-4f7a-bed0-026939ea74e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347222701 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_alert_test.
1347222701
Directory /workspace/39.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_dpe_smoke.2405151430
Short name T152
Test name
Test status
Simulation time 2432609173 ps
CPU time 23.86 seconds
Started Feb 22 12:26:06 PM PST 24
Finished Feb 22 12:26:31 PM PST 24
Peak memory 207904 kb
Host smart-3ebeee4c-fff1-4bd2-9360-3347e1ff93bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405151430 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_smoke.2405151430
Directory /workspace/39.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/4.keymgr_dpe_alert_test.910801056
Short name T37
Test name
Test status
Simulation time 26003682 ps
CPU time 0.71 seconds
Started Feb 22 12:25:45 PM PST 24
Finished Feb 22 12:25:46 PM PST 24
Peak memory 205200 kb
Host smart-6788c62d-ce2b-41a7-b7e1-6c0038a8432e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910801056 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_alert_test.910801056
Directory /workspace/4.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_dpe_smoke.1520053541
Short name T11
Test name
Test status
Simulation time 1955151836 ps
CPU time 17.18 seconds
Started Feb 22 12:25:47 PM PST 24
Finished Feb 22 12:26:04 PM PST 24
Peak memory 207048 kb
Host smart-0a720c1d-d033-4315-bb77-5e7e2384a884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520053541 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_smoke.1520053541
Directory /workspace/4.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/40.keymgr_dpe_alert_test.1439105268
Short name T145
Test name
Test status
Simulation time 24502007 ps
CPU time 0.75 seconds
Started Feb 22 12:25:57 PM PST 24
Finished Feb 22 12:25:58 PM PST 24
Peak memory 205244 kb
Host smart-852faa8d-32b4-477f-8607-a32343f2d97e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439105268 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_alert_test.
1439105268
Directory /workspace/40.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_dpe_smoke.2577413519
Short name T5
Test name
Test status
Simulation time 5809397104 ps
CPU time 16.72 seconds
Started Feb 22 12:25:39 PM PST 24
Finished Feb 22 12:25:57 PM PST 24
Peak memory 207916 kb
Host smart-d056b7a2-182e-44ae-91bd-b7d4aea6e030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577413519 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_smoke.2577413519
Directory /workspace/40.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/41.keymgr_dpe_alert_test.3794222938
Short name T33
Test name
Test status
Simulation time 97407755 ps
CPU time 0.76 seconds
Started Feb 22 12:25:52 PM PST 24
Finished Feb 22 12:25:53 PM PST 24
Peak memory 205148 kb
Host smart-2e652b28-93c6-48e0-ab89-0832909d80e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794222938 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_alert_test.
3794222938
Directory /workspace/41.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_dpe_smoke.4008996946
Short name T163
Test name
Test status
Simulation time 19100223648 ps
CPU time 97.04 seconds
Started Feb 22 12:26:23 PM PST 24
Finished Feb 22 12:28:00 PM PST 24
Peak memory 207892 kb
Host smart-51e8b654-a451-4375-a412-0996f1d2758e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008996946 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_smoke.4008996946
Directory /workspace/41.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/42.keymgr_dpe_alert_test.2958465410
Short name T147
Test name
Test status
Simulation time 11301533 ps
CPU time 0.84 seconds
Started Feb 22 12:25:42 PM PST 24
Finished Feb 22 12:25:43 PM PST 24
Peak memory 205096 kb
Host smart-f2d06dc4-eee1-4414-a2d8-11f180f4bd11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958465410 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_alert_test.
2958465410
Directory /workspace/42.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_dpe_smoke.62918964
Short name T103
Test name
Test status
Simulation time 154388639 ps
CPU time 10.16 seconds
Started Feb 22 12:25:52 PM PST 24
Finished Feb 22 12:26:03 PM PST 24
Peak memory 206012 kb
Host smart-e86e090a-5724-4c5a-95e5-dbe50011dafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62918964 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_smoke.62918964
Directory /workspace/42.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/43.keymgr_dpe_alert_test.1206651229
Short name T133
Test name
Test status
Simulation time 22264291 ps
CPU time 0.95 seconds
Started Feb 22 12:25:52 PM PST 24
Finished Feb 22 12:25:53 PM PST 24
Peak memory 205096 kb
Host smart-c414e949-1663-486a-b583-7866710899a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206651229 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_alert_test.
1206651229
Directory /workspace/43.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_dpe_smoke.1147008387
Short name T35
Test name
Test status
Simulation time 591477966 ps
CPU time 19.7 seconds
Started Feb 22 12:25:52 PM PST 24
Finished Feb 22 12:26:12 PM PST 24
Peak memory 208012 kb
Host smart-bcdea281-9211-4441-ab28-3d2b4a80c2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147008387 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_smoke.1147008387
Directory /workspace/43.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/44.keymgr_dpe_alert_test.4134575592
Short name T143
Test name
Test status
Simulation time 14376569 ps
CPU time 0.75 seconds
Started Feb 22 12:25:54 PM PST 24
Finished Feb 22 12:25:55 PM PST 24
Peak memory 205168 kb
Host smart-e93da03e-fcf7-4cfe-ac00-e47523f49f59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134575592 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_alert_test.
4134575592
Directory /workspace/44.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_dpe_smoke.3291908707
Short name T123
Test name
Test status
Simulation time 656305162 ps
CPU time 19.14 seconds
Started Feb 22 12:25:45 PM PST 24
Finished Feb 22 12:26:05 PM PST 24
Peak memory 207860 kb
Host smart-f7837f0d-cb26-4b7e-84bd-86741727626a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291908707 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_smoke.3291908707
Directory /workspace/44.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/45.keymgr_dpe_alert_test.1340171497
Short name T26
Test name
Test status
Simulation time 13180665 ps
CPU time 0.71 seconds
Started Feb 22 12:25:51 PM PST 24
Finished Feb 22 12:25:52 PM PST 24
Peak memory 205128 kb
Host smart-df73b435-a696-434c-9a4a-09f6ab8df17e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340171497 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_alert_test.
1340171497
Directory /workspace/45.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_dpe_alert_test.3410030546
Short name T165
Test name
Test status
Simulation time 38517079 ps
CPU time 0.82 seconds
Started Feb 22 12:25:52 PM PST 24
Finished Feb 22 12:25:53 PM PST 24
Peak memory 205172 kb
Host smart-bc9c674d-a920-4020-81e5-d5c2ac6c3d90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410030546 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_alert_test.
3410030546
Directory /workspace/46.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_dpe_alert_test.1238747729
Short name T1
Test name
Test status
Simulation time 10214636 ps
CPU time 0.73 seconds
Started Feb 22 12:25:45 PM PST 24
Finished Feb 22 12:25:46 PM PST 24
Peak memory 205256 kb
Host smart-fb4f0956-fc4c-4372-b40a-8610c47b6861
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238747729 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_alert_test.
1238747729
Directory /workspace/47.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_dpe_smoke.3971653883
Short name T140
Test name
Test status
Simulation time 1668309366 ps
CPU time 19.03 seconds
Started Feb 22 12:25:48 PM PST 24
Finished Feb 22 12:26:07 PM PST 24
Peak memory 207040 kb
Host smart-7a8d72b2-bb3e-4b60-a4b2-e8b8524977e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971653883 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_smoke.3971653883
Directory /workspace/47.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/48.keymgr_dpe_alert_test.318486861
Short name T101
Test name
Test status
Simulation time 14334176 ps
CPU time 0.89 seconds
Started Feb 22 12:25:47 PM PST 24
Finished Feb 22 12:25:48 PM PST 24
Peak memory 205288 kb
Host smart-9dc93b79-f4af-40e3-8514-64a0e7d36609
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318486861 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_alert_test.318486861
Directory /workspace/48.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_dpe_smoke.3639163205
Short name T15
Test name
Test status
Simulation time 19225070277 ps
CPU time 77.14 seconds
Started Feb 22 12:25:42 PM PST 24
Finished Feb 22 12:27:00 PM PST 24
Peak memory 207380 kb
Host smart-41aea67f-58ec-4883-a548-132c6401eb86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639163205 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_smoke.3639163205
Directory /workspace/48.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/49.keymgr_dpe_alert_test.394481622
Short name T3
Test name
Test status
Simulation time 50184460 ps
CPU time 0.76 seconds
Started Feb 22 12:25:52 PM PST 24
Finished Feb 22 12:25:53 PM PST 24
Peak memory 205128 kb
Host smart-8d70f6ff-5528-46ef-a5ba-2ae665bbc338
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394481622 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_alert_test.394481622
Directory /workspace/49.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_dpe_smoke.2525038001
Short name T90
Test name
Test status
Simulation time 2820343493 ps
CPU time 22.92 seconds
Started Feb 22 12:25:48 PM PST 24
Finished Feb 22 12:26:11 PM PST 24
Peak memory 208016 kb
Host smart-481fbc92-22e9-4b75-bc17-a51ad4116ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525038001 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_smoke.2525038001
Directory /workspace/49.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/5.keymgr_dpe_alert_test.733485844
Short name T138
Test name
Test status
Simulation time 17002506 ps
CPU time 0.89 seconds
Started Feb 22 12:25:52 PM PST 24
Finished Feb 22 12:25:53 PM PST 24
Peak memory 205336 kb
Host smart-c85e1e12-e05c-4d6b-b137-211e37eb6023
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733485844 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_alert_test.733485844
Directory /workspace/5.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_dpe_smoke.4179428257
Short name T10
Test name
Test status
Simulation time 154069345 ps
CPU time 9.73 seconds
Started Feb 22 12:25:48 PM PST 24
Finished Feb 22 12:25:58 PM PST 24
Peak memory 206320 kb
Host smart-e44fed57-cb63-4d0f-a80b-bca47c46bb50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179428257 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_smoke.4179428257
Directory /workspace/5.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/6.keymgr_dpe_alert_test.636602420
Short name T128
Test name
Test status
Simulation time 34722425 ps
CPU time 0.78 seconds
Started Feb 22 12:25:48 PM PST 24
Finished Feb 22 12:25:49 PM PST 24
Peak memory 205192 kb
Host smart-279ef439-dea3-47ff-90ed-471ff293669a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636602420 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_alert_test.636602420
Directory /workspace/6.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_dpe_smoke.3497806614
Short name T85
Test name
Test status
Simulation time 3590323206 ps
CPU time 21.06 seconds
Started Feb 22 12:25:54 PM PST 24
Finished Feb 22 12:26:15 PM PST 24
Peak memory 206128 kb
Host smart-76f37472-cf5f-4327-b467-08d76d332567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497806614 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_smoke.3497806614
Directory /workspace/6.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/7.keymgr_dpe_alert_test.2728745381
Short name T132
Test name
Test status
Simulation time 14160887 ps
CPU time 0.98 seconds
Started Feb 22 12:25:54 PM PST 24
Finished Feb 22 12:25:56 PM PST 24
Peak memory 205372 kb
Host smart-248ecbba-e24a-460e-a95e-01e90cf1031d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728745381 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_alert_test.2
728745381
Directory /workspace/7.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_dpe_smoke.342306361
Short name T121
Test name
Test status
Simulation time 4531675262 ps
CPU time 65 seconds
Started Feb 22 12:25:48 PM PST 24
Finished Feb 22 12:26:53 PM PST 24
Peak memory 221828 kb
Host smart-5143b8e8-6181-4bb9-b662-2ef3578d5a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342306361 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_smoke.342306361
Directory /workspace/7.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/8.keymgr_dpe_alert_test.3690579951
Short name T134
Test name
Test status
Simulation time 48403729 ps
CPU time 0.69 seconds
Started Feb 22 12:25:47 PM PST 24
Finished Feb 22 12:25:48 PM PST 24
Peak memory 205156 kb
Host smart-42b181bf-4944-49df-8b86-d11b03cdbae0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690579951 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_alert_test.3
690579951
Directory /workspace/8.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_dpe_smoke.1140435560
Short name T146
Test name
Test status
Simulation time 199059188 ps
CPU time 10.4 seconds
Started Feb 22 12:25:55 PM PST 24
Finished Feb 22 12:26:05 PM PST 24
Peak memory 206036 kb
Host smart-9b34b90a-06c5-4be7-9145-673da56ee5e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140435560 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_smoke.1140435560
Directory /workspace/8.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/9.keymgr_dpe_alert_test.4097363666
Short name T135
Test name
Test status
Simulation time 12017514 ps
CPU time 0.72 seconds
Started Feb 22 12:25:40 PM PST 24
Finished Feb 22 12:25:42 PM PST 24
Peak memory 205180 kb
Host smart-31663b65-102b-45ed-8dfd-1bd9735dcdac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097363666 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_alert_test.4
097363666
Directory /workspace/9.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_dpe_smoke.1855912770
Short name T164
Test name
Test status
Simulation time 3920966002 ps
CPU time 27.04 seconds
Started Feb 22 12:26:05 PM PST 24
Finished Feb 22 12:26:32 PM PST 24
Peak memory 207316 kb
Host smart-689f49f8-af71-4d2b-8c1b-4d9ffe32cd98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855912770 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_smoke.1855912770
Directory /workspace/9.keymgr_dpe_smoke/latest
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