Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	911106	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

245386

1

T1

2

T3

5

T4

3233

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1013420	1			T1	1		T2	1		T3	1
values[0x0]	70919	1			T1	4		T2	5		T3	7
values[0x1]	72153	1			T1	3		T2	3		T3	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	622658	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

533834

1

T1

2

T2

1

T3

8

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3596	1			T4	29		T11	13		T12	38
valid_sources[0x01]	3601	1			T4	36		T11	25		T12	37
valid_sources[0x02]	3409	1			T3	1		T4	31		T12	36
valid_sources[0x03]	3494	1			T4	29		T11	20		T12	29
valid_sources[0x04]	3709	1			T4	38		T11	61		T12	26
valid_sources[0x05]	3763	1			T3	1		T4	23		T12	37
valid_sources[0x06]	23668	1			T4	16		T6	20098		T11	18
valid_sources[0x07]	3576	1			T4	37		T12	35		T16	36
valid_sources[0x08]	3718	1			T4	26		T11	5		T12	35
valid_sources[0x09]	3546	1			T4	34		T12	45		T16	19
valid_sources[0x0a]	15905	1			T4	34		T6	12273		T11	13
valid_sources[0x0b]	3636	1			T4	37		T11	34		T12	32
valid_sources[0x0c]	3763	1			T4	32		T11	64		T12	47
valid_sources[0x0d]	3760	1			T4	31		T11	90		T12	35
valid_sources[0x0e]	5278	1			T1	1		T4	36		T6	1737
valid_sources[0x0f]	3504	1			T4	50		T11	31		T12	34
valid_sources[0x10]	3452	1			T4	27		T11	1		T12	37
valid_sources[0x11]	4007	1			T4	32		T11	55		T12	37
valid_sources[0x12]	3557	1			T4	51		T12	38		T16	37
valid_sources[0x13]	3882	1			T4	44		T11	49		T12	35
valid_sources[0x14]	3813	1			T4	50		T11	34		T12	33
valid_sources[0x15]	3791	1			T4	65		T12	26		T16	39
valid_sources[0x16]	3637	1			T4	33		T12	39		T16	37
valid_sources[0x17]	3391	1			T4	31		T11	20		T12	38
valid_sources[0x18]	3435	1			T4	33		T11	59		T12	36
valid_sources[0x19]	3457	1			T4	16		T11	13		T12	29
valid_sources[0x1a]	3439	1			T4	38		T11	8		T12	22
valid_sources[0x1b]	12675	1			T4	30		T11	13		T12	37
valid_sources[0x1c]	3575	1			T4	47		T11	98		T12	31
valid_sources[0x1d]	3845	1			T4	37		T11	49		T12	37
valid_sources[0x1e]	3741	1			T4	49		T11	21		T12	40
valid_sources[0x1f]	3713	1			T4	32		T11	62		T12	25
valid_sources[0x20]	3435	1			T3	1		T4	41		T11	13
valid_sources[0x21]	3798	1			T4	37		T11	9		T12	33
valid_sources[0x22]	3319	1			T4	16		T12	25		T16	28
valid_sources[0x23]	3521	1			T4	44		T11	16		T12	25
valid_sources[0x24]	3490	1			T4	40		T11	59		T12	38
valid_sources[0x25]	3493	1			T4	39		T11	40		T12	37
valid_sources[0x26]	3473	1			T4	23		T11	52		T12	42
valid_sources[0x27]	3688	1			T4	38		T11	11		T12	39
valid_sources[0x28]	3563	1			T4	16		T11	3		T12	37
valid_sources[0x29]	3761	1			T4	24		T11	40		T12	28
valid_sources[0x2a]	3482	1			T4	44		T11	20		T12	37
valid_sources[0x2b]	3583	1			T1	3		T4	33		T12	35
valid_sources[0x2c]	3832	1			T4	18		T11	28		T12	39
valid_sources[0x2d]	3749	1			T4	46		T11	1		T12	34
valid_sources[0x2e]	3740	1			T4	30		T11	35		T12	38
valid_sources[0x2f]	3776	1			T4	23		T11	33		T12	37
valid_sources[0x30]	3424	1			T4	28		T11	8		T12	32
valid_sources[0x31]	3969	1			T4	33		T11	18		T12	30
valid_sources[0x32]	3631	1			T4	29		T12	43		T16	29
valid_sources[0x33]	3963	1			T4	39		T11	49		T12	46
valid_sources[0x34]	3475	1			T4	29		T11	12		T12	35
valid_sources[0x35]	3468	1			T4	45		T11	22		T12	22
valid_sources[0x36]	3594	1			T4	41		T11	49		T12	28
valid_sources[0x37]	3724	1			T4	27		T11	37		T12	42
valid_sources[0x38]	3584	1			T4	42		T11	34		T12	45
valid_sources[0x39]	3472	1			T4	35		T11	4		T12	40
valid_sources[0x3a]	14631	1			T4	28		T11	9		T12	38
valid_sources[0x3b]	3436	1			T4	49		T11	1		T12	41
valid_sources[0x3c]	4042	1			T4	37		T11	41		T12	41
valid_sources[0x3d]	3418	1			T4	36		T11	36		T12	29
valid_sources[0x3e]	3374	1			T4	34		T11	59		T12	41
valid_sources[0x3f]	3306	1			T4	11		T11	23		T12	40
valid_sources[0x40]	3868	1			T4	51		T11	22		T12	43
valid_sources[0x41]	3743	1			T4	57		T11	25		T12	38
valid_sources[0x42]	3556	1			T4	60		T12	53		T121	1
valid_sources[0x43]	3410	1			T4	19		T11	37		T12	38
valid_sources[0x44]	3633	1			T4	37		T11	11		T12	36
valid_sources[0x45]	4119	1			T4	35		T11	1		T12	32
valid_sources[0x46]	3491	1			T4	14		T11	10		T12	35
valid_sources[0x47]	3634	1			T4	40		T11	68		T12	35
valid_sources[0x48]	3390	1			T4	37		T11	7		T12	31
valid_sources[0x49]	3572	1			T4	34		T11	9		T12	32
valid_sources[0x4a]	3423	1			T4	35		T11	21		T12	53
valid_sources[0x4b]	4020	1			T4	45		T11	3		T12	24
valid_sources[0x4c]	3546	1			T4	39		T12	40		T16	33
valid_sources[0x4d]	3470	1			T3	1		T4	23		T11	27
valid_sources[0x4e]	3891	1			T4	35		T11	40		T12	36
valid_sources[0x4f]	3650	1			T4	25		T11	8		T12	25
valid_sources[0x50]	3715	1			T4	28		T12	35		T16	29
valid_sources[0x51]	3488	1			T4	39		T11	38		T12	32
valid_sources[0x52]	3747	1			T4	31		T12	47		T16	34
valid_sources[0x53]	3788	1			T4	33		T11	36		T12	23
valid_sources[0x54]	3572	1			T4	27		T11	38		T12	32
valid_sources[0x55]	3395	1			T4	40		T11	2		T12	34
valid_sources[0x56]	3919	1			T4	25		T11	44		T12	37
valid_sources[0x57]	3686	1			T4	31		T11	18		T12	35
valid_sources[0x58]	3256	1			T4	33		T12	38		T122	1
valid_sources[0x59]	3426	1			T4	36		T12	36		T124	1
valid_sources[0x5a]	6010	1			T4	41		T11	16		T12	28
valid_sources[0x5b]	5393	1			T4	25		T12	38		T16	41
valid_sources[0x5c]	3511	1			T4	66		T11	20		T12	30
valid_sources[0x5d]	5523	1			T4	28		T11	24		T12	21
valid_sources[0x5e]	3428	1			T4	34		T11	11		T12	39
valid_sources[0x5f]	3502	1			T4	25		T11	82		T12	35
valid_sources[0x60]	3478	1			T4	32		T12	40		T16	35
valid_sources[0x61]	4104	1			T4	45		T11	12		T12	38
valid_sources[0x62]	4408	1			T4	21		T11	2		T12	51
valid_sources[0x63]	3598	1			T4	55		T12	28		T20	1
valid_sources[0x64]	3497	1			T4	29		T11	12		T12	41
valid_sources[0x65]	4002	1			T4	33		T12	37		T16	32
valid_sources[0x66]	3573	1			T4	9		T11	8		T12	34
valid_sources[0x67]	3629	1			T4	45		T11	25		T12	39
valid_sources[0x68]	3890	1			T4	34		T11	22		T12	36
valid_sources[0x69]	3407	1			T4	41		T11	25		T12	46
valid_sources[0x6a]	3444	1			T4	41		T11	11		T12	36
valid_sources[0x6b]	3606	1			T4	27		T12	39		T16	41
valid_sources[0x6c]	12879	1			T4	34		T11	6		T12	43
valid_sources[0x6d]	3434	1			T4	30		T11	4		T12	31
valid_sources[0x6e]	4247	1			T4	35		T11	32		T12	40
valid_sources[0x6f]	3548	1			T4	40		T11	31		T12	23
valid_sources[0x70]	3739	1			T4	47		T12	33		T14	277
valid_sources[0x71]	3407	1			T4	29		T11	90		T12	33
valid_sources[0x72]	3633	1			T4	35		T11	26		T12	33
valid_sources[0x73]	7156	1			T4	26		T11	25		T12	23
valid_sources[0x74]	4051	1			T4	28		T10	235		T11	1
valid_sources[0x75]	3480	1			T4	56		T11	38		T12	43
valid_sources[0x76]	3852	1			T4	42		T11	62		T12	47
valid_sources[0x77]	3922	1			T4	49		T11	40		T12	46
valid_sources[0x78]	7689	1			T4	21		T11	6		T12	29
valid_sources[0x79]	16828	1			T4	36		T11	35		T12	39
valid_sources[0x7a]	3522	1			T4	33		T11	16		T12	38
valid_sources[0x7b]	3769	1			T4	32		T11	16		T12	46
valid_sources[0x7c]	3866	1			T4	41		T11	4		T12	22
valid_sources[0x7d]	3443	1			T4	13		T11	6		T12	42
valid_sources[0x7e]	8063	1			T3	3		T4	27		T11	30
valid_sources[0x7f]	3490	1			T4	38		T11	5		T12	41
valid_sources[0x80]	3437	1			T4	53		T11	16		T12	46

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

135588

1

T1

1

T4

2155

T5

1922

values[0x0]

all_enables

biggest_size

58338

1

T1

1

T3

2

T4

616

values[0x1]

all_enables

biggest_size

51460

1

T3

3

T4

462

T5

411