Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
76.25 97.70 90.49 57.52 76.92 94.94 98.34 17.82


Total test records in report: 308
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html
T256 /workspace/coverage/cover_reg_top/19.keymgr_dpe_tl_errors.3452996432 Mar 02 01:20:29 PM PST 24 Mar 02 01:20:32 PM PST 24 989025366 ps
T257 /workspace/coverage/cover_reg_top/1.keymgr_dpe_shadow_reg_errors_with_csr_rw.1126946730 Mar 02 01:19:50 PM PST 24 Mar 02 01:19:55 PM PST 24 676551026 ps
T258 /workspace/coverage/cover_reg_top/10.keymgr_dpe_shadow_reg_errors.668352278 Mar 02 01:20:08 PM PST 24 Mar 02 01:20:12 PM PST 24 232171650 ps
T259 /workspace/coverage/cover_reg_top/30.keymgr_dpe_intr_test.959367619 Mar 02 01:20:48 PM PST 24 Mar 02 01:20:49 PM PST 24 53998278 ps
T260 /workspace/coverage/cover_reg_top/8.keymgr_dpe_tl_errors.136754554 Mar 02 01:20:06 PM PST 24 Mar 02 01:20:08 PM PST 24 117908050 ps
T261 /workspace/coverage/cover_reg_top/18.keymgr_dpe_csr_rw.2646909180 Mar 02 01:20:30 PM PST 24 Mar 02 01:20:31 PM PST 24 12034546 ps
T262 /workspace/coverage/cover_reg_top/7.keymgr_dpe_same_csr_outstanding.1962022136 Mar 02 01:20:08 PM PST 24 Mar 02 01:20:10 PM PST 24 19656032 ps
T263 /workspace/coverage/cover_reg_top/6.keymgr_dpe_same_csr_outstanding.9888274 Mar 02 01:20:05 PM PST 24 Mar 02 01:20:07 PM PST 24 30626348 ps
T264 /workspace/coverage/cover_reg_top/9.keymgr_dpe_shadow_reg_errors.4026275049 Mar 02 01:20:09 PM PST 24 Mar 02 01:20:12 PM PST 24 138144777 ps
T265 /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors_with_csr_rw.3422653680 Mar 02 01:20:17 PM PST 24 Mar 02 01:20:21 PM PST 24 153821342 ps
T266 /workspace/coverage/cover_reg_top/49.keymgr_dpe_intr_test.2478315237 Mar 02 01:20:43 PM PST 24 Mar 02 01:20:44 PM PST 24 39089403 ps
T267 /workspace/coverage/cover_reg_top/6.keymgr_dpe_shadow_reg_errors.1592384307 Mar 02 01:19:58 PM PST 24 Mar 02 01:20:03 PM PST 24 72690183 ps
T268 /workspace/coverage/cover_reg_top/16.keymgr_dpe_csr_rw.3302043355 Mar 02 01:20:30 PM PST 24 Mar 02 01:20:31 PM PST 24 9973976 ps
T269 /workspace/coverage/cover_reg_top/5.keymgr_dpe_shadow_reg_errors.625940790 Mar 02 01:20:03 PM PST 24 Mar 02 01:20:05 PM PST 24 362799260 ps
T270 /workspace/coverage/cover_reg_top/2.keymgr_dpe_shadow_reg_errors.279207669 Mar 02 01:19:53 PM PST 24 Mar 02 01:19:57 PM PST 24 67322115 ps
T271 /workspace/coverage/cover_reg_top/2.keymgr_dpe_tl_errors.2672576531 Mar 02 01:19:56 PM PST 24 Mar 02 01:19:59 PM PST 24 28820394 ps
T272 /workspace/coverage/cover_reg_top/11.keymgr_dpe_intr_test.132197608 Mar 02 01:20:16 PM PST 24 Mar 02 01:20:17 PM PST 24 21971415 ps
T273 /workspace/coverage/cover_reg_top/4.keymgr_dpe_same_csr_outstanding.1107687465 Mar 02 01:19:58 PM PST 24 Mar 02 01:20:04 PM PST 24 443361092 ps
T274 /workspace/coverage/cover_reg_top/15.keymgr_dpe_csr_rw.1166814455 Mar 02 01:20:26 PM PST 24 Mar 02 01:20:27 PM PST 24 17518322 ps
T275 /workspace/coverage/cover_reg_top/5.keymgr_dpe_csr_rw.776902990 Mar 02 01:20:04 PM PST 24 Mar 02 01:20:05 PM PST 24 12363519 ps
T276 /workspace/coverage/cover_reg_top/20.keymgr_dpe_intr_test.3887127235 Mar 02 01:20:30 PM PST 24 Mar 02 01:20:30 PM PST 24 9059361 ps
T277 /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_hw_reset.2097452006 Mar 02 01:19:49 PM PST 24 Mar 02 01:19:51 PM PST 24 50906433 ps
T278 /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_aliasing.4029429165 Mar 02 01:19:59 PM PST 24 Mar 02 01:20:05 PM PST 24 178290290 ps
T279 /workspace/coverage/cover_reg_top/21.keymgr_dpe_intr_test.2184249080 Mar 02 01:20:39 PM PST 24 Mar 02 01:20:40 PM PST 24 18406377 ps
T280 /workspace/coverage/cover_reg_top/11.keymgr_dpe_shadow_reg_errors_with_csr_rw.108914865 Mar 02 01:20:10 PM PST 24 Mar 02 01:20:14 PM PST 24 509690537 ps
T54 /workspace/coverage/cover_reg_top/1.keymgr_dpe_tl_intg_err.104106339 Mar 02 01:19:50 PM PST 24 Mar 02 01:19:53 PM PST 24 349721934 ps
T281 /workspace/coverage/cover_reg_top/42.keymgr_dpe_intr_test.2001038637 Mar 02 01:20:46 PM PST 24 Mar 02 01:20:47 PM PST 24 13852799 ps
T282 /workspace/coverage/cover_reg_top/39.keymgr_dpe_intr_test.2965388957 Mar 02 01:20:41 PM PST 24 Mar 02 01:20:42 PM PST 24 40233770 ps
T46 /workspace/coverage/cover_reg_top/9.keymgr_dpe_tl_intg_err.1628809531 Mar 02 01:20:08 PM PST 24 Mar 02 01:20:12 PM PST 24 394460398 ps
T283 /workspace/coverage/cover_reg_top/10.keymgr_dpe_shadow_reg_errors_with_csr_rw.4066215873 Mar 02 01:20:06 PM PST 24 Mar 02 01:20:11 PM PST 24 215887615 ps
T284 /workspace/coverage/cover_reg_top/24.keymgr_dpe_intr_test.3095711245 Mar 02 01:20:46 PM PST 24 Mar 02 01:20:47 PM PST 24 8742684 ps
T285 /workspace/coverage/cover_reg_top/48.keymgr_dpe_intr_test.965969452 Mar 02 01:20:49 PM PST 24 Mar 02 01:20:50 PM PST 24 14467373 ps
T50 /workspace/coverage/cover_reg_top/19.keymgr_dpe_tl_intg_err.1941384822 Mar 02 01:20:33 PM PST 24 Mar 02 01:20:38 PM PST 24 144689779 ps
T286 /workspace/coverage/cover_reg_top/4.keymgr_dpe_shadow_reg_errors.595848648 Mar 02 01:19:59 PM PST 24 Mar 02 01:20:02 PM PST 24 79409487 ps
T287 /workspace/coverage/cover_reg_top/35.keymgr_dpe_intr_test.1632646614 Mar 02 01:20:43 PM PST 24 Mar 02 01:20:44 PM PST 24 52324993 ps
T288 /workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_errors.842542132 Mar 02 01:20:06 PM PST 24 Mar 02 01:20:09 PM PST 24 50139490 ps
T289 /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_bit_bash.104665115 Mar 02 01:20:03 PM PST 24 Mar 02 01:20:12 PM PST 24 703480863 ps
T290 /workspace/coverage/cover_reg_top/1.keymgr_dpe_same_csr_outstanding.706234544 Mar 02 01:19:50 PM PST 24 Mar 02 01:19:53 PM PST 24 362616763 ps
T291 /workspace/coverage/cover_reg_top/8.keymgr_dpe_csr_mem_rw_with_rand_reset.622870084 Mar 02 01:20:06 PM PST 24 Mar 02 01:20:08 PM PST 24 25501674 ps
T57 /workspace/coverage/cover_reg_top/0.keymgr_dpe_tl_intg_err.2226836370 Mar 02 01:19:53 PM PST 24 Mar 02 01:19:59 PM PST 24 291073520 ps
T292 /workspace/coverage/cover_reg_top/4.keymgr_dpe_intr_test.1470526763 Mar 02 01:19:59 PM PST 24 Mar 02 01:20:03 PM PST 24 8081102 ps
T293 /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors.1330665956 Mar 02 01:20:15 PM PST 24 Mar 02 01:20:18 PM PST 24 108185348 ps
T294 /workspace/coverage/cover_reg_top/18.keymgr_dpe_same_csr_outstanding.1367542756 Mar 02 01:20:36 PM PST 24 Mar 02 01:20:38 PM PST 24 144571424 ps
T295 /workspace/coverage/cover_reg_top/19.keymgr_dpe_shadow_reg_errors_with_csr_rw.925028319 Mar 02 01:20:32 PM PST 24 Mar 02 01:20:35 PM PST 24 84780378 ps
T296 /workspace/coverage/cover_reg_top/7.keymgr_dpe_csr_mem_rw_with_rand_reset.571340982 Mar 02 01:20:04 PM PST 24 Mar 02 01:20:06 PM PST 24 22037533 ps
T297 /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_rw.1109590490 Mar 02 01:19:48 PM PST 24 Mar 02 01:19:50 PM PST 24 46487274 ps
T298 /workspace/coverage/cover_reg_top/45.keymgr_dpe_intr_test.1252596199 Mar 02 01:20:51 PM PST 24 Mar 02 01:20:52 PM PST 24 12301554 ps
T299 /workspace/coverage/cover_reg_top/25.keymgr_dpe_intr_test.666082660 Mar 02 01:20:30 PM PST 24 Mar 02 01:20:31 PM PST 24 23460630 ps
T300 /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_mem_rw_with_rand_reset.1538561231 Mar 02 01:19:57 PM PST 24 Mar 02 01:19:58 PM PST 24 22415740 ps
T301 /workspace/coverage/cover_reg_top/19.keymgr_dpe_intr_test.1291922721 Mar 02 01:20:34 PM PST 24 Mar 02 01:20:34 PM PST 24 51203747 ps
T302 /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_hw_reset.2197593711 Mar 02 01:19:56 PM PST 24 Mar 02 01:19:58 PM PST 24 24364940 ps
T303 /workspace/coverage/cover_reg_top/1.keymgr_dpe_tl_errors.1478301509 Mar 02 01:19:55 PM PST 24 Mar 02 01:19:58 PM PST 24 176644228 ps
T304 /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_mem_rw_with_rand_reset.731993095 Mar 02 01:20:04 PM PST 24 Mar 02 01:20:06 PM PST 24 19801452 ps
T53 /workspace/coverage/cover_reg_top/17.keymgr_dpe_tl_intg_err.347845270 Mar 02 01:20:29 PM PST 24 Mar 02 01:20:34 PM PST 24 304185383 ps
T305 /workspace/coverage/cover_reg_top/9.keymgr_dpe_csr_rw.36708405 Mar 02 01:20:10 PM PST 24 Mar 02 01:20:11 PM PST 24 89544443 ps
T306 /workspace/coverage/cover_reg_top/36.keymgr_dpe_intr_test.2823632347 Mar 02 01:20:43 PM PST 24 Mar 02 01:20:44 PM PST 24 31910798 ps
T307 /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_bit_bash.4027135038 Mar 02 01:20:03 PM PST 24 Mar 02 01:20:13 PM PST 24 171895101 ps
T308 /workspace/coverage/cover_reg_top/9.keymgr_dpe_intr_test.1937377104 Mar 02 01:20:05 PM PST 24 Mar 02 01:20:06 PM PST 24 8540853 ps

Test location /workspace/coverage/default/32.keymgr_dpe_smoke.1978919758
Short name T8
Test name
Test status
Simulation time 1001383732 ps
CPU time 19.52 seconds
Started Mar 02 01:20:44 PM PST 24
Finished Mar 02 01:21:04 PM PST 24
Peak memory 206232 kb
Host smart-8ca6bbfe-2640-4080-b5bd-6dbe8949510f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978919758 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_smoke.1978919758
Directory /workspace/32.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/3.keymgr_dpe_sec_cm.559790222
Short name T6
Test name
Test status
Simulation time 3872703140 ps
CPU time 14.03 seconds
Started Mar 02 01:20:13 PM PST 24
Finished Mar 02 01:20:27 PM PST 24
Peak memory 233100 kb
Host smart-062a5a87-89dc-4641-a055-1bf0f672f3b8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559790222 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_sec_cm.559790222
Directory /workspace/3.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_tl_intg_err.1613205075
Short name T22
Test name
Test status
Simulation time 211788222 ps
CPU time 7.62 seconds
Started Mar 02 01:20:00 PM PST 24
Finished Mar 02 01:20:09 PM PST 24
Peak memory 214792 kb
Host smart-0a7797f0-4b79-453a-a7a0-1447bf5b1ea8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613205075 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe
_tl_intg_err.1613205075
Directory /workspace/4.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_errors.1106210691
Short name T30
Test name
Test status
Simulation time 258646107 ps
CPU time 2.96 seconds
Started Mar 02 01:20:25 PM PST 24
Finished Mar 02 01:20:28 PM PST 24
Peak memory 215740 kb
Host smart-623cc818-b8e0-4f8e-a385-9359bc8e225d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106210691 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_tl_errors.
1106210691
Directory /workspace/16.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_shadow_reg_errors_with_csr_rw.3356423923
Short name T62
Test name
Test status
Simulation time 110887494 ps
CPU time 5.03 seconds
Started Mar 02 01:19:55 PM PST 24
Finished Mar 02 01:20:01 PM PST 24
Peak memory 212980 kb
Host smart-f715c4cb-310f-4953-9e48-d7e4edb6a825
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356423923 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.keymgr_dpe_shadow_reg_errors_with_csr_rw.3356423923
Directory /workspace/3.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/44.keymgr_dpe_smoke.627016475
Short name T12
Test name
Test status
Simulation time 1354039114 ps
CPU time 25 seconds
Started Mar 02 01:20:41 PM PST 24
Finished Mar 02 01:21:06 PM PST 24
Peak memory 207984 kb
Host smart-8c52e310-c2c7-45c5-b42a-809cb3652e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627016475 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_smoke.627016475
Directory /workspace/44.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_same_csr_outstanding.3617831570
Short name T71
Test name
Test status
Simulation time 64014587 ps
CPU time 1.97 seconds
Started Mar 02 01:20:15 PM PST 24
Finished Mar 02 01:20:17 PM PST 24
Peak memory 204516 kb
Host smart-ee8ad428-afb6-4e6c-afc8-124f79cd42fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617831570 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
keymgr_dpe_same_csr_outstanding.3617831570
Directory /workspace/11.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_dpe_intr_test.3593334605
Short name T40
Test name
Test status
Simulation time 52035882 ps
CPU time 0.87 seconds
Started Mar 02 01:20:31 PM PST 24
Finished Mar 02 01:20:32 PM PST 24
Peak memory 204232 kb
Host smart-1213a7ba-ae4e-475c-a48f-f08f12781fca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593334605 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_intr_test.
3593334605
Directory /workspace/28.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/default/0.keymgr_dpe_alert_test.2945242005
Short name T15
Test name
Test status
Simulation time 148479271 ps
CPU time 1 seconds
Started Mar 02 01:20:15 PM PST 24
Finished Mar 02 01:20:16 PM PST 24
Peak memory 205440 kb
Host smart-4af3d83b-2208-4527-ad16-1a20bb7a39e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945242005 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_alert_test.2
945242005
Directory /workspace/0.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_dpe_smoke.1907347238
Short name T11
Test name
Test status
Simulation time 162960936 ps
CPU time 10.28 seconds
Started Mar 02 01:20:20 PM PST 24
Finished Mar 02 01:20:31 PM PST 24
Peak memory 208124 kb
Host smart-3215c4fc-9423-4175-8115-51e3ac07a5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907347238 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_smoke.1907347238
Directory /workspace/10.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_tl_intg_err.3122250478
Short name T32
Test name
Test status
Simulation time 534822736 ps
CPU time 3.89 seconds
Started Mar 02 01:19:59 PM PST 24
Finished Mar 02 01:20:04 PM PST 24
Peak memory 212808 kb
Host smart-11c7b7d3-a725-44ec-a06e-e40135c7c3f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122250478 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe
_tl_intg_err.3122250478
Directory /workspace/3.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_tl_intg_err.3776007743
Short name T45
Test name
Test status
Simulation time 1127544509 ps
CPU time 4.35 seconds
Started Mar 02 01:20:16 PM PST 24
Finished Mar 02 01:20:20 PM PST 24
Peak memory 212640 kb
Host smart-a403bbfb-eff6-4334-8ca9-da6caa830cd1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776007743 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dp
e_tl_intg_err.3776007743
Directory /workspace/13.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/default/11.keymgr_dpe_smoke.2137214624
Short name T107
Test name
Test status
Simulation time 458574070 ps
CPU time 16.49 seconds
Started Mar 02 01:20:25 PM PST 24
Finished Mar 02 01:20:42 PM PST 24
Peak memory 207304 kb
Host smart-3e0e53e3-375a-4e0b-8f14-a912fd169bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137214624 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_smoke.2137214624
Directory /workspace/11.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_tl_intg_err.4244762096
Short name T49
Test name
Test status
Simulation time 221789922 ps
CPU time 5.13 seconds
Started Mar 02 01:20:19 PM PST 24
Finished Mar 02 01:20:24 PM PST 24
Peak memory 212756 kb
Host smart-af408cbf-fc25-4194-a8f6-4882d4d4310a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244762096 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dp
e_tl_intg_err.4244762096
Directory /workspace/12.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_tl_intg_err.1941384822
Short name T50
Test name
Test status
Simulation time 144689779 ps
CPU time 4.24 seconds
Started Mar 02 01:20:33 PM PST 24
Finished Mar 02 01:20:38 PM PST 24
Peak memory 213812 kb
Host smart-a9de0857-635f-4d53-99cf-62590fd833cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941384822 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dp
e_tl_intg_err.1941384822
Directory /workspace/19.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_tl_intg_err.219986517
Short name T43
Test name
Test status
Simulation time 212147509 ps
CPU time 3.76 seconds
Started Mar 02 01:20:24 PM PST 24
Finished Mar 02 01:20:28 PM PST 24
Peak memory 212592 kb
Host smart-9dce2b56-974b-4165-8479-0880193443c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219986517 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe
_tl_intg_err.219986517
Directory /workspace/15.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_intg_err.3495857849
Short name T55
Test name
Test status
Simulation time 353409540 ps
CPU time 2.16 seconds
Started Mar 02 01:20:22 PM PST 24
Finished Mar 02 01:20:25 PM PST 24
Peak memory 212604 kb
Host smart-ee3032a1-0a12-433c-b9e1-3cf5fc043d79
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495857849 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dp
e_tl_intg_err.3495857849
Directory /workspace/16.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_tl_intg_err.2613569850
Short name T52
Test name
Test status
Simulation time 335240384 ps
CPU time 6.51 seconds
Started Mar 02 01:19:51 PM PST 24
Finished Mar 02 01:19:57 PM PST 24
Peak memory 212664 kb
Host smart-4a2e0ac0-d661-4884-8f95-27227671ab15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613569850 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe
_tl_intg_err.2613569850
Directory /workspace/2.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_tl_intg_err.3012450019
Short name T47
Test name
Test status
Simulation time 254393028 ps
CPU time 7.91 seconds
Started Mar 02 01:20:03 PM PST 24
Finished Mar 02 01:20:11 PM PST 24
Peak memory 213968 kb
Host smart-4130ce22-ef79-4379-b453-52b9f07e6390
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012450019 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe
_tl_intg_err.3012450019
Directory /workspace/6.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_intg_err.627627533
Short name T51
Test name
Test status
Simulation time 259955524 ps
CPU time 8.73 seconds
Started Mar 02 01:20:07 PM PST 24
Finished Mar 02 01:20:16 PM PST 24
Peak memory 213844 kb
Host smart-94753c56-503c-4a00-8cbf-c2bc1741d3c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627627533 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_
tl_intg_err.627627533
Directory /workspace/7.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_dpe_sec_cm.3400364290
Short name T25
Test name
Test status
Simulation time 895795115 ps
CPU time 5.39 seconds
Started Mar 02 01:20:13 PM PST 24
Finished Mar 02 01:20:19 PM PST 24
Peak memory 233080 kb
Host smart-c825e8b6-34d7-49e8-bd2c-a79a681031d4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400364290 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_sec_cm.3400364290
Directory /workspace/0.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_mem_rw_with_rand_reset.2628885506
Short name T58
Test name
Test status
Simulation time 19809329 ps
CPU time 1.49 seconds
Started Mar 02 01:19:54 PM PST 24
Finished Mar 02 01:19:57 PM PST 24
Peak memory 212692 kb
Host smart-b30ae968-59a9-4133-ac28-8b1cefd91204
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628885506 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr_mem_rw_with_rand_reset.2628885506
Directory /workspace/0.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_intr_test.3568758598
Short name T66
Test name
Test status
Simulation time 25692924 ps
CPU time 0.71 seconds
Started Mar 02 01:19:49 PM PST 24
Finished Mar 02 01:19:50 PM PST 24
Peak memory 204300 kb
Host smart-c2c01ec3-7545-495b-b369-4b756db219d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568758598 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_intr_test.3
568758598
Directory /workspace/0.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/default/13.keymgr_dpe_smoke.325419723
Short name T80
Test name
Test status
Simulation time 2319601821 ps
CPU time 21.54 seconds
Started Mar 02 01:20:30 PM PST 24
Finished Mar 02 01:20:51 PM PST 24
Peak memory 207232 kb
Host smart-a4757abc-2065-420d-95d1-1cbd9e19e0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325419723 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_smoke.325419723
Directory /workspace/13.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/14.keymgr_dpe_smoke.18931679
Short name T166
Test name
Test status
Simulation time 5370464788 ps
CPU time 53.42 seconds
Started Mar 02 01:20:23 PM PST 24
Finished Mar 02 01:21:16 PM PST 24
Peak memory 208212 kb
Host smart-9f1dba09-ccc7-4699-afd8-3950db918277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18931679 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_smoke.18931679
Directory /workspace/14.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/15.keymgr_dpe_smoke.2847570505
Short name T9
Test name
Test status
Simulation time 2390527141 ps
CPU time 22.24 seconds
Started Mar 02 01:20:24 PM PST 24
Finished Mar 02 01:20:46 PM PST 24
Peak memory 207964 kb
Host smart-8e12924b-57e2-423d-a1cf-03e1c7a218b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847570505 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_smoke.2847570505
Directory /workspace/15.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/2.keymgr_dpe_smoke.3833559919
Short name T97
Test name
Test status
Simulation time 3332536663 ps
CPU time 58.39 seconds
Started Mar 02 01:20:20 PM PST 24
Finished Mar 02 01:21:18 PM PST 24
Peak memory 207580 kb
Host smart-9a773bf5-76b8-4ac9-86da-f423a270aad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833559919 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_smoke.3833559919
Directory /workspace/2.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/22.keymgr_dpe_smoke.3701078844
Short name T104
Test name
Test status
Simulation time 12337852259 ps
CPU time 21.74 seconds
Started Mar 02 01:20:32 PM PST 24
Finished Mar 02 01:20:54 PM PST 24
Peak memory 208032 kb
Host smart-488454c4-f9a5-4f28-899b-182a6da9a2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701078844 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_smoke.3701078844
Directory /workspace/22.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/30.keymgr_dpe_smoke.865702716
Short name T10
Test name
Test status
Simulation time 2954086370 ps
CPU time 26.45 seconds
Started Mar 02 01:20:50 PM PST 24
Finished Mar 02 01:21:16 PM PST 24
Peak memory 206572 kb
Host smart-7c9f7724-825a-4978-8870-43759f7af948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865702716 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_smoke.865702716
Directory /workspace/30.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/31.keymgr_dpe_smoke.1586374939
Short name T102
Test name
Test status
Simulation time 10526342969 ps
CPU time 206.9 seconds
Started Mar 02 01:20:32 PM PST 24
Finished Mar 02 01:23:59 PM PST 24
Peak memory 208312 kb
Host smart-2377c4bb-7b0d-4ff5-919a-eb8e0b882803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586374939 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_smoke.1586374939
Directory /workspace/31.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/33.keymgr_dpe_smoke.2446318415
Short name T2
Test name
Test status
Simulation time 1840881088 ps
CPU time 18.27 seconds
Started Mar 02 01:20:31 PM PST 24
Finished Mar 02 01:20:50 PM PST 24
Peak memory 207916 kb
Host smart-fac4e6b1-722b-4603-80cd-4ae7adfc8365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446318415 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_smoke.2446318415
Directory /workspace/33.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/34.keymgr_dpe_smoke.3170369884
Short name T109
Test name
Test status
Simulation time 1048926317 ps
CPU time 29.17 seconds
Started Mar 02 01:20:33 PM PST 24
Finished Mar 02 01:21:03 PM PST 24
Peak memory 207636 kb
Host smart-927d4a94-8977-4742-87a9-4eeb6b78b755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170369884 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_smoke.3170369884
Directory /workspace/34.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/37.keymgr_dpe_smoke.1696603042
Short name T103
Test name
Test status
Simulation time 2862896821 ps
CPU time 43.37 seconds
Started Mar 02 01:20:34 PM PST 24
Finished Mar 02 01:21:17 PM PST 24
Peak memory 207716 kb
Host smart-e88e8fd9-b0ec-4e96-9d59-6b3ed0dd0716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696603042 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_smoke.1696603042
Directory /workspace/37.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/38.keymgr_dpe_smoke.3397893237
Short name T99
Test name
Test status
Simulation time 3385435468 ps
CPU time 17.43 seconds
Started Mar 02 01:20:45 PM PST 24
Finished Mar 02 01:21:03 PM PST 24
Peak memory 207868 kb
Host smart-63f6c27b-d06c-4298-b4af-8b9b82c0fe11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397893237 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_smoke.3397893237
Directory /workspace/38.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/39.keymgr_dpe_smoke.3522414322
Short name T79
Test name
Test status
Simulation time 204560942 ps
CPU time 9.66 seconds
Started Mar 02 01:20:42 PM PST 24
Finished Mar 02 01:20:51 PM PST 24
Peak memory 207796 kb
Host smart-a3694562-6c99-42c7-8ba3-b92fca120e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522414322 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_smoke.3522414322
Directory /workspace/39.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/4.keymgr_dpe_smoke.924763138
Short name T100
Test name
Test status
Simulation time 1784153749 ps
CPU time 17.76 seconds
Started Mar 02 01:20:20 PM PST 24
Finished Mar 02 01:20:37 PM PST 24
Peak memory 207904 kb
Host smart-e23fff36-20d3-475f-b5a9-d46c0d945f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924763138 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_smoke.924763138
Directory /workspace/4.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_aliasing.2749092199
Short name T90
Test name
Test status
Simulation time 289562660 ps
CPU time 6.85 seconds
Started Mar 02 01:19:55 PM PST 24
Finished Mar 02 01:20:03 PM PST 24
Peak memory 204504 kb
Host smart-20c05a6b-4832-4fe3-b054-554957e9d814
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749092199 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_cs
r_aliasing.2749092199
Directory /workspace/0.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_bit_bash.1126367959
Short name T95
Test name
Test status
Simulation time 898013996 ps
CPU time 12.56 seconds
Started Mar 02 01:19:49 PM PST 24
Finished Mar 02 01:20:02 PM PST 24
Peak memory 204356 kb
Host smart-d9e4f79b-5bfc-417e-baf2-6e76c2cca3a2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126367959 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_cs
r_bit_bash.1126367959
Directory /workspace/0.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_hw_reset.2097452006
Short name T277
Test name
Test status
Simulation time 50906433 ps
CPU time 1.05 seconds
Started Mar 02 01:19:49 PM PST 24
Finished Mar 02 01:19:51 PM PST 24
Peak memory 204480 kb
Host smart-cd676963-429b-49bd-ad97-312786d29cb4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097452006 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_cs
r_hw_reset.2097452006
Directory /workspace/0.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_rw.2187196113
Short name T77
Test name
Test status
Simulation time 11061721 ps
CPU time 0.97 seconds
Started Mar 02 01:19:55 PM PST 24
Finished Mar 02 01:19:57 PM PST 24
Peak memory 204360 kb
Host smart-5fd72de1-2794-4734-8286-1c0426c320ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187196113 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr_rw.2
187196113
Directory /workspace/0.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_same_csr_outstanding.4225939914
Short name T209
Test name
Test status
Simulation time 113620204 ps
CPU time 1.67 seconds
Started Mar 02 01:19:55 PM PST 24
Finished Mar 02 01:19:58 PM PST 24
Peak memory 204448 kb
Host smart-f0b983e3-5d66-46d9-bc3b-a746669cedc0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225939914 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.k
eymgr_dpe_same_csr_outstanding.4225939914
Directory /workspace/0.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_shadow_reg_errors.1507574894
Short name T197
Test name
Test status
Simulation time 77282810 ps
CPU time 2.41 seconds
Started Mar 02 01:19:49 PM PST 24
Finished Mar 02 01:19:52 PM PST 24
Peak memory 216512 kb
Host smart-fb542f8d-bf01-4436-96fd-8b2929278733
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507574894 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keym
gr_dpe_shadow_reg_errors.1507574894
Directory /workspace/0.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_shadow_reg_errors_with_csr_rw.2698270763
Short name T220
Test name
Test status
Simulation time 134913274 ps
CPU time 4.57 seconds
Started Mar 02 01:19:50 PM PST 24
Finished Mar 02 01:19:55 PM PST 24
Peak memory 213156 kb
Host smart-017cff9e-b275-48bf-b657-d87f7f2d3699
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698270763 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.keymgr_dpe_shadow_reg_errors_with_csr_rw.2698270763
Directory /workspace/0.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_tl_errors.3124095647
Short name T36
Test name
Test status
Simulation time 27709911 ps
CPU time 2.07 seconds
Started Mar 02 01:19:50 PM PST 24
Finished Mar 02 01:19:52 PM PST 24
Peak memory 215272 kb
Host smart-8a99b949-20b1-4576-83ab-571c4919a7d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124095647 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_tl_errors.3
124095647
Directory /workspace/0.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_tl_intg_err.2226836370
Short name T57
Test name
Test status
Simulation time 291073520 ps
CPU time 4.02 seconds
Started Mar 02 01:19:53 PM PST 24
Finished Mar 02 01:19:59 PM PST 24
Peak memory 213636 kb
Host smart-9d95ff0a-9667-420d-bdaf-317dedb76f44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226836370 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe
_tl_intg_err.2226836370
Directory /workspace/0.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_aliasing.4249503600
Short name T193
Test name
Test status
Simulation time 183493943 ps
CPU time 5.2 seconds
Started Mar 02 01:19:57 PM PST 24
Finished Mar 02 01:20:02 PM PST 24
Peak memory 204492 kb
Host smart-57452032-d2ce-4c7a-ba2f-7a9c892d12b4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249503600 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_cs
r_aliasing.4249503600
Directory /workspace/1.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_bit_bash.581748331
Short name T88
Test name
Test status
Simulation time 454548943 ps
CPU time 12.1 seconds
Started Mar 02 01:19:53 PM PST 24
Finished Mar 02 01:20:07 PM PST 24
Peak memory 204484 kb
Host smart-02a77867-fd72-4e0d-9ce5-17a990bdbc7e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581748331 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_csr
_bit_bash.581748331
Directory /workspace/1.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_hw_reset.2965485956
Short name T204
Test name
Test status
Simulation time 70776391 ps
CPU time 0.87 seconds
Started Mar 02 01:19:49 PM PST 24
Finished Mar 02 01:19:50 PM PST 24
Peak memory 204224 kb
Host smart-246869c5-5a97-439b-b4ea-30305c9501d0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965485956 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_cs
r_hw_reset.2965485956
Directory /workspace/1.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_mem_rw_with_rand_reset.1255618793
Short name T35
Test name
Test status
Simulation time 24774207 ps
CPU time 1 seconds
Started Mar 02 01:19:52 PM PST 24
Finished Mar 02 01:19:54 PM PST 24
Peak memory 204348 kb
Host smart-38d84c56-7ff2-4568-bd15-d2e954bab94e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255618793 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_csr_mem_rw_with_rand_reset.1255618793
Directory /workspace/1.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_rw.2955692991
Short name T248
Test name
Test status
Simulation time 14118904 ps
CPU time 1.05 seconds
Started Mar 02 01:19:57 PM PST 24
Finished Mar 02 01:19:59 PM PST 24
Peak memory 204376 kb
Host smart-e7f01b9e-7d50-4b2e-a5f2-87652e81ae1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955692991 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_csr_rw.2
955692991
Directory /workspace/1.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_intr_test.799243895
Short name T227
Test name
Test status
Simulation time 10878648 ps
CPU time 0.77 seconds
Started Mar 02 01:19:53 PM PST 24
Finished Mar 02 01:19:57 PM PST 24
Peak memory 204272 kb
Host smart-53d7f1ac-ceb1-40e8-a84b-e221219fa76b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799243895 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_intr_test.799243895
Directory /workspace/1.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_same_csr_outstanding.706234544
Short name T290
Test name
Test status
Simulation time 362616763 ps
CPU time 3.39 seconds
Started Mar 02 01:19:50 PM PST 24
Finished Mar 02 01:19:53 PM PST 24
Peak memory 204456 kb
Host smart-bb581f93-5ccb-4085-9283-e386087070a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706234544 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.ke
ymgr_dpe_same_csr_outstanding.706234544
Directory /workspace/1.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_shadow_reg_errors.1408680142
Short name T192
Test name
Test status
Simulation time 182267312 ps
CPU time 2.05 seconds
Started Mar 02 01:19:49 PM PST 24
Finished Mar 02 01:19:51 PM PST 24
Peak memory 213064 kb
Host smart-d14ea5f4-f121-4eb3-af17-01145fa3e899
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408680142 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keym
gr_dpe_shadow_reg_errors.1408680142
Directory /workspace/1.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_shadow_reg_errors_with_csr_rw.1126946730
Short name T257
Test name
Test status
Simulation time 676551026 ps
CPU time 4.97 seconds
Started Mar 02 01:19:50 PM PST 24
Finished Mar 02 01:19:55 PM PST 24
Peak memory 213024 kb
Host smart-ae688f55-28c8-48ec-bbee-bf7e8c39d599
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126946730 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.keymgr_dpe_shadow_reg_errors_with_csr_rw.1126946730
Directory /workspace/1.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_tl_errors.1478301509
Short name T303
Test name
Test status
Simulation time 176644228 ps
CPU time 1.96 seconds
Started Mar 02 01:19:55 PM PST 24
Finished Mar 02 01:19:58 PM PST 24
Peak memory 212624 kb
Host smart-4823ea0c-9141-40c7-9736-2540de51b695
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478301509 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_tl_errors.1
478301509
Directory /workspace/1.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_tl_intg_err.104106339
Short name T54
Test name
Test status
Simulation time 349721934 ps
CPU time 2.89 seconds
Started Mar 02 01:19:50 PM PST 24
Finished Mar 02 01:19:53 PM PST 24
Peak memory 220720 kb
Host smart-896ae443-0fed-42f0-a4ad-f5de2fb48815
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104106339 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_
tl_intg_err.104106339
Directory /workspace/1.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_csr_mem_rw_with_rand_reset.1250085405
Short name T83
Test name
Test status
Simulation time 25072676 ps
CPU time 1.07 seconds
Started Mar 02 01:20:09 PM PST 24
Finished Mar 02 01:20:10 PM PST 24
Peak memory 204536 kb
Host smart-abb3c599-33d5-4778-9e7a-2a88d4dd8a7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250085405 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_csr_mem_rw_with_rand_reset.1250085405
Directory /workspace/10.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_csr_rw.4208725432
Short name T173
Test name
Test status
Simulation time 16696193 ps
CPU time 1.03 seconds
Started Mar 02 01:20:04 PM PST 24
Finished Mar 02 01:20:06 PM PST 24
Peak memory 204308 kb
Host smart-8de0fd5c-7832-43b0-8526-5783948395a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208725432 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_csr_rw.
4208725432
Directory /workspace/10.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_intr_test.3210980139
Short name T93
Test name
Test status
Simulation time 37711317 ps
CPU time 0.8 seconds
Started Mar 02 01:20:06 PM PST 24
Finished Mar 02 01:20:07 PM PST 24
Peak memory 204280 kb
Host smart-960bc471-baa9-4374-8472-167cb07252df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210980139 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_intr_test.
3210980139
Directory /workspace/10.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_same_csr_outstanding.346764440
Short name T254
Test name
Test status
Simulation time 173358664 ps
CPU time 1.32 seconds
Started Mar 02 01:20:07 PM PST 24
Finished Mar 02 01:20:09 PM PST 24
Peak memory 204500 kb
Host smart-b4d641d7-50ca-4d6d-ab20-11d0ed70ea04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346764440 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.k
eymgr_dpe_same_csr_outstanding.346764440
Directory /workspace/10.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_shadow_reg_errors.668352278
Short name T258
Test name
Test status
Simulation time 232171650 ps
CPU time 3.99 seconds
Started Mar 02 01:20:08 PM PST 24
Finished Mar 02 01:20:12 PM PST 24
Peak memory 213032 kb
Host smart-8169d63c-6cc0-4be5-854f-3fd422179de6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668352278 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keym
gr_dpe_shadow_reg_errors.668352278
Directory /workspace/10.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_shadow_reg_errors_with_csr_rw.4066215873
Short name T283
Test name
Test status
Simulation time 215887615 ps
CPU time 4.27 seconds
Started Mar 02 01:20:06 PM PST 24
Finished Mar 02 01:20:11 PM PST 24
Peak memory 213064 kb
Host smart-7356f6e7-be64-443c-a8c9-e7a83c72f914
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066215873 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.keymgr_dpe_shadow_reg_errors_with_csr_rw.4066215873
Directory /workspace/10.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_tl_errors.4248980016
Short name T183
Test name
Test status
Simulation time 261169156 ps
CPU time 2.76 seconds
Started Mar 02 01:20:06 PM PST 24
Finished Mar 02 01:20:09 PM PST 24
Peak memory 213492 kb
Host smart-8bccd4ea-ca95-4275-9d74-f68fed3fe99f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248980016 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_tl_errors.
4248980016
Directory /workspace/10.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_tl_intg_err.1685697961
Short name T56
Test name
Test status
Simulation time 348000801 ps
CPU time 4.29 seconds
Started Mar 02 01:20:06 PM PST 24
Finished Mar 02 01:20:11 PM PST 24
Peak memory 213908 kb
Host smart-d238c656-9a40-4e2a-918c-930f126d5207
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685697961 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dp
e_tl_intg_err.1685697961
Directory /workspace/10.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_csr_mem_rw_with_rand_reset.3285783809
Short name T179
Test name
Test status
Simulation time 18624600 ps
CPU time 1.15 seconds
Started Mar 02 01:20:19 PM PST 24
Finished Mar 02 01:20:20 PM PST 24
Peak memory 212672 kb
Host smart-199f2bc3-8cf7-4279-bb8c-ddafc4b31730
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285783809 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_csr_mem_rw_with_rand_reset.3285783809
Directory /workspace/11.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_csr_rw.1104575687
Short name T198
Test name
Test status
Simulation time 98608272 ps
CPU time 0.99 seconds
Started Mar 02 01:20:28 PM PST 24
Finished Mar 02 01:20:29 PM PST 24
Peak memory 204328 kb
Host smart-aaa8714c-0ef5-4175-a6a3-77e086e515a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104575687 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_csr_rw.
1104575687
Directory /workspace/11.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_intr_test.132197608
Short name T272
Test name
Test status
Simulation time 21971415 ps
CPU time 0.72 seconds
Started Mar 02 01:20:16 PM PST 24
Finished Mar 02 01:20:17 PM PST 24
Peak memory 204280 kb
Host smart-7703f001-4f2a-4c75-9549-3baf4e022086
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132197608 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_intr_test.132197608
Directory /workspace/11.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_shadow_reg_errors.3369717042
Short name T174
Test name
Test status
Simulation time 285444063 ps
CPU time 3.62 seconds
Started Mar 02 01:20:09 PM PST 24
Finished Mar 02 01:20:12 PM PST 24
Peak memory 217144 kb
Host smart-fe2cf3a5-0825-4fe2-965a-9b33a2a089ee
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369717042 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.key
mgr_dpe_shadow_reg_errors.3369717042
Directory /workspace/11.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_shadow_reg_errors_with_csr_rw.108914865
Short name T280
Test name
Test status
Simulation time 509690537 ps
CPU time 4.1 seconds
Started Mar 02 01:20:10 PM PST 24
Finished Mar 02 01:20:14 PM PST 24
Peak memory 212988 kb
Host smart-cba657a3-4842-44fc-bea8-1c8842b80a12
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108914865 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 11.keymgr_dpe_shadow_reg_errors_with_csr_rw.108914865
Directory /workspace/11.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_tl_errors.2432251887
Short name T199
Test name
Test status
Simulation time 84681826 ps
CPU time 2.37 seconds
Started Mar 02 01:20:19 PM PST 24
Finished Mar 02 01:20:22 PM PST 24
Peak memory 220844 kb
Host smart-d98fdaa0-3ca8-4b34-90b5-42b301e529ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432251887 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_tl_errors.
2432251887
Directory /workspace/11.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_tl_intg_err.3801694259
Short name T31
Test name
Test status
Simulation time 716239115 ps
CPU time 2.52 seconds
Started Mar 02 01:20:17 PM PST 24
Finished Mar 02 01:20:19 PM PST 24
Peak memory 212776 kb
Host smart-f8fe2821-60b6-4ff0-a754-2cfdfe402bc5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801694259 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dp
e_tl_intg_err.3801694259
Directory /workspace/11.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_csr_mem_rw_with_rand_reset.2492499734
Short name T249
Test name
Test status
Simulation time 123663453 ps
CPU time 1.35 seconds
Started Mar 02 01:20:19 PM PST 24
Finished Mar 02 01:20:20 PM PST 24
Peak memory 212636 kb
Host smart-44934b4a-a3d3-421f-ac03-e6e886fd5e43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492499734 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_csr_mem_rw_with_rand_reset.2492499734
Directory /workspace/12.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_csr_rw.3693140487
Short name T65
Test name
Test status
Simulation time 41734087 ps
CPU time 1.25 seconds
Started Mar 02 01:20:13 PM PST 24
Finished Mar 02 01:20:15 PM PST 24
Peak memory 204500 kb
Host smart-8529756c-7491-4328-9808-df9fbce04a87
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693140487 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_csr_rw.
3693140487
Directory /workspace/12.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_intr_test.1724798238
Short name T68
Test name
Test status
Simulation time 22457290 ps
CPU time 1.04 seconds
Started Mar 02 01:20:17 PM PST 24
Finished Mar 02 01:20:18 PM PST 24
Peak memory 204424 kb
Host smart-87de412e-175d-4593-aed9-fbc37617116a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724798238 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_intr_test.
1724798238
Directory /workspace/12.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_same_csr_outstanding.1457251913
Short name T226
Test name
Test status
Simulation time 59844443 ps
CPU time 1.31 seconds
Started Mar 02 01:20:19 PM PST 24
Finished Mar 02 01:20:20 PM PST 24
Peak memory 204436 kb
Host smart-3d03680a-c408-4904-b610-7012241a91f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457251913 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
keymgr_dpe_same_csr_outstanding.1457251913
Directory /workspace/12.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_shadow_reg_errors.2441701664
Short name T44
Test name
Test status
Simulation time 122622334 ps
CPU time 3.34 seconds
Started Mar 02 01:20:16 PM PST 24
Finished Mar 02 01:20:20 PM PST 24
Peak memory 216584 kb
Host smart-665838b5-09b5-4455-ad37-7b768645a542
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441701664 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.key
mgr_dpe_shadow_reg_errors.2441701664
Directory /workspace/12.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_shadow_reg_errors_with_csr_rw.232796169
Short name T219
Test name
Test status
Simulation time 514105215 ps
CPU time 4.84 seconds
Started Mar 02 01:20:16 PM PST 24
Finished Mar 02 01:20:20 PM PST 24
Peak memory 213048 kb
Host smart-11b666cb-b500-479b-960b-4befda5019ea
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232796169 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 12.keymgr_dpe_shadow_reg_errors_with_csr_rw.232796169
Directory /workspace/12.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_tl_errors.3573695432
Short name T238
Test name
Test status
Simulation time 265475815 ps
CPU time 2.12 seconds
Started Mar 02 01:20:15 PM PST 24
Finished Mar 02 01:20:17 PM PST 24
Peak memory 214812 kb
Host smart-cb462cea-5abe-4ce1-ab9c-02a4d8e33bf3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573695432 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_tl_errors.
3573695432
Directory /workspace/12.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_csr_mem_rw_with_rand_reset.1849349337
Short name T87
Test name
Test status
Simulation time 45967643 ps
CPU time 1.05 seconds
Started Mar 02 01:20:16 PM PST 24
Finished Mar 02 01:20:17 PM PST 24
Peak memory 212716 kb
Host smart-0a2b316b-0acf-48a4-9c5c-391931898230
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849349337 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_csr_mem_rw_with_rand_reset.1849349337
Directory /workspace/13.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_csr_rw.1019306674
Short name T250
Test name
Test status
Simulation time 68271108 ps
CPU time 1.13 seconds
Started Mar 02 01:20:16 PM PST 24
Finished Mar 02 01:20:17 PM PST 24
Peak memory 204180 kb
Host smart-4ea0d179-73ec-4c49-b94f-830c6f7fda28
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019306674 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_csr_rw.
1019306674
Directory /workspace/13.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_intr_test.979436012
Short name T86
Test name
Test status
Simulation time 21136682 ps
CPU time 0.85 seconds
Started Mar 02 01:20:19 PM PST 24
Finished Mar 02 01:20:20 PM PST 24
Peak memory 204264 kb
Host smart-0b9684bf-609d-4c08-ae1d-f1052b411b28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979436012 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_intr_test.979436012
Directory /workspace/13.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_same_csr_outstanding.420167799
Short name T218
Test name
Test status
Simulation time 115099448 ps
CPU time 1.4 seconds
Started Mar 02 01:20:16 PM PST 24
Finished Mar 02 01:20:18 PM PST 24
Peak memory 204480 kb
Host smart-6bd905f7-eae3-436c-99e3-7c1b1a023cae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420167799 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.k
eymgr_dpe_same_csr_outstanding.420167799
Directory /workspace/13.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors.1330665956
Short name T293
Test name
Test status
Simulation time 108185348 ps
CPU time 3.02 seconds
Started Mar 02 01:20:15 PM PST 24
Finished Mar 02 01:20:18 PM PST 24
Peak memory 212980 kb
Host smart-27d5a4f8-0b5e-4bf8-a2ce-f43df68cdcf0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330665956 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.key
mgr_dpe_shadow_reg_errors.1330665956
Directory /workspace/13.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors_with_csr_rw.3422653680
Short name T265
Test name
Test status
Simulation time 153821342 ps
CPU time 3.41 seconds
Started Mar 02 01:20:17 PM PST 24
Finished Mar 02 01:20:21 PM PST 24
Peak memory 213032 kb
Host smart-6cbe41b2-e03c-46ed-8dde-bc81a89cf5e4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422653680 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.keymgr_dpe_shadow_reg_errors_with_csr_rw.3422653680
Directory /workspace/13.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_tl_errors.2566285570
Short name T233
Test name
Test status
Simulation time 122253773 ps
CPU time 2.08 seconds
Started Mar 02 01:20:14 PM PST 24
Finished Mar 02 01:20:16 PM PST 24
Peak memory 215432 kb
Host smart-0d833303-65f4-49bb-9c7e-e8bc6b5e777d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566285570 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_tl_errors.
2566285570
Directory /workspace/13.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_csr_mem_rw_with_rand_reset.1102775170
Short name T64
Test name
Test status
Simulation time 105162030 ps
CPU time 2.22 seconds
Started Mar 02 01:20:33 PM PST 24
Finished Mar 02 01:20:35 PM PST 24
Peak memory 212744 kb
Host smart-9175f131-aa33-4546-8b1d-f22e7f0139ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102775170 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_csr_mem_rw_with_rand_reset.1102775170
Directory /workspace/14.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_csr_rw.1910411685
Short name T172
Test name
Test status
Simulation time 48668445 ps
CPU time 0.96 seconds
Started Mar 02 01:20:24 PM PST 24
Finished Mar 02 01:20:25 PM PST 24
Peak memory 204408 kb
Host smart-0b238d3f-9b39-499d-b7ed-8bb97a4345c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910411685 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_csr_rw.
1910411685
Directory /workspace/14.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_intr_test.934934991
Short name T85
Test name
Test status
Simulation time 22301952 ps
CPU time 0.73 seconds
Started Mar 02 01:20:31 PM PST 24
Finished Mar 02 01:20:32 PM PST 24
Peak memory 203716 kb
Host smart-1567ac8b-9c58-41e4-baa3-8bb5590203d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934934991 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_intr_test.934934991
Directory /workspace/14.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_same_csr_outstanding.2123395817
Short name T74
Test name
Test status
Simulation time 50202266 ps
CPU time 1.93 seconds
Started Mar 02 01:20:31 PM PST 24
Finished Mar 02 01:20:33 PM PST 24
Peak memory 203872 kb
Host smart-fb5d4728-5461-44ae-8cf3-660ae14b0c52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123395817 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
keymgr_dpe_same_csr_outstanding.2123395817
Directory /workspace/14.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_shadow_reg_errors.2383364880
Short name T92
Test name
Test status
Simulation time 65920771 ps
CPU time 1.62 seconds
Started Mar 02 01:20:28 PM PST 24
Finished Mar 02 01:20:30 PM PST 24
Peak memory 212992 kb
Host smart-f4f208bc-9b2f-4345-80de-46172dc974e1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383364880 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.key
mgr_dpe_shadow_reg_errors.2383364880
Directory /workspace/14.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_shadow_reg_errors_with_csr_rw.1515808677
Short name T182
Test name
Test status
Simulation time 543471315 ps
CPU time 5.61 seconds
Started Mar 02 01:20:22 PM PST 24
Finished Mar 02 01:20:27 PM PST 24
Peak memory 213040 kb
Host smart-dca00ddb-9722-44e8-8324-492109b584aa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515808677 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.keymgr_dpe_shadow_reg_errors_with_csr_rw.1515808677
Directory /workspace/14.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_tl_errors.2450495699
Short name T89
Test name
Test status
Simulation time 653170127 ps
CPU time 3.58 seconds
Started Mar 02 01:20:19 PM PST 24
Finished Mar 02 01:20:22 PM PST 24
Peak memory 220664 kb
Host smart-04bb0050-61dc-4a17-b65b-8cbea60dde70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450495699 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_tl_errors.
2450495699
Directory /workspace/14.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_tl_intg_err.682860439
Short name T194
Test name
Test status
Simulation time 71510549 ps
CPU time 2.99 seconds
Started Mar 02 01:20:28 PM PST 24
Finished Mar 02 01:20:31 PM PST 24
Peak memory 212648 kb
Host smart-3f29a7d0-88c2-45e5-bb0b-748764b32c05
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682860439 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe
_tl_intg_err.682860439
Directory /workspace/14.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_csr_mem_rw_with_rand_reset.151847329
Short name T177
Test name
Test status
Simulation time 158374615 ps
CPU time 1.1 seconds
Started Mar 02 01:20:22 PM PST 24
Finished Mar 02 01:20:24 PM PST 24
Peak memory 212692 kb
Host smart-2e9a4397-76ab-4712-91a3-3c14d29782d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151847329 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_csr_mem_rw_with_rand_reset.151847329
Directory /workspace/15.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_csr_rw.1166814455
Short name T274
Test name
Test status
Simulation time 17518322 ps
CPU time 0.93 seconds
Started Mar 02 01:20:26 PM PST 24
Finished Mar 02 01:20:27 PM PST 24
Peak memory 204272 kb
Host smart-2f0146cd-dc28-47c4-b4b7-2eca008c0be8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166814455 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_csr_rw.
1166814455
Directory /workspace/15.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_intr_test.3381832232
Short name T235
Test name
Test status
Simulation time 28167533 ps
CPU time 0.95 seconds
Started Mar 02 01:20:32 PM PST 24
Finished Mar 02 01:20:33 PM PST 24
Peak memory 204432 kb
Host smart-e90d9b3f-67c8-4779-8d8b-e7eaa6ef19e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381832232 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_intr_test.
3381832232
Directory /workspace/15.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_same_csr_outstanding.2185359249
Short name T181
Test name
Test status
Simulation time 35496218 ps
CPU time 2.26 seconds
Started Mar 02 01:20:30 PM PST 24
Finished Mar 02 01:20:32 PM PST 24
Peak memory 204480 kb
Host smart-14ff9971-7c10-4e59-ab05-27dcb13d7b56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185359249 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
keymgr_dpe_same_csr_outstanding.2185359249
Directory /workspace/15.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors.1969471902
Short name T59
Test name
Test status
Simulation time 257926719 ps
CPU time 1.64 seconds
Started Mar 02 01:20:26 PM PST 24
Finished Mar 02 01:20:27 PM PST 24
Peak memory 213032 kb
Host smart-477c88c1-173a-4683-9dbb-42024a31f61e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969471902 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.key
mgr_dpe_shadow_reg_errors.1969471902
Directory /workspace/15.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors_with_csr_rw.4060049564
Short name T200
Test name
Test status
Simulation time 387862967 ps
CPU time 4.06 seconds
Started Mar 02 01:20:22 PM PST 24
Finished Mar 02 01:20:26 PM PST 24
Peak memory 213000 kb
Host smart-524a5a8e-d8ca-49bb-98b6-55551c6a7e15
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060049564 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.keymgr_dpe_shadow_reg_errors_with_csr_rw.4060049564
Directory /workspace/15.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_tl_errors.2744637574
Short name T206
Test name
Test status
Simulation time 49956641 ps
CPU time 1.61 seconds
Started Mar 02 01:20:30 PM PST 24
Finished Mar 02 01:20:31 PM PST 24
Peak memory 204392 kb
Host smart-5316ca8d-a8b3-4e0d-9b3b-0e21e40da033
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744637574 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_tl_errors.
2744637574
Directory /workspace/15.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_csr_mem_rw_with_rand_reset.544446388
Short name T215
Test name
Test status
Simulation time 50893551 ps
CPU time 1.76 seconds
Started Mar 02 01:20:24 PM PST 24
Finished Mar 02 01:20:26 PM PST 24
Peak memory 212772 kb
Host smart-94d6baa4-cb14-4ec4-8fae-065d7544c3aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544446388 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_csr_mem_rw_with_rand_reset.544446388
Directory /workspace/16.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_csr_rw.3302043355
Short name T268
Test name
Test status
Simulation time 9973976 ps
CPU time 1.07 seconds
Started Mar 02 01:20:30 PM PST 24
Finished Mar 02 01:20:31 PM PST 24
Peak memory 204396 kb
Host smart-d24161f9-ac48-4404-86c1-815dc495e18f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302043355 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_csr_rw.
3302043355
Directory /workspace/16.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_intr_test.4060193003
Short name T69
Test name
Test status
Simulation time 35365478 ps
CPU time 0.85 seconds
Started Mar 02 01:20:24 PM PST 24
Finished Mar 02 01:20:25 PM PST 24
Peak memory 204312 kb
Host smart-d6bcd4f3-4621-4ebf-8147-b473018e7d9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060193003 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_intr_test.
4060193003
Directory /workspace/16.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_same_csr_outstanding.3796809051
Short name T228
Test name
Test status
Simulation time 54410336 ps
CPU time 1.86 seconds
Started Mar 02 01:20:23 PM PST 24
Finished Mar 02 01:20:25 PM PST 24
Peak memory 204448 kb
Host smart-1f9d1427-8d6e-438b-86e4-8f969b50f65c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796809051 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
keymgr_dpe_same_csr_outstanding.3796809051
Directory /workspace/16.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_shadow_reg_errors.2687444497
Short name T239
Test name
Test status
Simulation time 679486331 ps
CPU time 1.83 seconds
Started Mar 02 01:20:24 PM PST 24
Finished Mar 02 01:20:26 PM PST 24
Peak memory 213052 kb
Host smart-9aacdd60-70ee-458e-844d-d34e3ac2717f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687444497 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.key
mgr_dpe_shadow_reg_errors.2687444497
Directory /workspace/16.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_shadow_reg_errors_with_csr_rw.743284966
Short name T208
Test name
Test status
Simulation time 1005310619 ps
CPU time 8.79 seconds
Started Mar 02 01:20:24 PM PST 24
Finished Mar 02 01:20:33 PM PST 24
Peak memory 212980 kb
Host smart-92f46833-b1a1-4c16-a73e-5b33358c2c22
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743284966 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 16.keymgr_dpe_shadow_reg_errors_with_csr_rw.743284966
Directory /workspace/16.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_csr_mem_rw_with_rand_reset.3671583247
Short name T171
Test name
Test status
Simulation time 380193814 ps
CPU time 1.36 seconds
Started Mar 02 01:20:23 PM PST 24
Finished Mar 02 01:20:24 PM PST 24
Peak memory 220848 kb
Host smart-0e0550b0-42e9-4c74-9462-24277e952bc1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671583247 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_csr_mem_rw_with_rand_reset.3671583247
Directory /workspace/17.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_csr_rw.1490186221
Short name T231
Test name
Test status
Simulation time 31711000 ps
CPU time 0.92 seconds
Started Mar 02 01:20:29 PM PST 24
Finished Mar 02 01:20:30 PM PST 24
Peak memory 204376 kb
Host smart-703c16f8-9cb1-4a12-9bcd-951e2eb4936b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490186221 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_csr_rw.
1490186221
Directory /workspace/17.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_intr_test.3239761401
Short name T42
Test name
Test status
Simulation time 40262642 ps
CPU time 0.86 seconds
Started Mar 02 01:20:27 PM PST 24
Finished Mar 02 01:20:28 PM PST 24
Peak memory 204268 kb
Host smart-14b2ade7-d7d1-425d-b599-6bda809d8aff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239761401 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_intr_test.
3239761401
Directory /workspace/17.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_same_csr_outstanding.90076868
Short name T241
Test name
Test status
Simulation time 104352409 ps
CPU time 1.73 seconds
Started Mar 02 01:20:24 PM PST 24
Finished Mar 02 01:20:25 PM PST 24
Peak memory 204564 kb
Host smart-53cff932-8776-4637-904c-25111d9a193a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90076868 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=k
eymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ke
ymgr_dpe_same_csr_outstanding.90076868
Directory /workspace/17.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_shadow_reg_errors.915557595
Short name T207
Test name
Test status
Simulation time 169599039 ps
CPU time 2.94 seconds
Started Mar 02 01:20:22 PM PST 24
Finished Mar 02 01:20:25 PM PST 24
Peak memory 212960 kb
Host smart-245b175a-dfd5-497d-9261-e8efba116bca
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915557595 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keym
gr_dpe_shadow_reg_errors.915557595
Directory /workspace/17.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_shadow_reg_errors_with_csr_rw.3303201145
Short name T188
Test name
Test status
Simulation time 82685525 ps
CPU time 3.77 seconds
Started Mar 02 01:20:27 PM PST 24
Finished Mar 02 01:20:30 PM PST 24
Peak memory 212984 kb
Host smart-6ca0a568-d0c0-4000-aedb-5eab9a004215
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303201145 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.keymgr_dpe_shadow_reg_errors_with_csr_rw.3303201145
Directory /workspace/17.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_tl_errors.3778156869
Short name T37
Test name
Test status
Simulation time 125167643 ps
CPU time 3.14 seconds
Started Mar 02 01:20:22 PM PST 24
Finished Mar 02 01:20:26 PM PST 24
Peak memory 220592 kb
Host smart-57a27920-efcb-427e-a38d-bfea6a209f4a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778156869 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_tl_errors.
3778156869
Directory /workspace/17.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_tl_intg_err.347845270
Short name T53
Test name
Test status
Simulation time 304185383 ps
CPU time 4.16 seconds
Started Mar 02 01:20:29 PM PST 24
Finished Mar 02 01:20:34 PM PST 24
Peak memory 213480 kb
Host smart-cd10ea06-5e0a-4e98-bc68-9809e94f6d01
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347845270 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe
_tl_intg_err.347845270
Directory /workspace/17.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_csr_mem_rw_with_rand_reset.446451520
Short name T213
Test name
Test status
Simulation time 60510781 ps
CPU time 1.43 seconds
Started Mar 02 01:20:37 PM PST 24
Finished Mar 02 01:20:39 PM PST 24
Peak memory 204524 kb
Host smart-3225ad90-a984-443a-97ba-9f92bd8ce2a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446451520 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_csr_mem_rw_with_rand_reset.446451520
Directory /workspace/18.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_csr_rw.2646909180
Short name T261
Test name
Test status
Simulation time 12034546 ps
CPU time 1.01 seconds
Started Mar 02 01:20:30 PM PST 24
Finished Mar 02 01:20:31 PM PST 24
Peak memory 204592 kb
Host smart-01ff5ae1-7943-475c-8334-e0633dbd90e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646909180 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_csr_rw.
2646909180
Directory /workspace/18.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_intr_test.3273032622
Short name T251
Test name
Test status
Simulation time 41393142 ps
CPU time 0.75 seconds
Started Mar 02 01:20:39 PM PST 24
Finished Mar 02 01:20:40 PM PST 24
Peak memory 204272 kb
Host smart-62ed273b-59f3-4729-9f61-90b5028bd37a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273032622 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_intr_test.
3273032622
Directory /workspace/18.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_same_csr_outstanding.1367542756
Short name T294
Test name
Test status
Simulation time 144571424 ps
CPU time 1.81 seconds
Started Mar 02 01:20:36 PM PST 24
Finished Mar 02 01:20:38 PM PST 24
Peak memory 204504 kb
Host smart-0622b139-abd3-4b7f-ab81-cbb862095674
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367542756 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
keymgr_dpe_same_csr_outstanding.1367542756
Directory /workspace/18.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_shadow_reg_errors.1732279555
Short name T61
Test name
Test status
Simulation time 239812702 ps
CPU time 1.91 seconds
Started Mar 02 01:20:32 PM PST 24
Finished Mar 02 01:20:34 PM PST 24
Peak memory 213080 kb
Host smart-666c2d39-ade7-4214-91b0-aa6f825fc723
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732279555 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.key
mgr_dpe_shadow_reg_errors.1732279555
Directory /workspace/18.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_shadow_reg_errors_with_csr_rw.42107409
Short name T243
Test name
Test status
Simulation time 237739960 ps
CPU time 3.17 seconds
Started Mar 02 01:20:29 PM PST 24
Finished Mar 02 01:20:32 PM PST 24
Peak memory 212956 kb
Host smart-ec187b65-e813-47e2-bd29-34d457b087cc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42107409 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_T
EST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 18.keymgr_dpe_shadow_reg_errors_with_csr_rw.42107409
Directory /workspace/18.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_tl_errors.3547847513
Short name T39
Test name
Test status
Simulation time 403361353 ps
CPU time 4.35 seconds
Started Mar 02 01:20:32 PM PST 24
Finished Mar 02 01:20:36 PM PST 24
Peak memory 215984 kb
Host smart-4a9ffa87-399c-4712-99c4-84fb6e7407cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547847513 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_tl_errors.
3547847513
Directory /workspace/18.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_tl_intg_err.3803322034
Short name T48
Test name
Test status
Simulation time 177966296 ps
CPU time 2.29 seconds
Started Mar 02 01:20:36 PM PST 24
Finished Mar 02 01:20:39 PM PST 24
Peak memory 212592 kb
Host smart-c37cf206-8c52-41d4-a34f-dd0d30c63eac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803322034 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dp
e_tl_intg_err.3803322034
Directory /workspace/18.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_csr_mem_rw_with_rand_reset.2582216622
Short name T84
Test name
Test status
Simulation time 34634063 ps
CPU time 1.62 seconds
Started Mar 02 01:20:47 PM PST 24
Finished Mar 02 01:20:49 PM PST 24
Peak memory 212692 kb
Host smart-31e574c5-9481-405c-82af-78efce38e163
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582216622 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_csr_mem_rw_with_rand_reset.2582216622
Directory /workspace/19.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_csr_rw.240113320
Short name T242
Test name
Test status
Simulation time 59603895 ps
CPU time 1.04 seconds
Started Mar 02 01:20:41 PM PST 24
Finished Mar 02 01:20:42 PM PST 24
Peak memory 204376 kb
Host smart-d907c9de-ce6e-4bc2-9f38-c5a2f15a4227
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240113320 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_csr_rw.240113320
Directory /workspace/19.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_intr_test.1291922721
Short name T301
Test name
Test status
Simulation time 51203747 ps
CPU time 0.74 seconds
Started Mar 02 01:20:34 PM PST 24
Finished Mar 02 01:20:34 PM PST 24
Peak memory 204216 kb
Host smart-c3de1120-7229-42fe-a027-fda5133df80f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291922721 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_intr_test.
1291922721
Directory /workspace/19.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_same_csr_outstanding.3082149858
Short name T195
Test name
Test status
Simulation time 908237845 ps
CPU time 1.99 seconds
Started Mar 02 01:20:33 PM PST 24
Finished Mar 02 01:20:36 PM PST 24
Peak memory 204384 kb
Host smart-2aef6466-b594-43cf-a5ed-252c09af7c1d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082149858 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
keymgr_dpe_same_csr_outstanding.3082149858
Directory /workspace/19.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_shadow_reg_errors.1970895786
Short name T205
Test name
Test status
Simulation time 215398460 ps
CPU time 1.29 seconds
Started Mar 02 01:20:36 PM PST 24
Finished Mar 02 01:20:38 PM PST 24
Peak memory 213252 kb
Host smart-c3e0bb97-4aa6-4a0a-9e86-5cdd8210adcc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970895786 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.key
mgr_dpe_shadow_reg_errors.1970895786
Directory /workspace/19.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_shadow_reg_errors_with_csr_rw.925028319
Short name T295
Test name
Test status
Simulation time 84780378 ps
CPU time 2.65 seconds
Started Mar 02 01:20:32 PM PST 24
Finished Mar 02 01:20:35 PM PST 24
Peak memory 213088 kb
Host smart-902c0910-d1b9-4209-b5c5-56fb560bf41e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925028319 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 19.keymgr_dpe_shadow_reg_errors_with_csr_rw.925028319
Directory /workspace/19.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_tl_errors.3452996432
Short name T256
Test name
Test status
Simulation time 989025366 ps
CPU time 3.16 seconds
Started Mar 02 01:20:29 PM PST 24
Finished Mar 02 01:20:32 PM PST 24
Peak memory 212712 kb
Host smart-1979525d-a97b-4b83-a5c5-50d2bbdb3ab8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452996432 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_tl_errors.
3452996432
Directory /workspace/19.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_aliasing.118290543
Short name T184
Test name
Test status
Simulation time 852221727 ps
CPU time 5.68 seconds
Started Mar 02 01:19:58 PM PST 24
Finished Mar 02 01:20:05 PM PST 24
Peak memory 204472 kb
Host smart-096421c5-573b-49f0-9f11-ac3b15be5deb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118290543 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr
_aliasing.118290543
Directory /workspace/2.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_bit_bash.104665115
Short name T289
Test name
Test status
Simulation time 703480863 ps
CPU time 8.29 seconds
Started Mar 02 01:20:03 PM PST 24
Finished Mar 02 01:20:12 PM PST 24
Peak memory 204488 kb
Host smart-f003b9a3-8a41-4bfd-b46e-d67b9866f5ba
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104665115 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr
_bit_bash.104665115
Directory /workspace/2.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_hw_reset.2166985930
Short name T91
Test name
Test status
Simulation time 440447965 ps
CPU time 1.37 seconds
Started Mar 02 01:19:56 PM PST 24
Finished Mar 02 01:19:58 PM PST 24
Peak memory 204568 kb
Host smart-d43df542-7372-4388-be58-544da4c540fa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166985930 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_cs
r_hw_reset.2166985930
Directory /workspace/2.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_mem_rw_with_rand_reset.1538561231
Short name T300
Test name
Test status
Simulation time 22415740 ps
CPU time 1.4 seconds
Started Mar 02 01:19:57 PM PST 24
Finished Mar 02 01:19:58 PM PST 24
Peak memory 204564 kb
Host smart-f0fb42fd-c25d-4bef-a529-fdecedbe6af0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538561231 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr_mem_rw_with_rand_reset.1538561231
Directory /workspace/2.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_rw.1109590490
Short name T297
Test name
Test status
Simulation time 46487274 ps
CPU time 1.05 seconds
Started Mar 02 01:19:48 PM PST 24
Finished Mar 02 01:19:50 PM PST 24
Peak memory 204480 kb
Host smart-0bdcb306-aab4-4198-b97a-2b9460a7a21a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109590490 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr_rw.1
109590490
Directory /workspace/2.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_intr_test.2506021883
Short name T230
Test name
Test status
Simulation time 11300625 ps
CPU time 0.77 seconds
Started Mar 02 01:19:53 PM PST 24
Finished Mar 02 01:19:56 PM PST 24
Peak memory 204284 kb
Host smart-d50d7d28-1c36-43fd-84d5-b4da614941a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506021883 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_intr_test.2
506021883
Directory /workspace/2.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_same_csr_outstanding.2405172571
Short name T185
Test name
Test status
Simulation time 74948102 ps
CPU time 2.26 seconds
Started Mar 02 01:20:04 PM PST 24
Finished Mar 02 01:20:06 PM PST 24
Peak memory 204436 kb
Host smart-00c09ce5-01cd-4580-aa31-01302f19df31
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405172571 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.k
eymgr_dpe_same_csr_outstanding.2405172571
Directory /workspace/2.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_shadow_reg_errors.279207669
Short name T270
Test name
Test status
Simulation time 67322115 ps
CPU time 2.24 seconds
Started Mar 02 01:19:53 PM PST 24
Finished Mar 02 01:19:57 PM PST 24
Peak memory 213052 kb
Host smart-1b21c7f7-570f-4273-a90c-0d79e743d4ac
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279207669 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymg
r_dpe_shadow_reg_errors.279207669
Directory /workspace/2.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_shadow_reg_errors_with_csr_rw.2445155198
Short name T75
Test name
Test status
Simulation time 261938756 ps
CPU time 7.85 seconds
Started Mar 02 01:19:54 PM PST 24
Finished Mar 02 01:20:04 PM PST 24
Peak memory 213048 kb
Host smart-b0113a1b-b92d-448e-ae7b-07498adcd192
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445155198 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.keymgr_dpe_shadow_reg_errors_with_csr_rw.2445155198
Directory /workspace/2.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_tl_errors.2672576531
Short name T271
Test name
Test status
Simulation time 28820394 ps
CPU time 2.06 seconds
Started Mar 02 01:19:56 PM PST 24
Finished Mar 02 01:19:59 PM PST 24
Peak memory 220836 kb
Host smart-cc67dd9b-9563-437d-9c87-f1506995e8de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672576531 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_tl_errors.2
672576531
Directory /workspace/2.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_dpe_intr_test.3887127235
Short name T276
Test name
Test status
Simulation time 9059361 ps
CPU time 0.75 seconds
Started Mar 02 01:20:30 PM PST 24
Finished Mar 02 01:20:30 PM PST 24
Peak memory 204316 kb
Host smart-ac8c375b-7abd-4be8-b9a5-b59df5e0a428
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887127235 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_intr_test.
3887127235
Directory /workspace/20.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_dpe_intr_test.2184249080
Short name T279
Test name
Test status
Simulation time 18406377 ps
CPU time 0.73 seconds
Started Mar 02 01:20:39 PM PST 24
Finished Mar 02 01:20:40 PM PST 24
Peak memory 204232 kb
Host smart-4f5a36c5-f72e-4bc9-b46a-14ef76f4ee98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184249080 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_intr_test.
2184249080
Directory /workspace/21.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_dpe_intr_test.175593952
Short name T189
Test name
Test status
Simulation time 37372142 ps
CPU time 0.8 seconds
Started Mar 02 01:20:35 PM PST 24
Finished Mar 02 01:20:35 PM PST 24
Peak memory 204264 kb
Host smart-65fc2852-e59b-412f-b0b7-2f170421bb75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175593952 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_intr_test.175593952
Directory /workspace/22.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_dpe_intr_test.3867441393
Short name T253
Test name
Test status
Simulation time 61662113 ps
CPU time 0.89 seconds
Started Mar 02 01:20:30 PM PST 24
Finished Mar 02 01:20:31 PM PST 24
Peak memory 204316 kb
Host smart-72c79e76-0c4d-4daf-8a8c-ef0c7d54dbe4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867441393 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_intr_test.
3867441393
Directory /workspace/23.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_dpe_intr_test.3095711245
Short name T284
Test name
Test status
Simulation time 8742684 ps
CPU time 0.76 seconds
Started Mar 02 01:20:46 PM PST 24
Finished Mar 02 01:20:47 PM PST 24
Peak memory 204288 kb
Host smart-d79e7368-4f68-4c6a-a086-28979ec879d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095711245 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_intr_test.
3095711245
Directory /workspace/24.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_dpe_intr_test.666082660
Short name T299
Test name
Test status
Simulation time 23460630 ps
CPU time 0.75 seconds
Started Mar 02 01:20:30 PM PST 24
Finished Mar 02 01:20:31 PM PST 24
Peak memory 204320 kb
Host smart-4106ada6-8a47-4eff-83ad-b959d73a6dde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666082660 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_intr_test.666082660
Directory /workspace/25.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_dpe_intr_test.2669838792
Short name T224
Test name
Test status
Simulation time 42963240 ps
CPU time 0.86 seconds
Started Mar 02 01:20:33 PM PST 24
Finished Mar 02 01:20:34 PM PST 24
Peak memory 204268 kb
Host smart-fec0be78-b7e5-4a21-8f37-e0d33f811c18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669838792 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_intr_test.
2669838792
Directory /workspace/26.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_dpe_intr_test.4091715605
Short name T229
Test name
Test status
Simulation time 20478365 ps
CPU time 0.87 seconds
Started Mar 02 01:20:32 PM PST 24
Finished Mar 02 01:20:33 PM PST 24
Peak memory 204268 kb
Host smart-930957b6-50ab-4aba-a0cb-0a5fe8caf975
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091715605 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_intr_test.
4091715605
Directory /workspace/27.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_dpe_intr_test.3103681291
Short name T176
Test name
Test status
Simulation time 31278205 ps
CPU time 0.72 seconds
Started Mar 02 01:20:31 PM PST 24
Finished Mar 02 01:20:32 PM PST 24
Peak memory 204292 kb
Host smart-709209f1-47bd-48e3-8778-459b3421378c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103681291 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_intr_test.
3103681291
Directory /workspace/29.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_aliasing.4029429165
Short name T278
Test name
Test status
Simulation time 178290290 ps
CPU time 2.83 seconds
Started Mar 02 01:19:59 PM PST 24
Finished Mar 02 01:20:05 PM PST 24
Peak memory 204436 kb
Host smart-a172a35f-72b7-4cd1-858d-a1b6d75949a3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029429165 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_cs
r_aliasing.4029429165
Directory /workspace/3.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_bit_bash.4027135038
Short name T307
Test name
Test status
Simulation time 171895101 ps
CPU time 10.06 seconds
Started Mar 02 01:20:03 PM PST 24
Finished Mar 02 01:20:13 PM PST 24
Peak memory 204480 kb
Host smart-69c8d300-bb70-4625-b09c-9a1bcb16bf7e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027135038 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_cs
r_bit_bash.4027135038
Directory /workspace/3.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_hw_reset.3841089481
Short name T223
Test name
Test status
Simulation time 100409129 ps
CPU time 1.34 seconds
Started Mar 02 01:19:57 PM PST 24
Finished Mar 02 01:19:58 PM PST 24
Peak memory 204408 kb
Host smart-d84c01b0-04b4-4bd6-ae72-018096d74c03
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841089481 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_cs
r_hw_reset.3841089481
Directory /workspace/3.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_mem_rw_with_rand_reset.731993095
Short name T304
Test name
Test status
Simulation time 19801452 ps
CPU time 1.21 seconds
Started Mar 02 01:20:04 PM PST 24
Finished Mar 02 01:20:06 PM PST 24
Peak memory 204544 kb
Host smart-bc80e0cb-a6a8-4869-8b35-58c0d0bd9d00
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731993095 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_csr_mem_rw_with_rand_reset.731993095
Directory /workspace/3.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_rw.2476126309
Short name T70
Test name
Test status
Simulation time 67633930 ps
CPU time 0.92 seconds
Started Mar 02 01:19:58 PM PST 24
Finished Mar 02 01:20:02 PM PST 24
Peak memory 204324 kb
Host smart-3eb8ef4f-fb76-42a1-a2ca-871fb6a364c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476126309 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_csr_rw.2
476126309
Directory /workspace/3.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_intr_test.1460825188
Short name T72
Test name
Test status
Simulation time 25329399 ps
CPU time 0.68 seconds
Started Mar 02 01:19:58 PM PST 24
Finished Mar 02 01:20:01 PM PST 24
Peak memory 204260 kb
Host smart-3a322bae-fe60-4787-ad02-b59b6a28c4be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460825188 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_intr_test.1
460825188
Directory /workspace/3.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_same_csr_outstanding.2518581508
Short name T76
Test name
Test status
Simulation time 66017689 ps
CPU time 1.4 seconds
Started Mar 02 01:19:56 PM PST 24
Finished Mar 02 01:19:58 PM PST 24
Peak memory 204456 kb
Host smart-faf93fe7-e210-4aed-b046-052d6ce5c825
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518581508 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.k
eymgr_dpe_same_csr_outstanding.2518581508
Directory /workspace/3.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_shadow_reg_errors.3660103800
Short name T178
Test name
Test status
Simulation time 166321191 ps
CPU time 2 seconds
Started Mar 02 01:20:03 PM PST 24
Finished Mar 02 01:20:05 PM PST 24
Peak memory 213036 kb
Host smart-513a77be-5e10-4e05-abdb-15ff0f5448fc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660103800 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keym
gr_dpe_shadow_reg_errors.3660103800
Directory /workspace/3.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_tl_errors.3899461100
Short name T23
Test name
Test status
Simulation time 110886793 ps
CPU time 3.93 seconds
Started Mar 02 01:19:56 PM PST 24
Finished Mar 02 01:20:01 PM PST 24
Peak memory 212704 kb
Host smart-806481f7-c4cf-4499-89ab-28a00a13f16e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899461100 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_tl_errors.3
899461100
Directory /workspace/3.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_dpe_intr_test.959367619
Short name T259
Test name
Test status
Simulation time 53998278 ps
CPU time 0.75 seconds
Started Mar 02 01:20:48 PM PST 24
Finished Mar 02 01:20:49 PM PST 24
Peak memory 204248 kb
Host smart-bfd5ad16-7462-46e9-a8c2-aa51541fa020
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959367619 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_intr_test.959367619
Directory /workspace/30.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_dpe_intr_test.3701097585
Short name T252
Test name
Test status
Simulation time 42735413 ps
CPU time 0.83 seconds
Started Mar 02 01:20:47 PM PST 24
Finished Mar 02 01:20:48 PM PST 24
Peak memory 204268 kb
Host smart-f24a43be-33e7-448f-85df-fcc34b0eac35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701097585 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_intr_test.
3701097585
Directory /workspace/31.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_dpe_intr_test.3138158636
Short name T190
Test name
Test status
Simulation time 16510807 ps
CPU time 0.86 seconds
Started Mar 02 01:20:43 PM PST 24
Finished Mar 02 01:20:44 PM PST 24
Peak memory 204348 kb
Host smart-860076ba-d222-4dc8-9151-2e273ee875eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138158636 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_intr_test.
3138158636
Directory /workspace/32.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_dpe_intr_test.3650781266
Short name T247
Test name
Test status
Simulation time 28922632 ps
CPU time 0.89 seconds
Started Mar 02 01:20:47 PM PST 24
Finished Mar 02 01:20:48 PM PST 24
Peak memory 204516 kb
Host smart-f693c939-5472-4127-8627-c46861c76e0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650781266 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_intr_test.
3650781266
Directory /workspace/33.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_dpe_intr_test.3444881341
Short name T212
Test name
Test status
Simulation time 35423228 ps
CPU time 0.81 seconds
Started Mar 02 01:20:43 PM PST 24
Finished Mar 02 01:20:44 PM PST 24
Peak memory 204272 kb
Host smart-a91d5450-8950-482e-b9c3-cb50871a5f66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444881341 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_intr_test.
3444881341
Directory /workspace/34.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_dpe_intr_test.1632646614
Short name T287
Test name
Test status
Simulation time 52324993 ps
CPU time 0.86 seconds
Started Mar 02 01:20:43 PM PST 24
Finished Mar 02 01:20:44 PM PST 24
Peak memory 204312 kb
Host smart-809d8358-a1dc-403c-a478-32eea73baddb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632646614 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_intr_test.
1632646614
Directory /workspace/35.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_dpe_intr_test.2823632347
Short name T306
Test name
Test status
Simulation time 31910798 ps
CPU time 0.74 seconds
Started Mar 02 01:20:43 PM PST 24
Finished Mar 02 01:20:44 PM PST 24
Peak memory 204164 kb
Host smart-9c91f36e-f498-49e1-ae64-5d3cf580110e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823632347 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_intr_test.
2823632347
Directory /workspace/36.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_dpe_intr_test.2055533142
Short name T255
Test name
Test status
Simulation time 27319841 ps
CPU time 0.87 seconds
Started Mar 02 01:20:43 PM PST 24
Finished Mar 02 01:20:44 PM PST 24
Peak memory 204272 kb
Host smart-22334288-6394-43f8-ba14-931508cdaa39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055533142 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_intr_test.
2055533142
Directory /workspace/37.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_dpe_intr_test.3945940530
Short name T232
Test name
Test status
Simulation time 16888629 ps
CPU time 0.76 seconds
Started Mar 02 01:20:41 PM PST 24
Finished Mar 02 01:20:42 PM PST 24
Peak memory 204244 kb
Host smart-1ddccfb6-78aa-47bb-b91d-7fe1c436b586
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945940530 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_intr_test.
3945940530
Directory /workspace/38.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_dpe_intr_test.2965388957
Short name T282
Test name
Test status
Simulation time 40233770 ps
CPU time 0.71 seconds
Started Mar 02 01:20:41 PM PST 24
Finished Mar 02 01:20:42 PM PST 24
Peak memory 204256 kb
Host smart-958ad531-8f96-4bb9-8ff2-aabf20278151
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965388957 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_intr_test.
2965388957
Directory /workspace/39.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_aliasing.3591550594
Short name T221
Test name
Test status
Simulation time 221948524 ps
CPU time 8.08 seconds
Started Mar 02 01:20:03 PM PST 24
Finished Mar 02 01:20:11 PM PST 24
Peak memory 204404 kb
Host smart-839f94a3-a035-48e2-9356-4cd41ebcbe6e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591550594 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_cs
r_aliasing.3591550594
Directory /workspace/4.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_bit_bash.3466974975
Short name T73
Test name
Test status
Simulation time 3074673710 ps
CPU time 12.35 seconds
Started Mar 02 01:20:03 PM PST 24
Finished Mar 02 01:20:15 PM PST 24
Peak memory 204424 kb
Host smart-c2788ccd-abb0-45cd-b1be-a355532b944f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466974975 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_cs
r_bit_bash.3466974975
Directory /workspace/4.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_hw_reset.2197593711
Short name T302
Test name
Test status
Simulation time 24364940 ps
CPU time 1.03 seconds
Started Mar 02 01:19:56 PM PST 24
Finished Mar 02 01:19:58 PM PST 24
Peak memory 204280 kb
Host smart-b8103b78-df55-4c0b-b26f-fddf96329a64
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197593711 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_cs
r_hw_reset.2197593711
Directory /workspace/4.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_mem_rw_with_rand_reset.1520646745
Short name T63
Test name
Test status
Simulation time 23896793 ps
CPU time 1.05 seconds
Started Mar 02 01:20:01 PM PST 24
Finished Mar 02 01:20:04 PM PST 24
Peak memory 204272 kb
Host smart-dd6f8ba3-52a9-4b80-99d2-97021b1d7b46
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520646745 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_csr_mem_rw_with_rand_reset.1520646745
Directory /workspace/4.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_rw.1831893663
Short name T67
Test name
Test status
Simulation time 47222469 ps
CPU time 1.01 seconds
Started Mar 02 01:19:57 PM PST 24
Finished Mar 02 01:19:59 PM PST 24
Peak memory 204268 kb
Host smart-5a644711-3d47-4116-9b88-0d23d1ab5151
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831893663 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_csr_rw.1
831893663
Directory /workspace/4.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_intr_test.1470526763
Short name T292
Test name
Test status
Simulation time 8081102 ps
CPU time 0.77 seconds
Started Mar 02 01:19:59 PM PST 24
Finished Mar 02 01:20:03 PM PST 24
Peak memory 204276 kb
Host smart-38dcb1e5-7a85-421e-b6b7-3e0bd8c1299c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470526763 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_intr_test.1
470526763
Directory /workspace/4.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_same_csr_outstanding.1107687465
Short name T273
Test name
Test status
Simulation time 443361092 ps
CPU time 3.67 seconds
Started Mar 02 01:19:58 PM PST 24
Finished Mar 02 01:20:04 PM PST 24
Peak memory 212628 kb
Host smart-4811e518-63a8-434f-95ef-246e3f0a222d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107687465 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.k
eymgr_dpe_same_csr_outstanding.1107687465
Directory /workspace/4.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_shadow_reg_errors.595848648
Short name T286
Test name
Test status
Simulation time 79409487 ps
CPU time 1.36 seconds
Started Mar 02 01:19:59 PM PST 24
Finished Mar 02 01:20:02 PM PST 24
Peak memory 213028 kb
Host smart-2908ffa7-b0db-4c5b-a0a3-3e10312cc003
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595848648 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymg
r_dpe_shadow_reg_errors.595848648
Directory /workspace/4.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_shadow_reg_errors_with_csr_rw.3378022548
Short name T34
Test name
Test status
Simulation time 97140656 ps
CPU time 3.03 seconds
Started Mar 02 01:19:59 PM PST 24
Finished Mar 02 01:20:04 PM PST 24
Peak memory 213172 kb
Host smart-c7bc0dcb-8a72-4e63-9462-8bd18dedaeb1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378022548 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.keymgr_dpe_shadow_reg_errors_with_csr_rw.3378022548
Directory /workspace/4.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_tl_errors.811384849
Short name T246
Test name
Test status
Simulation time 162755904 ps
CPU time 1.84 seconds
Started Mar 02 01:19:56 PM PST 24
Finished Mar 02 01:19:59 PM PST 24
Peak memory 212716 kb
Host smart-74fb17e5-8bbc-47da-894f-a32e4c7532d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811384849 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_tl_errors.811384849
Directory /workspace/4.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_dpe_intr_test.3960814097
Short name T245
Test name
Test status
Simulation time 37227956 ps
CPU time 0.74 seconds
Started Mar 02 01:20:44 PM PST 24
Finished Mar 02 01:20:44 PM PST 24
Peak memory 204332 kb
Host smart-774274f8-642c-44bf-8b70-120f14716ed9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960814097 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_intr_test.
3960814097
Directory /workspace/40.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_dpe_intr_test.4268269430
Short name T187
Test name
Test status
Simulation time 50637041 ps
CPU time 0.89 seconds
Started Mar 02 01:20:42 PM PST 24
Finished Mar 02 01:20:43 PM PST 24
Peak memory 204436 kb
Host smart-b5989a43-de1b-4f25-8055-beddd19ee005
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268269430 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_intr_test.
4268269430
Directory /workspace/41.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_dpe_intr_test.2001038637
Short name T281
Test name
Test status
Simulation time 13852799 ps
CPU time 0.9 seconds
Started Mar 02 01:20:46 PM PST 24
Finished Mar 02 01:20:47 PM PST 24
Peak memory 204328 kb
Host smart-20c38158-09d5-4bdc-91cb-9f6d3a619264
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001038637 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_intr_test.
2001038637
Directory /workspace/42.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_dpe_intr_test.1206619296
Short name T201
Test name
Test status
Simulation time 10491340 ps
CPU time 0.73 seconds
Started Mar 02 01:20:45 PM PST 24
Finished Mar 02 01:20:46 PM PST 24
Peak memory 204304 kb
Host smart-5241675d-b1b0-4f5e-873c-d83e6ad07b88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206619296 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_intr_test.
1206619296
Directory /workspace/43.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_dpe_intr_test.3100088968
Short name T225
Test name
Test status
Simulation time 28848932 ps
CPU time 0.89 seconds
Started Mar 02 01:20:44 PM PST 24
Finished Mar 02 01:20:45 PM PST 24
Peak memory 204260 kb
Host smart-8e9d2caa-5d4f-464d-96ef-d79c9001a4ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100088968 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_intr_test.
3100088968
Directory /workspace/44.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_dpe_intr_test.1252596199
Short name T298
Test name
Test status
Simulation time 12301554 ps
CPU time 0.77 seconds
Started Mar 02 01:20:51 PM PST 24
Finished Mar 02 01:20:52 PM PST 24
Peak memory 204228 kb
Host smart-0e088349-c6e2-4344-bd0c-9d458d1e8e86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252596199 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_intr_test.
1252596199
Directory /workspace/45.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_dpe_intr_test.2954961063
Short name T41
Test name
Test status
Simulation time 17014449 ps
CPU time 0.78 seconds
Started Mar 02 01:20:46 PM PST 24
Finished Mar 02 01:20:47 PM PST 24
Peak memory 204328 kb
Host smart-a3a17f3a-1d91-463e-bc22-0ef183fd1bce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954961063 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_intr_test.
2954961063
Directory /workspace/46.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_dpe_intr_test.845461603
Short name T96
Test name
Test status
Simulation time 19811607 ps
CPU time 0.98 seconds
Started Mar 02 01:20:49 PM PST 24
Finished Mar 02 01:20:50 PM PST 24
Peak memory 204404 kb
Host smart-e2aa7dec-35c0-4b1e-8e00-c6dd155fba23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845461603 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_intr_test.845461603
Directory /workspace/47.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_dpe_intr_test.965969452
Short name T285
Test name
Test status
Simulation time 14467373 ps
CPU time 0.86 seconds
Started Mar 02 01:20:49 PM PST 24
Finished Mar 02 01:20:50 PM PST 24
Peak memory 204208 kb
Host smart-5ee5c9cc-c731-4bcc-b26a-1c468d13d489
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965969452 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_intr_test.965969452
Directory /workspace/48.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_dpe_intr_test.2478315237
Short name T266
Test name
Test status
Simulation time 39089403 ps
CPU time 0.74 seconds
Started Mar 02 01:20:43 PM PST 24
Finished Mar 02 01:20:44 PM PST 24
Peak memory 204272 kb
Host smart-bd5f2307-d35c-4d8f-ab5a-d118e095d953
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478315237 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_intr_test.
2478315237
Directory /workspace/49.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_csr_mem_rw_with_rand_reset.845136710
Short name T236
Test name
Test status
Simulation time 133919602 ps
CPU time 1 seconds
Started Mar 02 01:19:58 PM PST 24
Finished Mar 02 01:20:00 PM PST 24
Peak memory 204432 kb
Host smart-2d2f0b95-f75a-4367-b317-789fe3e7dcd2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845136710 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_csr_mem_rw_with_rand_reset.845136710
Directory /workspace/5.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_csr_rw.776902990
Short name T275
Test name
Test status
Simulation time 12363519 ps
CPU time 0.88 seconds
Started Mar 02 01:20:04 PM PST 24
Finished Mar 02 01:20:05 PM PST 24
Peak memory 204256 kb
Host smart-27cd4199-4ebc-4d06-a1cc-1db63ec7cc31
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776902990 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_csr_rw.776902990
Directory /workspace/5.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_intr_test.2596897895
Short name T180
Test name
Test status
Simulation time 9653536 ps
CPU time 0.69 seconds
Started Mar 02 01:19:57 PM PST 24
Finished Mar 02 01:19:58 PM PST 24
Peak memory 204272 kb
Host smart-032819d2-c55f-4cab-aeec-658b38f6b5e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596897895 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_intr_test.2
596897895
Directory /workspace/5.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_same_csr_outstanding.2422963498
Short name T244
Test name
Test status
Simulation time 77220803 ps
CPU time 2.11 seconds
Started Mar 02 01:20:00 PM PST 24
Finished Mar 02 01:20:04 PM PST 24
Peak memory 204480 kb
Host smart-ac9e5893-262f-46d9-9815-42e515de84f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422963498 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.k
eymgr_dpe_same_csr_outstanding.2422963498
Directory /workspace/5.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_shadow_reg_errors.625940790
Short name T269
Test name
Test status
Simulation time 362799260 ps
CPU time 1.62 seconds
Started Mar 02 01:20:03 PM PST 24
Finished Mar 02 01:20:05 PM PST 24
Peak memory 213032 kb
Host smart-a542ea86-188a-4e0e-85d5-87323cc44257
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625940790 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymg
r_dpe_shadow_reg_errors.625940790
Directory /workspace/5.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_shadow_reg_errors_with_csr_rw.3854055607
Short name T203
Test name
Test status
Simulation time 206685579 ps
CPU time 6.12 seconds
Started Mar 02 01:19:58 PM PST 24
Finished Mar 02 01:20:07 PM PST 24
Peak memory 213052 kb
Host smart-19197bc9-f1da-453b-9a7b-7a64c365a1e0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854055607 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.keymgr_dpe_shadow_reg_errors_with_csr_rw.3854055607
Directory /workspace/5.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_tl_errors.2627641495
Short name T21
Test name
Test status
Simulation time 268644720 ps
CPU time 1.92 seconds
Started Mar 02 01:19:59 PM PST 24
Finished Mar 02 01:20:04 PM PST 24
Peak memory 212664 kb
Host smart-82f3089c-f1ba-48bb-ad3d-974de0a694ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627641495 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_tl_errors.2
627641495
Directory /workspace/5.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_tl_intg_err.1293852666
Short name T112
Test name
Test status
Simulation time 144488741 ps
CPU time 3.01 seconds
Started Mar 02 01:20:01 PM PST 24
Finished Mar 02 01:20:06 PM PST 24
Peak memory 212712 kb
Host smart-37309cc4-63a9-44f5-8153-a337e387c0a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293852666 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe
_tl_intg_err.1293852666
Directory /workspace/5.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_csr_mem_rw_with_rand_reset.984321409
Short name T234
Test name
Test status
Simulation time 110362724 ps
CPU time 1.08 seconds
Started Mar 02 01:20:06 PM PST 24
Finished Mar 02 01:20:07 PM PST 24
Peak memory 204520 kb
Host smart-70b259b7-dc28-45e0-b3c2-adbf298a5ddf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984321409 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_csr_mem_rw_with_rand_reset.984321409
Directory /workspace/6.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_csr_rw.394169795
Short name T211
Test name
Test status
Simulation time 31120728 ps
CPU time 0.89 seconds
Started Mar 02 01:20:13 PM PST 24
Finished Mar 02 01:20:14 PM PST 24
Peak memory 204288 kb
Host smart-e6b425d8-3a44-4eaa-9bec-40f09196b8a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394169795 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_csr_rw.394169795
Directory /workspace/6.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_intr_test.1875882605
Short name T214
Test name
Test status
Simulation time 111899257 ps
CPU time 0.8 seconds
Started Mar 02 01:20:07 PM PST 24
Finished Mar 02 01:20:08 PM PST 24
Peak memory 204360 kb
Host smart-67cfa8b0-5bbe-4bf1-811b-d7c7e2420259
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875882605 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_intr_test.1
875882605
Directory /workspace/6.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_same_csr_outstanding.9888274
Short name T263
Test name
Test status
Simulation time 30626348 ps
CPU time 2.16 seconds
Started Mar 02 01:20:05 PM PST 24
Finished Mar 02 01:20:07 PM PST 24
Peak memory 204360 kb
Host smart-adab814a-58b8-4c68-9caf-dbf0f7c91e8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9888274 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keym
gr_dpe_same_csr_outstanding.9888274
Directory /workspace/6.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_shadow_reg_errors.1592384307
Short name T267
Test name
Test status
Simulation time 72690183 ps
CPU time 2.09 seconds
Started Mar 02 01:19:58 PM PST 24
Finished Mar 02 01:20:03 PM PST 24
Peak memory 213104 kb
Host smart-a80df45c-715b-436f-b0d9-27c48b3e28f7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592384307 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keym
gr_dpe_shadow_reg_errors.1592384307
Directory /workspace/6.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_shadow_reg_errors_with_csr_rw.3476419577
Short name T175
Test name
Test status
Simulation time 380670290 ps
CPU time 4.74 seconds
Started Mar 02 01:20:03 PM PST 24
Finished Mar 02 01:20:08 PM PST 24
Peak memory 213036 kb
Host smart-9a64ec9a-f189-4e07-acb4-0e9185b32277
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476419577 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 6.keymgr_dpe_shadow_reg_errors_with_csr_rw.3476419577
Directory /workspace/6.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_tl_errors.1135787048
Short name T240
Test name
Test status
Simulation time 195617556 ps
CPU time 2.82 seconds
Started Mar 02 01:19:58 PM PST 24
Finished Mar 02 01:20:03 PM PST 24
Peak memory 220456 kb
Host smart-88c06456-8b26-400a-b76a-9deaa085dc3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135787048 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_tl_errors.1
135787048
Directory /workspace/6.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_csr_mem_rw_with_rand_reset.571340982
Short name T296
Test name
Test status
Simulation time 22037533 ps
CPU time 0.94 seconds
Started Mar 02 01:20:04 PM PST 24
Finished Mar 02 01:20:06 PM PST 24
Peak memory 204376 kb
Host smart-89c4e2ec-a054-48ac-8fd6-705958ad8836
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571340982 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_csr_mem_rw_with_rand_reset.571340982
Directory /workspace/7.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_csr_rw.1984036012
Short name T191
Test name
Test status
Simulation time 25943345 ps
CPU time 1.04 seconds
Started Mar 02 01:20:06 PM PST 24
Finished Mar 02 01:20:07 PM PST 24
Peak memory 204360 kb
Host smart-91e911cf-0c1d-4375-8847-04d8cf2886e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984036012 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_csr_rw.1
984036012
Directory /workspace/7.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_intr_test.1283813035
Short name T210
Test name
Test status
Simulation time 34446876 ps
CPU time 0.68 seconds
Started Mar 02 01:20:06 PM PST 24
Finished Mar 02 01:20:07 PM PST 24
Peak memory 204316 kb
Host smart-c239cd42-4070-4ec1-bb7f-cf354aa3fbf8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283813035 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_intr_test.1
283813035
Directory /workspace/7.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_same_csr_outstanding.1962022136
Short name T262
Test name
Test status
Simulation time 19656032 ps
CPU time 1.44 seconds
Started Mar 02 01:20:08 PM PST 24
Finished Mar 02 01:20:10 PM PST 24
Peak memory 204468 kb
Host smart-5399042d-5ef9-4a15-a84d-537ff80a7c0c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962022136 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.k
eymgr_dpe_same_csr_outstanding.1962022136
Directory /workspace/7.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_shadow_reg_errors.876252856
Short name T170
Test name
Test status
Simulation time 150776982 ps
CPU time 2.1 seconds
Started Mar 02 01:20:06 PM PST 24
Finished Mar 02 01:20:09 PM PST 24
Peak memory 213064 kb
Host smart-31130afe-9acc-4dbd-99fa-ce3f578c4351
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876252856 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymg
r_dpe_shadow_reg_errors.876252856
Directory /workspace/7.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_shadow_reg_errors_with_csr_rw.2688223851
Short name T33
Test name
Test status
Simulation time 237960622 ps
CPU time 2.65 seconds
Started Mar 02 01:20:05 PM PST 24
Finished Mar 02 01:20:08 PM PST 24
Peak memory 213156 kb
Host smart-e4997808-7fd6-4081-8909-eafa93629257
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688223851 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.keymgr_dpe_shadow_reg_errors_with_csr_rw.2688223851
Directory /workspace/7.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_errors.842542132
Short name T288
Test name
Test status
Simulation time 50139490 ps
CPU time 2.17 seconds
Started Mar 02 01:20:06 PM PST 24
Finished Mar 02 01:20:09 PM PST 24
Peak memory 212696 kb
Host smart-699e7f2f-f038-4fb3-939f-dee7c68cafdd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842542132 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_tl_errors.842542132
Directory /workspace/7.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_csr_mem_rw_with_rand_reset.622870084
Short name T291
Test name
Test status
Simulation time 25501674 ps
CPU time 1.31 seconds
Started Mar 02 01:20:06 PM PST 24
Finished Mar 02 01:20:08 PM PST 24
Peak memory 220220 kb
Host smart-f6419028-b9f4-4263-a06a-2ade32653800
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622870084 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_csr_mem_rw_with_rand_reset.622870084
Directory /workspace/8.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_csr_rw.3068713840
Short name T222
Test name
Test status
Simulation time 12460413 ps
CPU time 1.08 seconds
Started Mar 02 01:20:10 PM PST 24
Finished Mar 02 01:20:11 PM PST 24
Peak memory 204416 kb
Host smart-3d9168c3-c07d-41ad-8d14-f15aaa49e761
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068713840 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_csr_rw.3
068713840
Directory /workspace/8.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_intr_test.3236972253
Short name T196
Test name
Test status
Simulation time 29527325 ps
CPU time 0.69 seconds
Started Mar 02 01:20:04 PM PST 24
Finished Mar 02 01:20:05 PM PST 24
Peak memory 204216 kb
Host smart-ecf1fdcb-4a41-4aa8-852a-33d4a831773d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236972253 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_intr_test.3
236972253
Directory /workspace/8.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_same_csr_outstanding.754694073
Short name T186
Test name
Test status
Simulation time 75767149 ps
CPU time 1.27 seconds
Started Mar 02 01:20:04 PM PST 24
Finished Mar 02 01:20:05 PM PST 24
Peak memory 204472 kb
Host smart-d5032188-42e8-490a-a5f4-ab7f723d395f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754694073 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.ke
ymgr_dpe_same_csr_outstanding.754694073
Directory /workspace/8.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_shadow_reg_errors.1490865258
Short name T94
Test name
Test status
Simulation time 95280568 ps
CPU time 2.16 seconds
Started Mar 02 01:20:06 PM PST 24
Finished Mar 02 01:20:09 PM PST 24
Peak memory 213084 kb
Host smart-e5b07cd6-cbb3-4d96-834e-51e0812b95a0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490865258 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keym
gr_dpe_shadow_reg_errors.1490865258
Directory /workspace/8.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_shadow_reg_errors_with_csr_rw.3530607496
Short name T217
Test name
Test status
Simulation time 145146986 ps
CPU time 3.28 seconds
Started Mar 02 01:20:09 PM PST 24
Finished Mar 02 01:20:13 PM PST 24
Peak memory 213056 kb
Host smart-ed450965-7e2d-494e-8639-ef39e1fe5ba1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530607496 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.keymgr_dpe_shadow_reg_errors_with_csr_rw.3530607496
Directory /workspace/8.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_tl_errors.136754554
Short name T260
Test name
Test status
Simulation time 117908050 ps
CPU time 1.97 seconds
Started Mar 02 01:20:06 PM PST 24
Finished Mar 02 01:20:08 PM PST 24
Peak memory 215768 kb
Host smart-92ba7311-cd7a-4bc6-b933-b99672e50b21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136754554 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_tl_errors.136754554
Directory /workspace/8.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_tl_intg_err.471351970
Short name T237
Test name
Test status
Simulation time 451612677 ps
CPU time 3.1 seconds
Started Mar 02 01:20:07 PM PST 24
Finished Mar 02 01:20:10 PM PST 24
Peak memory 212700 kb
Host smart-d9fdfd17-a8ed-479d-af52-c789ed62afe6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471351970 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_
tl_intg_err.471351970
Directory /workspace/8.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_csr_mem_rw_with_rand_reset.1334020830
Short name T202
Test name
Test status
Simulation time 99242042 ps
CPU time 1.6 seconds
Started Mar 02 01:20:07 PM PST 24
Finished Mar 02 01:20:09 PM PST 24
Peak memory 220768 kb
Host smart-3829b675-bcf2-4f81-af79-1747903971e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334020830 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_csr_mem_rw_with_rand_reset.1334020830
Directory /workspace/9.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_csr_rw.36708405
Short name T305
Test name
Test status
Simulation time 89544443 ps
CPU time 1.15 seconds
Started Mar 02 01:20:10 PM PST 24
Finished Mar 02 01:20:11 PM PST 24
Peak memory 204476 kb
Host smart-dbdbfb6d-f2b9-416d-996c-48d2c56a4335
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36708405 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_csr_rw.36708405
Directory /workspace/9.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_intr_test.1937377104
Short name T308
Test name
Test status
Simulation time 8540853 ps
CPU time 0.74 seconds
Started Mar 02 01:20:05 PM PST 24
Finished Mar 02 01:20:06 PM PST 24
Peak memory 204340 kb
Host smart-afd778a2-4b10-4e6d-9ba7-f526b57b40ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937377104 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_intr_test.1
937377104
Directory /workspace/9.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_same_csr_outstanding.1456570266
Short name T216
Test name
Test status
Simulation time 396320562 ps
CPU time 1.25 seconds
Started Mar 02 01:20:10 PM PST 24
Finished Mar 02 01:20:11 PM PST 24
Peak memory 204476 kb
Host smart-456e9377-b519-4d04-b386-dbd460b2e91a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456570266 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.k
eymgr_dpe_same_csr_outstanding.1456570266
Directory /workspace/9.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_shadow_reg_errors.4026275049
Short name T264
Test name
Test status
Simulation time 138144777 ps
CPU time 3.77 seconds
Started Mar 02 01:20:09 PM PST 24
Finished Mar 02 01:20:12 PM PST 24
Peak memory 217308 kb
Host smart-91f74e4d-9541-4038-be83-4e64319f5ff6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026275049 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keym
gr_dpe_shadow_reg_errors.4026275049
Directory /workspace/9.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_shadow_reg_errors_with_csr_rw.3552953474
Short name T60
Test name
Test status
Simulation time 422982749 ps
CPU time 7.32 seconds
Started Mar 02 01:20:05 PM PST 24
Finished Mar 02 01:20:13 PM PST 24
Peak memory 218012 kb
Host smart-2da63d72-7b15-4884-9485-28afd07ef966
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552953474 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.keymgr_dpe_shadow_reg_errors_with_csr_rw.3552953474
Directory /workspace/9.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_tl_errors.2487654488
Short name T38
Test name
Test status
Simulation time 619066002 ps
CPU time 5.1 seconds
Started Mar 02 01:20:06 PM PST 24
Finished Mar 02 01:20:12 PM PST 24
Peak memory 212684 kb
Host smart-3a84c815-ca05-48c1-9aa5-2df7f6e93261
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487654488 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_tl_errors.2
487654488
Directory /workspace/9.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_tl_intg_err.1628809531
Short name T46
Test name
Test status
Simulation time 394460398 ps
CPU time 4.14 seconds
Started Mar 02 01:20:08 PM PST 24
Finished Mar 02 01:20:12 PM PST 24
Peak memory 213088 kb
Host smart-beabb587-45b4-4a46-8c68-67b2791d3ee5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628809531 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe
_tl_intg_err.1628809531
Directory /workspace/9.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_dpe_smoke.853291131
Short name T148
Test name
Test status
Simulation time 896775221 ps
CPU time 18.47 seconds
Started Mar 02 01:20:07 PM PST 24
Finished Mar 02 01:20:26 PM PST 24
Peak memory 207972 kb
Host smart-68608eaa-30ab-443e-936f-e8c786215269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853291131 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_smoke.853291131
Directory /workspace/0.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/1.keymgr_dpe_alert_test.324990604
Short name T151
Test name
Test status
Simulation time 53321382 ps
CPU time 0.79 seconds
Started Mar 02 01:20:15 PM PST 24
Finished Mar 02 01:20:16 PM PST 24
Peak memory 205268 kb
Host smart-afdcb663-2937-4887-85d2-02b839112268
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324990604 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_alert_test.324990604
Directory /workspace/1.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_dpe_sec_cm.3867686612
Short name T5
Test name
Test status
Simulation time 2680897947 ps
CPU time 9.08 seconds
Started Mar 02 01:20:25 PM PST 24
Finished Mar 02 01:20:34 PM PST 24
Peak memory 230332 kb
Host smart-20afe4f0-afdf-458b-a74f-2dc0149440e9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867686612 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_sec_cm.3867686612
Directory /workspace/1.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_dpe_smoke.2846149855
Short name T153
Test name
Test status
Simulation time 476106861 ps
CPU time 17.33 seconds
Started Mar 02 01:20:16 PM PST 24
Finished Mar 02 01:20:33 PM PST 24
Peak memory 207920 kb
Host smart-8d65d5c7-5d5b-4338-9069-7e4dc51fb3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846149855 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_smoke.2846149855
Directory /workspace/1.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/10.keymgr_dpe_alert_test.2102854899
Short name T129
Test name
Test status
Simulation time 23449110 ps
CPU time 0.86 seconds
Started Mar 02 01:20:19 PM PST 24
Finished Mar 02 01:20:20 PM PST 24
Peak memory 205360 kb
Host smart-ae289350-4f6f-4297-af53-b84b268eb320
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102854899 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_alert_test.
2102854899
Directory /workspace/10.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_dpe_alert_test.344253072
Short name T150
Test name
Test status
Simulation time 69850790 ps
CPU time 0.77 seconds
Started Mar 02 01:20:20 PM PST 24
Finished Mar 02 01:20:21 PM PST 24
Peak memory 205356 kb
Host smart-290a6d73-425a-4953-8ece-172ce91bd49a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344253072 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_alert_test.344253072
Directory /workspace/11.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_dpe_alert_test.3263948869
Short name T132
Test name
Test status
Simulation time 11297740 ps
CPU time 0.74 seconds
Started Mar 02 01:20:30 PM PST 24
Finished Mar 02 01:20:31 PM PST 24
Peak memory 205280 kb
Host smart-50dd4328-7244-4b7c-a472-71211c64e896
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263948869 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_alert_test.
3263948869
Directory /workspace/12.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_dpe_smoke.3072421082
Short name T136
Test name
Test status
Simulation time 437923705 ps
CPU time 16.11 seconds
Started Mar 02 01:20:31 PM PST 24
Finished Mar 02 01:20:47 PM PST 24
Peak memory 208028 kb
Host smart-1d896691-8a57-4599-8ec0-1abb6dc1c2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072421082 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_smoke.3072421082
Directory /workspace/12.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/13.keymgr_dpe_alert_test.1312452092
Short name T119
Test name
Test status
Simulation time 18542545 ps
CPU time 0.77 seconds
Started Mar 02 01:20:21 PM PST 24
Finished Mar 02 01:20:22 PM PST 24
Peak memory 205284 kb
Host smart-ad2bb2c8-c150-4a5c-bcf9-67c7f5c71ef2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312452092 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_alert_test.
1312452092
Directory /workspace/13.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_dpe_alert_test.474989668
Short name T130
Test name
Test status
Simulation time 17516538 ps
CPU time 0.78 seconds
Started Mar 02 01:20:22 PM PST 24
Finished Mar 02 01:20:23 PM PST 24
Peak memory 205368 kb
Host smart-88ea11de-7df0-4f9c-b897-b7bfd94682ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474989668 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_alert_test.474989668
Directory /workspace/14.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_dpe_alert_test.1138482738
Short name T152
Test name
Test status
Simulation time 123672166 ps
CPU time 0.73 seconds
Started Mar 02 01:20:27 PM PST 24
Finished Mar 02 01:20:28 PM PST 24
Peak memory 205356 kb
Host smart-d89ecea4-81d0-4cdc-a7b1-56f129d4c554
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138482738 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_alert_test.
1138482738
Directory /workspace/15.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_dpe_alert_test.386125671
Short name T127
Test name
Test status
Simulation time 18868244 ps
CPU time 0.7 seconds
Started Mar 02 01:20:27 PM PST 24
Finished Mar 02 01:20:28 PM PST 24
Peak memory 205356 kb
Host smart-d0211b8b-5760-407c-b2ab-a9ccdceae193
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386125671 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_alert_test.386125671
Directory /workspace/16.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_dpe_smoke.1879886792
Short name T110
Test name
Test status
Simulation time 6344342479 ps
CPU time 62.14 seconds
Started Mar 02 01:20:20 PM PST 24
Finished Mar 02 01:21:22 PM PST 24
Peak memory 221948 kb
Host smart-91d002e6-e164-456f-82ed-1637aabbbe44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879886792 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_smoke.1879886792
Directory /workspace/16.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/17.keymgr_dpe_alert_test.3583652438
Short name T162
Test name
Test status
Simulation time 37828074 ps
CPU time 0.74 seconds
Started Mar 02 01:20:19 PM PST 24
Finished Mar 02 01:20:20 PM PST 24
Peak memory 205348 kb
Host smart-1855ebef-7a81-49fd-b6b0-b681888a6761
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583652438 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_alert_test.
3583652438
Directory /workspace/17.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_dpe_smoke.3467127520
Short name T142
Test name
Test status
Simulation time 683634139 ps
CPU time 17.63 seconds
Started Mar 02 01:20:27 PM PST 24
Finished Mar 02 01:20:44 PM PST 24
Peak memory 207848 kb
Host smart-5bba7fcb-08f9-464d-a53b-44220282bb5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467127520 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_smoke.3467127520
Directory /workspace/17.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/18.keymgr_dpe_alert_test.3230818972
Short name T116
Test name
Test status
Simulation time 34127554 ps
CPU time 0.71 seconds
Started Mar 02 01:20:25 PM PST 24
Finished Mar 02 01:20:26 PM PST 24
Peak memory 205292 kb
Host smart-ee5abfd8-1035-47f3-a6c7-cad8b18d28a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230818972 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_alert_test.
3230818972
Directory /workspace/18.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_dpe_smoke.945827422
Short name T168
Test name
Test status
Simulation time 723121007 ps
CPU time 17.36 seconds
Started Mar 02 01:20:30 PM PST 24
Finished Mar 02 01:20:47 PM PST 24
Peak memory 206388 kb
Host smart-c3c8e073-7b1f-4f49-94fe-6cd77661233f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945827422 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_smoke.945827422
Directory /workspace/18.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/19.keymgr_dpe_alert_test.4084335550
Short name T123
Test name
Test status
Simulation time 18159814 ps
CPU time 0.99 seconds
Started Mar 02 01:20:23 PM PST 24
Finished Mar 02 01:20:24 PM PST 24
Peak memory 205492 kb
Host smart-cb93179a-a68f-4b4a-9db5-a9ffd4d9468e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084335550 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_alert_test.
4084335550
Directory /workspace/19.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_dpe_smoke.1597460036
Short name T154
Test name
Test status
Simulation time 461243712 ps
CPU time 19.05 seconds
Started Mar 02 01:20:21 PM PST 24
Finished Mar 02 01:20:40 PM PST 24
Peak memory 206392 kb
Host smart-aa35ccd9-b4a2-4d44-a728-60b08e773b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597460036 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_smoke.1597460036
Directory /workspace/19.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/2.keymgr_dpe_alert_test.883839548
Short name T78
Test name
Test status
Simulation time 12455178 ps
CPU time 0.95 seconds
Started Mar 02 01:20:16 PM PST 24
Finished Mar 02 01:20:17 PM PST 24
Peak memory 205448 kb
Host smart-09411fcb-151e-46eb-adb8-cd710c8a2125
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883839548 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_alert_test.883839548
Directory /workspace/2.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_dpe_sec_cm.1161837562
Short name T7
Test name
Test status
Simulation time 5651224468 ps
CPU time 18.12 seconds
Started Mar 02 01:20:17 PM PST 24
Finished Mar 02 01:20:35 PM PST 24
Peak memory 231008 kb
Host smart-f876506f-0b30-4d72-8c5f-3e1c34b83050
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161837562 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_sec_cm.1161837562
Directory /workspace/2.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/20.keymgr_dpe_alert_test.1384947368
Short name T133
Test name
Test status
Simulation time 40714168 ps
CPU time 0.78 seconds
Started Mar 02 01:20:32 PM PST 24
Finished Mar 02 01:20:33 PM PST 24
Peak memory 205320 kb
Host smart-056c1685-6b93-46a1-aeae-6c8399ac81ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384947368 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_alert_test.
1384947368
Directory /workspace/20.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_dpe_smoke.3536995946
Short name T141
Test name
Test status
Simulation time 8966761180 ps
CPU time 210.22 seconds
Started Mar 02 01:20:23 PM PST 24
Finished Mar 02 01:23:53 PM PST 24
Peak memory 221932 kb
Host smart-2d9b8000-2e85-45f4-96eb-a6aef0b121ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536995946 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_smoke.3536995946
Directory /workspace/20.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/21.keymgr_dpe_alert_test.3242051943
Short name T3
Test name
Test status
Simulation time 11718684 ps
CPU time 0.77 seconds
Started Mar 02 01:20:32 PM PST 24
Finished Mar 02 01:20:33 PM PST 24
Peak memory 205320 kb
Host smart-c04fc215-89ce-48af-b739-318885ef3ad9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242051943 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_alert_test.
3242051943
Directory /workspace/21.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_dpe_smoke.1627604615
Short name T14
Test name
Test status
Simulation time 519818923 ps
CPU time 8.89 seconds
Started Mar 02 01:20:33 PM PST 24
Finished Mar 02 01:20:42 PM PST 24
Peak memory 206636 kb
Host smart-57eb952c-64b4-4e51-a6bf-a3e1edf9d9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627604615 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_smoke.1627604615
Directory /workspace/21.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/22.keymgr_dpe_alert_test.3189191542
Short name T143
Test name
Test status
Simulation time 12749823 ps
CPU time 0.73 seconds
Started Mar 02 01:20:29 PM PST 24
Finished Mar 02 01:20:30 PM PST 24
Peak memory 205380 kb
Host smart-4411ac46-37d4-44db-9c7a-84df9b6df167
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189191542 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_alert_test.
3189191542
Directory /workspace/22.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_dpe_alert_test.1536099141
Short name T164
Test name
Test status
Simulation time 20863446 ps
CPU time 0.74 seconds
Started Mar 02 01:20:34 PM PST 24
Finished Mar 02 01:20:35 PM PST 24
Peak memory 205352 kb
Host smart-f689aa12-c929-4722-a093-833eea2291be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536099141 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_alert_test.
1536099141
Directory /workspace/23.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_dpe_smoke.3897139675
Short name T4
Test name
Test status
Simulation time 4728311671 ps
CPU time 47.11 seconds
Started Mar 02 01:20:30 PM PST 24
Finished Mar 02 01:21:17 PM PST 24
Peak memory 217780 kb
Host smart-739accbb-45a1-4e4b-850b-64ec8240a0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897139675 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_smoke.3897139675
Directory /workspace/23.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/24.keymgr_dpe_alert_test.1482029904
Short name T147
Test name
Test status
Simulation time 170717175 ps
CPU time 0.94 seconds
Started Mar 02 01:20:33 PM PST 24
Finished Mar 02 01:20:34 PM PST 24
Peak memory 205308 kb
Host smart-f2dc26f3-553a-4c3f-a0d4-683a828f6170
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482029904 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_alert_test.
1482029904
Directory /workspace/24.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_dpe_smoke.1878119498
Short name T105
Test name
Test status
Simulation time 1465754412 ps
CPU time 15.05 seconds
Started Mar 02 01:20:33 PM PST 24
Finished Mar 02 01:20:49 PM PST 24
Peak memory 206456 kb
Host smart-abcc06e8-c1a7-4d1d-89d9-f90cf0911936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878119498 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_smoke.1878119498
Directory /workspace/24.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/25.keymgr_dpe_alert_test.1398002052
Short name T139
Test name
Test status
Simulation time 33345371 ps
CPU time 0.7 seconds
Started Mar 02 01:20:44 PM PST 24
Finished Mar 02 01:20:45 PM PST 24
Peak memory 205368 kb
Host smart-24d62e81-9df7-47bb-8b77-420a2d6b7639
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398002052 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_alert_test.
1398002052
Directory /workspace/25.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_dpe_smoke.1930769139
Short name T161
Test name
Test status
Simulation time 917756533 ps
CPU time 15.47 seconds
Started Mar 02 01:20:36 PM PST 24
Finished Mar 02 01:20:52 PM PST 24
Peak memory 206632 kb
Host smart-fa37405c-50fa-4099-942d-4c9f1311e7ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930769139 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_smoke.1930769139
Directory /workspace/25.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/26.keymgr_dpe_alert_test.2634136472
Short name T115
Test name
Test status
Simulation time 14695200 ps
CPU time 0.88 seconds
Started Mar 02 01:20:31 PM PST 24
Finished Mar 02 01:20:32 PM PST 24
Peak memory 205304 kb
Host smart-ba9efa70-be68-4290-a279-b4bdba48fef6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634136472 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_alert_test.
2634136472
Directory /workspace/26.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_dpe_smoke.1588673233
Short name T111
Test name
Test status
Simulation time 1906330980 ps
CPU time 17.38 seconds
Started Mar 02 01:20:33 PM PST 24
Finished Mar 02 01:20:50 PM PST 24
Peak memory 207808 kb
Host smart-de10852f-739b-4edb-b978-04fdc208922f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588673233 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_smoke.1588673233
Directory /workspace/26.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/27.keymgr_dpe_alert_test.1267224893
Short name T157
Test name
Test status
Simulation time 17980598 ps
CPU time 0.97 seconds
Started Mar 02 01:20:33 PM PST 24
Finished Mar 02 01:20:34 PM PST 24
Peak memory 205492 kb
Host smart-3366031b-f045-4fff-be63-73dce3d4bfdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267224893 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_alert_test.
1267224893
Directory /workspace/27.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_dpe_smoke.575591254
Short name T131
Test name
Test status
Simulation time 831421656 ps
CPU time 18.06 seconds
Started Mar 02 01:20:40 PM PST 24
Finished Mar 02 01:20:59 PM PST 24
Peak memory 208120 kb
Host smart-4719ab65-9259-4b91-b83c-8fa3e295d112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575591254 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_smoke.575591254
Directory /workspace/27.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/28.keymgr_dpe_alert_test.3192648819
Short name T18
Test name
Test status
Simulation time 11878021 ps
CPU time 0.89 seconds
Started Mar 02 01:20:48 PM PST 24
Finished Mar 02 01:20:49 PM PST 24
Peak memory 205304 kb
Host smart-805dfa35-21b9-4131-a77e-78660aaa46c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192648819 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_alert_test.
3192648819
Directory /workspace/28.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_dpe_smoke.51590598
Short name T106
Test name
Test status
Simulation time 2201692160 ps
CPU time 10.68 seconds
Started Mar 02 01:20:42 PM PST 24
Finished Mar 02 01:20:53 PM PST 24
Peak memory 208264 kb
Host smart-160dcf46-b459-4d79-87e8-2d321611e841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51590598 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_smoke.51590598
Directory /workspace/28.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/29.keymgr_dpe_alert_test.2900318628
Short name T16
Test name
Test status
Simulation time 21054273 ps
CPU time 0.74 seconds
Started Mar 02 01:20:31 PM PST 24
Finished Mar 02 01:20:32 PM PST 24
Peak memory 205292 kb
Host smart-be8cce32-a70d-4b08-a262-79758b43e399
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900318628 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_alert_test.
2900318628
Directory /workspace/29.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_dpe_smoke.2081949867
Short name T165
Test name
Test status
Simulation time 4041531939 ps
CPU time 16.09 seconds
Started Mar 02 01:20:38 PM PST 24
Finished Mar 02 01:20:54 PM PST 24
Peak memory 207924 kb
Host smart-78ec2b39-0f7f-4d47-ac93-8e7ae9af2bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081949867 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_smoke.2081949867
Directory /workspace/29.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/3.keymgr_dpe_alert_test.1917051133
Short name T20
Test name
Test status
Simulation time 13613532 ps
CPU time 0.89 seconds
Started Mar 02 01:20:20 PM PST 24
Finished Mar 02 01:20:21 PM PST 24
Peak memory 205488 kb
Host smart-edcf766e-0967-42fe-a3c9-4b26711f0b40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917051133 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_alert_test.1
917051133
Directory /workspace/3.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_dpe_alert_test.518997956
Short name T28
Test name
Test status
Simulation time 19492784 ps
CPU time 0.72 seconds
Started Mar 02 01:20:32 PM PST 24
Finished Mar 02 01:20:33 PM PST 24
Peak memory 205368 kb
Host smart-fd68479a-a116-4e97-97f7-3f8e81720edb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518997956 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_alert_test.518997956
Directory /workspace/30.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_dpe_alert_test.3701650816
Short name T149
Test name
Test status
Simulation time 13018870 ps
CPU time 0.89 seconds
Started Mar 02 01:20:30 PM PST 24
Finished Mar 02 01:20:31 PM PST 24
Peak memory 205364 kb
Host smart-a3619ada-b827-4ed1-82b5-677786ae71bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701650816 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_alert_test.
3701650816
Directory /workspace/31.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_dpe_alert_test.3636971550
Short name T27
Test name
Test status
Simulation time 24919872 ps
CPU time 0.73 seconds
Started Mar 02 01:20:34 PM PST 24
Finished Mar 02 01:20:35 PM PST 24
Peak memory 205356 kb
Host smart-7728c6e0-59c2-4005-a809-d3190c5f31b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636971550 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_alert_test.
3636971550
Directory /workspace/32.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_dpe_alert_test.3153575629
Short name T158
Test name
Test status
Simulation time 16202493 ps
CPU time 0.81 seconds
Started Mar 02 01:20:42 PM PST 24
Finished Mar 02 01:20:43 PM PST 24
Peak memory 205360 kb
Host smart-a1b55546-5069-4a4b-ad93-bb919a5dc421
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153575629 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_alert_test.
3153575629
Directory /workspace/33.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_dpe_alert_test.351878889
Short name T118
Test name
Test status
Simulation time 30147453 ps
CPU time 0.78 seconds
Started Mar 02 01:20:37 PM PST 24
Finished Mar 02 01:20:38 PM PST 24
Peak memory 205308 kb
Host smart-f11e9952-7d89-44f3-a13d-438c4a6c5fc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351878889 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_alert_test.351878889
Directory /workspace/34.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_dpe_alert_test.2582930304
Short name T125
Test name
Test status
Simulation time 12147131 ps
CPU time 0.76 seconds
Started Mar 02 01:20:31 PM PST 24
Finished Mar 02 01:20:32 PM PST 24
Peak memory 205312 kb
Host smart-339eba86-9e61-430b-bb66-ac6f40dc7796
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582930304 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_alert_test.
2582930304
Directory /workspace/35.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_dpe_smoke.3828104286
Short name T1
Test name
Test status
Simulation time 5034186679 ps
CPU time 23.95 seconds
Started Mar 02 01:20:35 PM PST 24
Finished Mar 02 01:20:59 PM PST 24
Peak memory 218448 kb
Host smart-0dcbd124-dab3-46de-9fcd-13fd5d7cbe14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828104286 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_smoke.3828104286
Directory /workspace/35.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/36.keymgr_dpe_alert_test.473899527
Short name T117
Test name
Test status
Simulation time 53969451 ps
CPU time 0.76 seconds
Started Mar 02 01:20:33 PM PST 24
Finished Mar 02 01:20:34 PM PST 24
Peak memory 205276 kb
Host smart-27a6c190-f132-477c-935d-4c8a149e044f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473899527 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_alert_test.473899527
Directory /workspace/36.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_dpe_smoke.1090470203
Short name T81
Test name
Test status
Simulation time 1391496086 ps
CPU time 15.42 seconds
Started Mar 02 01:20:29 PM PST 24
Finished Mar 02 01:20:45 PM PST 24
Peak memory 206164 kb
Host smart-64ee3b13-f1b3-4a85-87ce-5accab17d4f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090470203 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_smoke.1090470203
Directory /workspace/36.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/37.keymgr_dpe_alert_test.721452659
Short name T156
Test name
Test status
Simulation time 32435313 ps
CPU time 0.79 seconds
Started Mar 02 01:20:44 PM PST 24
Finished Mar 02 01:20:44 PM PST 24
Peak memory 205244 kb
Host smart-61d5a18a-cce6-44ea-82c7-4d3241dd6a58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721452659 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_alert_test.721452659
Directory /workspace/37.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_dpe_alert_test.460023576
Short name T124
Test name
Test status
Simulation time 70866265 ps
CPU time 0.81 seconds
Started Mar 02 01:20:43 PM PST 24
Finished Mar 02 01:20:44 PM PST 24
Peak memory 205232 kb
Host smart-f6e0fd17-7592-4678-ba59-d05f67100179
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460023576 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_alert_test.460023576
Directory /workspace/38.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_dpe_alert_test.2913725527
Short name T17
Test name
Test status
Simulation time 13075181 ps
CPU time 0.72 seconds
Started Mar 02 01:20:41 PM PST 24
Finished Mar 02 01:20:42 PM PST 24
Peak memory 205356 kb
Host smart-b3e29d43-1093-4c36-b6ce-66dc1c6db46a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913725527 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_alert_test.
2913725527
Directory /workspace/39.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_dpe_alert_test.1438409592
Short name T145
Test name
Test status
Simulation time 25725554 ps
CPU time 0.77 seconds
Started Mar 02 01:20:15 PM PST 24
Finished Mar 02 01:20:16 PM PST 24
Peak memory 205368 kb
Host smart-54d7358c-4194-41ca-b86e-3f6620ed5c2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438409592 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_alert_test.1
438409592
Directory /workspace/4.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_dpe_sec_cm.3278340515
Short name T24
Test name
Test status
Simulation time 4360878780 ps
CPU time 14.22 seconds
Started Mar 02 01:20:27 PM PST 24
Finished Mar 02 01:20:41 PM PST 24
Peak memory 231656 kb
Host smart-f8304a09-20a3-4294-aa4e-ca853e8c9225
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278340515 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_sec_cm.3278340515
Directory /workspace/4.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/40.keymgr_dpe_alert_test.2365669938
Short name T159
Test name
Test status
Simulation time 73343540 ps
CPU time 0.94 seconds
Started Mar 02 01:20:45 PM PST 24
Finished Mar 02 01:20:46 PM PST 24
Peak memory 205416 kb
Host smart-899414cf-e36d-4f52-b08f-1ba873ea9457
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365669938 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_alert_test.
2365669938
Directory /workspace/40.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_dpe_smoke.1772082615
Short name T101
Test name
Test status
Simulation time 256933351 ps
CPU time 13.7 seconds
Started Mar 02 01:20:42 PM PST 24
Finished Mar 02 01:20:56 PM PST 24
Peak memory 205980 kb
Host smart-8a8754ac-e0f9-4eb1-ae85-fe0b4171027f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772082615 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_smoke.1772082615
Directory /workspace/40.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/41.keymgr_dpe_alert_test.300807137
Short name T121
Test name
Test status
Simulation time 48358124 ps
CPU time 0.88 seconds
Started Mar 02 01:20:45 PM PST 24
Finished Mar 02 01:20:46 PM PST 24
Peak memory 205340 kb
Host smart-7fa4860f-9f0d-4cfb-b6c6-f7c4ef86200c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300807137 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_alert_test.300807137
Directory /workspace/41.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_dpe_smoke.1121190117
Short name T98
Test name
Test status
Simulation time 500945480 ps
CPU time 13.61 seconds
Started Mar 02 01:20:42 PM PST 24
Finished Mar 02 01:20:56 PM PST 24
Peak memory 207988 kb
Host smart-f340c45a-32ac-4565-8a98-b61dd05a02f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121190117 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_smoke.1121190117
Directory /workspace/41.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/42.keymgr_dpe_alert_test.1434817512
Short name T128
Test name
Test status
Simulation time 43348347 ps
CPU time 0.76 seconds
Started Mar 02 01:20:42 PM PST 24
Finished Mar 02 01:20:42 PM PST 24
Peak memory 205372 kb
Host smart-25201bce-a8ca-4009-8fe0-985595b4aabe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434817512 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_alert_test.
1434817512
Directory /workspace/42.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_dpe_smoke.4018710226
Short name T82
Test name
Test status
Simulation time 1487945238 ps
CPU time 24.05 seconds
Started Mar 02 01:20:42 PM PST 24
Finished Mar 02 01:21:06 PM PST 24
Peak memory 207436 kb
Host smart-0f6040b3-6336-4033-b337-4782219f1cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018710226 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_smoke.4018710226
Directory /workspace/42.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/43.keymgr_dpe_alert_test.3855884196
Short name T126
Test name
Test status
Simulation time 140816123 ps
CPU time 0.76 seconds
Started Mar 02 01:20:41 PM PST 24
Finished Mar 02 01:20:42 PM PST 24
Peak memory 205360 kb
Host smart-dcbda7a2-12ee-4b3d-9810-b165a2bbf3e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855884196 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_alert_test.
3855884196
Directory /workspace/43.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_dpe_smoke.2693835268
Short name T13
Test name
Test status
Simulation time 1568623158 ps
CPU time 17.28 seconds
Started Mar 02 01:20:45 PM PST 24
Finished Mar 02 01:21:02 PM PST 24
Peak memory 207872 kb
Host smart-8d8b0f52-8c45-48dc-a8da-a267f612aae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693835268 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_smoke.2693835268
Directory /workspace/43.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/44.keymgr_dpe_alert_test.2124067381
Short name T120
Test name
Test status
Simulation time 12379205 ps
CPU time 0.76 seconds
Started Mar 02 01:20:48 PM PST 24
Finished Mar 02 01:20:48 PM PST 24
Peak memory 205320 kb
Host smart-d681c2c8-8f8a-4bc2-97a1-8627b156c23e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124067381 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_alert_test.
2124067381
Directory /workspace/44.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_dpe_alert_test.2311425916
Short name T114
Test name
Test status
Simulation time 22361104 ps
CPU time 0.85 seconds
Started Mar 02 01:20:46 PM PST 24
Finished Mar 02 01:20:47 PM PST 24
Peak memory 205340 kb
Host smart-98af8c0f-fbc3-4278-a985-bb12efd83299
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311425916 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_alert_test.
2311425916
Directory /workspace/45.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_dpe_smoke.546963719
Short name T138
Test name
Test status
Simulation time 4893275996 ps
CPU time 79.55 seconds
Started Mar 02 01:20:48 PM PST 24
Finished Mar 02 01:22:08 PM PST 24
Peak memory 221372 kb
Host smart-30d57200-3708-437e-979d-32dd2be941ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546963719 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_smoke.546963719
Directory /workspace/45.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/46.keymgr_dpe_alert_test.231137244
Short name T160
Test name
Test status
Simulation time 30550350 ps
CPU time 0.81 seconds
Started Mar 02 01:20:48 PM PST 24
Finished Mar 02 01:20:49 PM PST 24
Peak memory 205356 kb
Host smart-1c56e429-85bd-440d-9594-748aff7227c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231137244 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_alert_test.231137244
Directory /workspace/46.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_dpe_smoke.4049143575
Short name T163
Test name
Test status
Simulation time 264162743 ps
CPU time 9.22 seconds
Started Mar 02 01:20:44 PM PST 24
Finished Mar 02 01:20:54 PM PST 24
Peak memory 207940 kb
Host smart-e4522f6e-f864-4027-a973-d51aefe0bf50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049143575 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_smoke.4049143575
Directory /workspace/46.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/47.keymgr_dpe_alert_test.1155216340
Short name T167
Test name
Test status
Simulation time 30264835 ps
CPU time 0.95 seconds
Started Mar 02 01:20:47 PM PST 24
Finished Mar 02 01:20:48 PM PST 24
Peak memory 205428 kb
Host smart-79093546-1c29-4c0d-b69b-58fc72c6b69d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155216340 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_alert_test.
1155216340
Directory /workspace/47.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_dpe_smoke.1686672004
Short name T140
Test name
Test status
Simulation time 2048151479 ps
CPU time 23.29 seconds
Started Mar 02 01:20:46 PM PST 24
Finished Mar 02 01:21:09 PM PST 24
Peak memory 207888 kb
Host smart-5da0ab60-a3b1-4b6c-8c87-46e0287e3bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686672004 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_smoke.1686672004
Directory /workspace/47.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/48.keymgr_dpe_alert_test.1223618539
Short name T134
Test name
Test status
Simulation time 65946708 ps
CPU time 0.84 seconds
Started Mar 02 01:20:43 PM PST 24
Finished Mar 02 01:20:44 PM PST 24
Peak memory 205284 kb
Host smart-1ee67361-4487-4b41-802b-7224e57326c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223618539 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_alert_test.
1223618539
Directory /workspace/48.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_dpe_smoke.1400149984
Short name T122
Test name
Test status
Simulation time 4139753580 ps
CPU time 23.44 seconds
Started Mar 02 01:20:41 PM PST 24
Finished Mar 02 01:21:04 PM PST 24
Peak memory 208076 kb
Host smart-97b4bb6e-3474-47f7-a365-fa71b623e06f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400149984 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_smoke.1400149984
Directory /workspace/48.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/49.keymgr_dpe_alert_test.1749151453
Short name T155
Test name
Test status
Simulation time 30933360 ps
CPU time 0.9 seconds
Started Mar 02 01:20:43 PM PST 24
Finished Mar 02 01:20:44 PM PST 24
Peak memory 205324 kb
Host smart-dff40c72-a53f-4303-ab3b-96e4136846e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749151453 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_alert_test.
1749151453
Directory /workspace/49.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_dpe_smoke.94822152
Short name T29
Test name
Test status
Simulation time 21576356907 ps
CPU time 247.14 seconds
Started Mar 02 01:20:43 PM PST 24
Finished Mar 02 01:24:50 PM PST 24
Peak memory 225316 kb
Host smart-bc16c03c-bcb6-4996-8ea7-73456ee40a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94822152 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_smoke.94822152
Directory /workspace/49.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/5.keymgr_dpe_alert_test.4169632798
Short name T135
Test name
Test status
Simulation time 117639633 ps
CPU time 1 seconds
Started Mar 02 01:20:14 PM PST 24
Finished Mar 02 01:20:15 PM PST 24
Peak memory 205536 kb
Host smart-9013c28f-f2b4-4314-a0ef-f1290d03ca72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169632798 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_alert_test.4
169632798
Directory /workspace/5.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_dpe_smoke.867281226
Short name T144
Test name
Test status
Simulation time 2329468283 ps
CPU time 23.12 seconds
Started Mar 02 01:20:19 PM PST 24
Finished Mar 02 01:20:42 PM PST 24
Peak memory 208028 kb
Host smart-f418d79e-962e-4271-9edd-b7cf6273bfb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867281226 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_smoke.867281226
Directory /workspace/5.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/6.keymgr_dpe_alert_test.1676988682
Short name T113
Test name
Test status
Simulation time 27484641 ps
CPU time 0.79 seconds
Started Mar 02 01:20:19 PM PST 24
Finished Mar 02 01:20:20 PM PST 24
Peak memory 205232 kb
Host smart-8e602209-dfde-4724-8189-bd5b77729941
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676988682 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_alert_test.1
676988682
Directory /workspace/6.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_dpe_smoke.617113704
Short name T108
Test name
Test status
Simulation time 8276678018 ps
CPU time 197.59 seconds
Started Mar 02 01:20:20 PM PST 24
Finished Mar 02 01:23:37 PM PST 24
Peak memory 222236 kb
Host smart-a09559ab-2ba4-40e8-b66e-b8e44f94d97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617113704 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_smoke.617113704
Directory /workspace/6.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/7.keymgr_dpe_alert_test.1309454443
Short name T26
Test name
Test status
Simulation time 144960751 ps
CPU time 0.8 seconds
Started Mar 02 01:20:22 PM PST 24
Finished Mar 02 01:20:23 PM PST 24
Peak memory 205276 kb
Host smart-ec658cf6-60fc-42a5-81ab-98d19da20734
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309454443 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_alert_test.1
309454443
Directory /workspace/7.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_dpe_alert_test.1252831759
Short name T19
Test name
Test status
Simulation time 56565034 ps
CPU time 0.76 seconds
Started Mar 02 01:20:27 PM PST 24
Finished Mar 02 01:20:28 PM PST 24
Peak memory 205292 kb
Host smart-5292c2bd-ea4c-4996-8049-cb0b53dca5db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252831759 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_alert_test.1
252831759
Directory /workspace/8.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_dpe_smoke.412783980
Short name T169
Test name
Test status
Simulation time 6755106393 ps
CPU time 26.22 seconds
Started Mar 02 01:20:21 PM PST 24
Finished Mar 02 01:20:48 PM PST 24
Peak memory 208344 kb
Host smart-9fb65f63-efba-4307-aa40-4944e6beba02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412783980 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_smoke.412783980
Directory /workspace/8.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/9.keymgr_dpe_alert_test.2498660764
Short name T137
Test name
Test status
Simulation time 12161885 ps
CPU time 0.86 seconds
Started Mar 02 01:20:26 PM PST 24
Finished Mar 02 01:20:27 PM PST 24
Peak memory 205360 kb
Host smart-92dfe238-d1ab-4d21-b0ff-8365a2c2bfd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498660764 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_alert_test.2
498660764
Directory /workspace/9.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_dpe_smoke.807901992
Short name T146
Test name
Test status
Simulation time 649420033 ps
CPU time 21.63 seconds
Started Mar 02 01:20:27 PM PST 24
Finished Mar 02 01:20:49 PM PST 24
Peak memory 206044 kb
Host smart-6f90bfd8-f7fb-4670-ad03-c7236f69f531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807901992 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_smoke.807901992
Directory /workspace/9.keymgr_dpe_smoke/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%