Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1025931	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

247127

1

T1

10

T2

3292

T3

2244

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1129461	1			T1	1		T2	4786		T3	3869
values[0x0]	71246	1			T1	10		T2	867		T3	567
values[0x1]	72351	1			T1	9		T2	838		T3	575

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	700131	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

572927

1

T1

10

T2

4063

T3

2997

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3329	1			T2	23		T8	32		T6	13
valid_sources[0x01]	24936	1			T2	31		T8	33		T6	10
valid_sources[0x02]	3408	1			T2	21		T8	23		T6	11
valid_sources[0x03]	3467	1			T2	36		T8	29		T6	7
valid_sources[0x04]	3638	1			T2	20		T8	42		T6	10
valid_sources[0x05]	3566	1			T2	25		T8	15		T6	13
valid_sources[0x06]	23752	1			T2	19		T8	44		T6	5
valid_sources[0x07]	3413	1			T2	13		T8	18		T6	9
valid_sources[0x08]	3501	1			T2	22		T8	50		T6	9
valid_sources[0x09]	3313	1			T2	20		T8	49		T6	17
valid_sources[0x0a]	3394	1			T2	27		T8	33		T6	9
valid_sources[0x0b]	3338	1			T2	27		T8	28		T6	18
valid_sources[0x0c]	3838	1			T2	24		T8	49		T6	13
valid_sources[0x0d]	3413	1			T2	25		T8	33		T6	10
valid_sources[0x0e]	3606	1			T2	22		T8	55		T6	13
valid_sources[0x0f]	3638	1			T2	24		T8	29		T6	8
valid_sources[0x10]	3690	1			T2	22		T8	35		T6	6
valid_sources[0x11]	3554	1			T2	23		T8	25		T6	15
valid_sources[0x12]	3520	1			T2	21		T8	26		T6	10
valid_sources[0x13]	3605	1			T2	32		T8	9		T6	13
valid_sources[0x14]	3687	1			T2	42		T8	26		T6	6
valid_sources[0x15]	3447	1			T2	23		T8	48		T6	15
valid_sources[0x16]	3419	1			T2	31		T8	26		T6	17
valid_sources[0x17]	3232	1			T2	17		T15	7		T8	54
valid_sources[0x18]	3272	1			T2	25		T8	14		T6	16
valid_sources[0x19]	3245	1			T2	22		T8	24		T6	12
valid_sources[0x1a]	3307	1			T2	31		T8	16		T6	11
valid_sources[0x1b]	3579	1			T2	33		T8	35		T6	17
valid_sources[0x1c]	12052	1			T2	27		T8	28		T6	12
valid_sources[0x1d]	3553	1			T2	21		T8	32		T6	5
valid_sources[0x1e]	3474	1			T2	34		T8	37		T6	12
valid_sources[0x1f]	3344	1			T2	23		T8	24		T6	11
valid_sources[0x20]	3491	1			T2	34		T8	58		T6	17
valid_sources[0x21]	3468	1			T2	23		T8	25		T6	13
valid_sources[0x22]	3434	1			T2	30		T8	17		T6	11
valid_sources[0x23]	3533	1			T2	25		T8	25		T6	13
valid_sources[0x24]	3171	1			T2	23		T8	27		T6	11
valid_sources[0x25]	5078	1			T2	42		T8	50		T6	7
valid_sources[0x26]	3691	1			T2	23		T8	24		T6	10
valid_sources[0x27]	3661	1			T2	23		T8	47		T6	6
valid_sources[0x28]	3544	1			T2	17		T8	23		T6	17
valid_sources[0x29]	3559	1			T2	27		T8	24		T6	6
valid_sources[0x2a]	3537	1			T2	27		T8	33		T6	12
valid_sources[0x2b]	6355	1			T2	33		T4	2823		T8	33
valid_sources[0x2c]	3544	1			T2	32		T8	54		T6	9
valid_sources[0x2d]	3705	1			T2	26		T8	34		T6	7
valid_sources[0x2e]	5087	1			T2	26		T8	23		T6	17
valid_sources[0x2f]	3454	1			T2	26		T8	19		T6	9
valid_sources[0x30]	3494	1			T2	22		T8	36		T6	11
valid_sources[0x31]	3168	1			T2	23		T8	22		T6	17
valid_sources[0x32]	3569	1			T2	24		T8	26		T6	14
valid_sources[0x33]	3632	1			T2	34		T8	25		T6	8
valid_sources[0x34]	3547	1			T2	21		T8	65		T6	15
valid_sources[0x35]	3657	1			T2	22		T8	38		T6	8
valid_sources[0x36]	3325	1			T2	25		T8	31		T6	17
valid_sources[0x37]	3583	1			T2	31		T8	67		T6	11
valid_sources[0x38]	3561	1			T2	23		T15	5		T8	43
valid_sources[0x39]	13597	1			T2	28		T8	42		T6	10
valid_sources[0x3a]	3384	1			T2	24		T8	26		T6	5
valid_sources[0x3b]	3424	1			T2	23		T8	25		T6	12
valid_sources[0x3c]	3603	1			T2	19		T8	27		T6	12
valid_sources[0x3d]	3857	1			T2	30		T8	22		T6	11
valid_sources[0x3e]	3460	1			T2	13		T8	14		T6	12
valid_sources[0x3f]	3484	1			T2	24		T8	39		T6	5
valid_sources[0x40]	3424	1			T2	24		T8	12		T6	14
valid_sources[0x41]	3683	1			T2	23		T8	44		T6	8
valid_sources[0x42]	9661	1			T2	13		T8	50		T6	9
valid_sources[0x43]	3307	1			T2	32		T8	31		T6	17
valid_sources[0x44]	3524	1			T2	12		T8	32		T6	6
valid_sources[0x45]	3583	1			T2	29		T8	26		T6	8
valid_sources[0x46]	3797	1			T2	32		T8	35		T6	15
valid_sources[0x47]	3361	1			T2	19		T8	19		T6	11
valid_sources[0x48]	3419	1			T2	17		T8	9		T6	11
valid_sources[0x49]	3516	1			T2	23		T8	15		T6	5
valid_sources[0x4a]	3221	1			T2	30		T8	19		T6	9
valid_sources[0x4b]	4996	1			T2	11		T8	24		T6	10
valid_sources[0x4c]	3652	1			T2	25		T8	20		T6	9
valid_sources[0x4d]	3589	1			T2	23		T8	56		T6	11
valid_sources[0x4e]	3442	1			T2	15		T8	55		T6	13
valid_sources[0x4f]	3732	1			T2	28		T8	17		T6	10
valid_sources[0x50]	3682	1			T2	18		T8	42		T6	10
valid_sources[0x51]	3710	1			T2	24		T8	28		T6	9
valid_sources[0x52]	3566	1			T1	20		T2	22		T8	40
valid_sources[0x53]	15430	1			T2	25		T8	68		T6	14
valid_sources[0x54]	32084	1			T2	24		T3	184		T8	38
valid_sources[0x55]	3603	1			T2	26		T8	43		T6	20
valid_sources[0x56]	3495	1			T2	19		T8	26		T6	9
valid_sources[0x57]	3441	1			T2	20		T8	40		T6	10
valid_sources[0x58]	7379	1			T2	26		T8	21		T6	16
valid_sources[0x59]	3347	1			T2	23		T8	16		T6	14
valid_sources[0x5a]	3623	1			T2	40		T8	52		T6	10
valid_sources[0x5b]	3529	1			T2	20		T8	43		T6	11
valid_sources[0x5c]	5161	1			T2	22		T5	1255		T8	39
valid_sources[0x5d]	3447	1			T2	27		T8	36		T6	12
valid_sources[0x5e]	3334	1			T2	27		T8	46		T6	12
valid_sources[0x5f]	3896	1			T2	32		T8	42		T6	9
valid_sources[0x60]	3541	1			T2	21		T8	31		T6	15
valid_sources[0x61]	3787	1			T2	24		T8	45		T6	15
valid_sources[0x62]	3509	1			T2	17		T8	38		T6	5
valid_sources[0x63]	3299	1			T2	21		T8	27		T6	10
valid_sources[0x64]	3950	1			T2	18		T8	65		T6	7
valid_sources[0x65]	3374	1			T2	28		T8	50		T6	11
valid_sources[0x66]	3523	1			T2	22		T8	64		T6	9
valid_sources[0x67]	3761	1			T2	31		T8	44		T6	9
valid_sources[0x68]	3479	1			T2	29		T8	44		T6	6
valid_sources[0x69]	3600	1			T2	27		T8	20		T6	7
valid_sources[0x6a]	3611	1			T2	18		T8	24		T6	12
valid_sources[0x6b]	3207	1			T2	19		T8	40		T6	5
valid_sources[0x6c]	3435	1			T2	21		T8	37		T6	13
valid_sources[0x6d]	3399	1			T2	31		T8	38		T6	11
valid_sources[0x6e]	10986	1			T2	24		T8	46		T6	16
valid_sources[0x6f]	56886	1			T2	30		T8	23		T6	12
valid_sources[0x70]	4982	1			T2	28		T8	32		T6	18
valid_sources[0x71]	11443	1			T2	32		T4	5175		T8	37
valid_sources[0x72]	3712	1			T2	27		T8	53		T6	11
valid_sources[0x73]	3494	1			T2	20		T8	18		T6	6
valid_sources[0x74]	3420	1			T2	25		T8	32		T6	8
valid_sources[0x75]	3373	1			T2	35		T8	36		T6	11
valid_sources[0x76]	3485	1			T2	22		T8	33		T6	14
valid_sources[0x77]	3355	1			T2	26		T8	24		T6	12
valid_sources[0x78]	3247	1			T2	18		T8	28		T6	6
valid_sources[0x79]	3621	1			T2	25		T8	25		T6	11
valid_sources[0x7a]	3414	1			T2	31		T8	55		T6	14
valid_sources[0x7b]	6006	1			T2	21		T8	32		T6	4
valid_sources[0x7c]	3643	1			T2	29		T8	49		T6	13
valid_sources[0x7d]	3596	1			T2	23		T8	30		T6	10
valid_sources[0x7e]	3469	1			T2	25		T8	27		T6	9
valid_sources[0x7f]	47643	1			T2	15		T8	35		T6	8
valid_sources[0x80]	3855	1			T2	22		T8	46		T6	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

137027

1

T2

2171

T3

1474

T4

1747

values[0x0]

all_enables

biggest_size

58553

1

T1

7

T2

643

T3

429

values[0x1]

all_enables

biggest_size

51547

1

T1

3

T2

478

T3

341