Unified Coverage Report :: Module :: keymgr_dpe_reg_top

Module : keymgr_dpe_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.79	100.00	95.18			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_dpe_0.1/rtl/keymgr_dpe_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg	98.79	100.00	95.18			100.00	100.00

---

Module Instance : tb.dut.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.79	100.00	95.18			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.17	98.11	95.65	100.00		97.07	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.39	100.00	80.22	53.88		97.83	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test_fatal_fault_err	100.00	100.00
u_alert_test_recov_operation_err	100.00	100.00
u_cfg_regwen	100.00	100.00
u_chk	100.00	100.00		100.00			100.00
u_control_shadowed_dest_sel	99.55	100.00	98.21			100.00	100.00
u_control_shadowed_operation	99.55	100.00	98.21			100.00	100.00
u_control_shadowed_slot_dst_sel	99.55	100.00	98.21			100.00	100.00
u_control_shadowed_slot_src_sel	99.55	100.00	98.21			100.00	100.00
u_debug_inactive_lc_en	69.07	88.89	58.33			60.00
u_debug_invalid_creator_seed	94.44	100.00	83.33			100.00
u_debug_invalid_dev_id	94.44	100.00	83.33			100.00
u_debug_invalid_digest	94.44	100.00	83.33			100.00
u_debug_invalid_health_state	94.44	100.00	83.33			100.00
u_debug_invalid_key	100.00	100.00	100.00			100.00
u_debug_invalid_key_version	100.00	100.00	100.00			100.00
u_debug_invalid_owner_seed	94.44	100.00	83.33			100.00
u_debug_invalid_root_key	94.44	100.00	83.33			100.00
u_err_code_invalid_kmac_input	100.00	100.00	100.00			100.00
u_err_code_invalid_op	100.00	100.00	100.00			100.00
u_err_code_invalid_shadow_update	97.22	100.00	91.67			100.00
u_fault_status_cmd	63.33	80.00	50.00			60.00
u_fault_status_ctrl_fsm_chk	63.33	80.00	50.00			60.00
u_fault_status_ctrl_fsm_cnt	96.67	90.00	100.00			100.00
u_fault_status_ctrl_fsm_intg	96.67	90.00	100.00			100.00
u_fault_status_key_ecc	63.33	80.00	50.00			60.00
u_fault_status_kmac_done	63.33	80.00	50.00			60.00
u_fault_status_kmac_fsm	96.67	90.00	100.00			100.00
u_fault_status_kmac_op	63.33	80.00	50.00			60.00
u_fault_status_kmac_out	63.33	80.00	50.00			60.00
u_fault_status_regfile_intg	96.67	90.00	100.00			100.00
u_fault_status_reseed_cnt	96.67	90.00	100.00			100.00
u_fault_status_shadow	96.67	90.00	100.00			100.00
u_fault_status_side_ctrl_fsm	96.67	90.00	100.00			100.00
u_fault_status_side_ctrl_sel	63.33	80.00	50.00			60.00
u_intr_enable	100.00	100.00	100.00			100.00
u_intr_state	100.00	100.00	100.00			100.00
u_intr_test	100.00	100.00
u_key_version	100.00	100.00	100.00			100.00
u_max_key_ver_regwen	100.00	100.00
u_max_key_ver_shadowed	99.55	100.00	98.21			100.00	100.00
u_op_status	100.00	100.00	100.00			100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	98.69	97.14	97.62			100.00	100.00
u_reseed_interval_regwen	66.30	88.89	50.00			60.00
u_reseed_interval_shadowed	99.55	100.00	98.21			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_salt_0	100.00	100.00	100.00			100.00
u_salt_1	100.00	100.00	100.00			100.00
u_salt_2	100.00	100.00	100.00			100.00
u_salt_3	100.00	100.00	100.00			100.00
u_salt_4	100.00	100.00	100.00			100.00
u_salt_5	100.00	100.00	100.00			100.00
u_salt_6	100.00	100.00	100.00			100.00
u_salt_7	100.00	100.00	100.00			100.00
u_sideload_clear	100.00	100.00	100.00			100.00
u_slot_policy_allow_child	100.00	100.00	100.00			100.00
u_slot_policy_exportable	100.00	100.00	100.00			100.00
u_slot_policy_regwen	100.00	100.00
u_slot_policy_retain_parent	100.00	100.00	100.00			100.00
u_start	100.00	100.00	100.00			100.00
u_sw_binding_0	100.00	100.00	100.00			100.00
u_sw_binding_1	100.00	100.00	100.00			100.00
u_sw_binding_2	100.00	100.00	100.00			100.00
u_sw_binding_3	100.00	100.00	100.00			100.00
u_sw_binding_4	100.00	100.00	100.00			100.00
u_sw_binding_5	100.00	100.00	100.00			100.00
u_sw_binding_6	100.00	100.00	100.00			100.00
u_sw_binding_7	100.00	100.00	100.00			100.00
u_sw_binding_regwen	100.00	100.00
u_sw_share0_output_0	100.00	100.00	100.00			100.00
u_sw_share0_output_1	100.00	100.00	100.00			100.00
u_sw_share0_output_2	100.00	100.00	100.00			100.00
u_sw_share0_output_3	100.00	100.00	100.00			100.00
u_sw_share0_output_4	100.00	100.00	100.00			100.00
u_sw_share0_output_5	100.00	100.00	100.00			100.00
u_sw_share0_output_6	100.00	100.00	100.00			100.00
u_sw_share0_output_7	100.00	100.00	100.00			100.00
u_sw_share1_output_0	100.00	100.00	100.00			100.00
u_sw_share1_output_1	100.00	100.00	100.00			100.00
u_sw_share1_output_2	100.00	100.00	100.00			100.00
u_sw_share1_output_3	100.00	100.00	100.00			100.00
u_sw_share1_output_4	100.00	100.00	100.00			100.00
u_sw_share1_output_5	100.00	100.00	100.00			100.00
u_sw_share1_output_6	100.00	100.00	100.00			100.00
u_sw_share1_output_7	100.00	100.00	100.00			100.00
u_working_state	63.33	80.00	50.00			60.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : keymgr_dpe_reg_top

	Line No.	Total	Covered	Percent
TOTAL		356	356	100.00
ALWAYS	75	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	97	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	406	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	441	1	1	100.00
CONT_ASSIGN	457	1	1	100.00
CONT_ASSIGN	479	1	1	100.00
CONT_ASSIGN	510	1	1	100.00
CONT_ASSIGN	659	1	1	100.00
CONT_ASSIGN	718	1	1	100.00
CONT_ASSIGN	759	1	1	100.00
CONT_ASSIGN	773	1	1	100.00
CONT_ASSIGN	779	1	1	100.00
CONT_ASSIGN	865	1	1	100.00
CONT_ASSIGN	879	1	1	100.00
CONT_ASSIGN	886	1	1	100.00
CONT_ASSIGN	918	1	1	100.00
CONT_ASSIGN	950	1	1	100.00
CONT_ASSIGN	982	1	1	100.00
CONT_ASSIGN	1014	1	1	100.00
CONT_ASSIGN	1046	1	1	100.00
CONT_ASSIGN	1078	1	1	100.00
CONT_ASSIGN	1110	1	1	100.00
CONT_ASSIGN	1142	1	1	100.00
CONT_ASSIGN	1174	1	1	100.00
CONT_ASSIGN	1206	1	1	100.00
CONT_ASSIGN	1238	1	1	100.00
CONT_ASSIGN	1270	1	1	100.00
CONT_ASSIGN	1302	1	1	100.00
CONT_ASSIGN	1334	1	1	100.00
CONT_ASSIGN	1366	1	1	100.00
CONT_ASSIGN	1398	1	1	100.00
CONT_ASSIGN	1429	1	1	100.00
CONT_ASSIGN	1443	1	1	100.00
CONT_ASSIGN	1449	1	1	100.00
ALWAYS	2717	54	54	100.00
CONT_ASSIGN	2773	1	1	100.00
ALWAYS	2777	1	1	100.00
CONT_ASSIGN	2834	1	1	100.00
CONT_ASSIGN	2836	1	1	100.00
CONT_ASSIGN	2837	1	1	100.00
CONT_ASSIGN	2839	1	1	100.00
CONT_ASSIGN	2840	1	1	100.00
CONT_ASSIGN	2842	1	1	100.00
CONT_ASSIGN	2843	1	1	100.00
CONT_ASSIGN	2845	1	1	100.00
CONT_ASSIGN	2847	1	1	100.00
CONT_ASSIGN	2848	1	1	100.00
CONT_ASSIGN	2849	1	1	100.00
CONT_ASSIGN	2851	1	1	100.00
CONT_ASSIGN	2852	1	1	100.00
CONT_ASSIGN	2853	1	1	100.00
CONT_ASSIGN	2855	1	1	100.00
CONT_ASSIGN	2857	1	1	100.00
CONT_ASSIGN	2859	1	1	100.00
CONT_ASSIGN	2861	1	1	100.00
CONT_ASSIGN	2862	1	1	100.00
CONT_ASSIGN	2864	1	1	100.00
CONT_ASSIGN	2865	1	1	100.00
CONT_ASSIGN	2867	1	1	100.00
CONT_ASSIGN	2868	1	1	100.00
CONT_ASSIGN	2869	1	1	100.00
CONT_ASSIGN	2871	1	1	100.00
CONT_ASSIGN	2872	1	1	100.00
CONT_ASSIGN	2873	1	1	100.00
CONT_ASSIGN	2875	1	1	100.00
CONT_ASSIGN	2876	1	1	100.00
CONT_ASSIGN	2878	1	1	100.00
CONT_ASSIGN	2880	1	1	100.00
CONT_ASSIGN	2882	1	1	100.00
CONT_ASSIGN	2883	1	1	100.00
CONT_ASSIGN	2884	1	1	100.00
CONT_ASSIGN	2886	1	1	100.00
CONT_ASSIGN	2887	1	1	100.00
CONT_ASSIGN	2889	1	1	100.00
CONT_ASSIGN	2890	1	1	100.00
CONT_ASSIGN	2892	1	1	100.00
CONT_ASSIGN	2893	1	1	100.00
CONT_ASSIGN	2895	1	1	100.00
CONT_ASSIGN	2896	1	1	100.00
CONT_ASSIGN	2898	1	1	100.00
CONT_ASSIGN	2899	1	1	100.00
CONT_ASSIGN	2901	1	1	100.00
CONT_ASSIGN	2902	1	1	100.00
CONT_ASSIGN	2904	1	1	100.00
CONT_ASSIGN	2905	1	1	100.00
CONT_ASSIGN	2907	1	1	100.00
CONT_ASSIGN	2908	1	1	100.00
CONT_ASSIGN	2910	1	1	100.00
CONT_ASSIGN	2911	1	1	100.00
CONT_ASSIGN	2913	1	1	100.00
CONT_ASSIGN	2914	1	1	100.00
CONT_ASSIGN	2916	1	1	100.00
CONT_ASSIGN	2917	1	1	100.00
CONT_ASSIGN	2919	1	1	100.00
CONT_ASSIGN	2920	1	1	100.00
CONT_ASSIGN	2922	1	1	100.00
CONT_ASSIGN	2923	1	1	100.00
CONT_ASSIGN	2925	1	1	100.00
CONT_ASSIGN	2926	1	1	100.00
CONT_ASSIGN	2928	1	1	100.00
CONT_ASSIGN	2929	1	1	100.00
CONT_ASSIGN	2931	1	1	100.00
CONT_ASSIGN	2932	1	1	100.00
CONT_ASSIGN	2934	1	1	100.00
CONT_ASSIGN	2935	1	1	100.00
CONT_ASSIGN	2937	1	1	100.00
CONT_ASSIGN	2938	1	1	100.00
CONT_ASSIGN	2939	1	1	100.00
CONT_ASSIGN	2941	1	1	100.00
CONT_ASSIGN	2942	1	1	100.00
CONT_ASSIGN	2943	1	1	100.00
CONT_ASSIGN	2945	1	1	100.00
CONT_ASSIGN	2946	1	1	100.00
CONT_ASSIGN	2949	1	1	100.00
CONT_ASSIGN	2952	1	1	100.00
CONT_ASSIGN	2955	1	1	100.00
CONT_ASSIGN	2958	1	1	100.00
CONT_ASSIGN	2961	1	1	100.00
CONT_ASSIGN	2964	1	1	100.00
CONT_ASSIGN	2967	1	1	100.00
CONT_ASSIGN	2970	1	1	100.00
CONT_ASSIGN	2973	1	1	100.00
CONT_ASSIGN	2976	1	1	100.00
CONT_ASSIGN	2979	1	1	100.00
CONT_ASSIGN	2982	1	1	100.00
CONT_ASSIGN	2985	1	1	100.00
CONT_ASSIGN	2988	1	1	100.00
CONT_ASSIGN	2991	1	1	100.00
CONT_ASSIGN	2994	1	1	100.00
CONT_ASSIGN	2996	1	1	100.00
CONT_ASSIGN	2997	1	1	100.00
CONT_ASSIGN	2999	1	1	100.00
CONT_ASSIGN	3001	1	1	100.00
CONT_ASSIGN	3003	1	1	100.00
CONT_ASSIGN	3004	1	1	100.00
CONT_ASSIGN	3006	1	1	100.00
CONT_ASSIGN	3008	1	1	100.00
CONT_ASSIGN	3010	1	1	100.00
CONT_ASSIGN	3012	1	1	100.00
CONT_ASSIGN	3014	1	1	100.00
CONT_ASSIGN	3016	1	1	100.00
CONT_ASSIGN	3018	1	1	100.00
CONT_ASSIGN	3020	1	1	100.00
CONT_ASSIGN	3022	1	1	100.00
ALWAYS	3026	54	54	100.00
ALWAYS	3084	84	84	100.00
ALWAYS	3338	3	3	100.00
ALWAYS	3346	3	3	100.00
CONT_ASSIGN	3354	1	1	100.00
CONT_ASSIGN	3357	1	1	100.00
CONT_ASSIGN	3365	1	1	100.00
CONT_ASSIGN	3375	1	1	100.00
CONT_ASSIGN	3383	1	1	100.00
CONT_ASSIGN	3384	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_dpe_0.1/rtl/keymgr_dpe_reg_top.sv' or '../src/lowrisc_ip_keymgr_dpe_0.1/rtl/keymgr_dpe_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
75	1	1
76	1	1
77	1	1
78	1	1
			MISSING_ELSE
84	1	1
96	1	1
97	1	1
125	1	1
126	1	1
406	1	1
420	1	1
426	1	1
441	1	1
457	1	1
479	1	1
510	1	1
659	1	1
718	1	1
759	1	1
773	1	1
779	1	1
865	1	1
879	1	1
886	1	1
918	1	1
950	1	1
982	1	1
1014	1	1
1046	1	1
1078	1	1
1110	1	1
1142	1	1
1174	1	1
1206	1	1
1238	1	1
1270	1	1
1302	1	1
1334	1	1
1366	1	1
1398	1	1
1429	1	1
1443	1	1
1449	1	1
2717	1	1
2718	1	1
2719	1	1
2720	1	1
2721	1	1
2722	1	1
2723	1	1
2724	1	1
2725	1	1
2726	1	1
2727	1	1
2728	1	1
2729	1	1
2730	1	1
2731	1	1
2732	1	1
2733	1	1
2734	1	1
2735	1	1
2736	1	1
2737	1	1
2738	1	1
2739	1	1
2740	1	1
2741	1	1
2742	1	1
2743	1	1
2744	1	1
2745	1	1
2746	1	1
2747	1	1
2748	1	1
2749	1	1
2750	1	1
2751	1	1
2752	1	1
2753	1	1
2754	1	1
2755	1	1
2756	1	1
2757	1	1
2758	1	1
2759	1	1
2760	1	1
2761	1	1
2762	1	1
2763	1	1
2764	1	1
2765	1	1
2766	1	1
2767	1	1
2768	1	1
2769	1	1
2770	1	1
2773	1	1
2777	1	1
2834	1	1
2836	1	1
2837	1	1
2839	1	1
2840	1	1
2842	1	1
2843	1	1
2845	1	1
2847	1	1
2848	1	1
2849	1	1
2851	1	1
2852	1	1
2853	1	1
2855	1	1
2857	1	1
2859	1	1
2861	1	1
2862	1	1
2864	1	1
2865	1	1
2867	1	1
2868	1	1
2869	1	1
2871	1	1
2872	1	1
2873	1	1
2875	1	1
2876	1	1
2878	1	1
2880	1	1
2882	1	1
2883	1	1
2884	1	1
2886	1	1
2887	1	1
2889	1	1
2890	1	1
2892	1	1
2893	1	1
2895	1	1
2896	1	1
2898	1	1
2899	1	1
2901	1	1
2902	1	1
2904	1	1
2905	1	1
2907	1	1
2908	1	1
2910	1	1
2911	1	1
2913	1	1
2914	1	1
2916	1	1
2917	1	1
2919	1	1
2920	1	1
2922	1	1
2923	1	1
2925	1	1
2926	1	1
2928	1	1
2929	1	1
2931	1	1
2932	1	1
2934	1	1
2935	1	1
2937	1	1
2938	1	1
2939	1	1
2941	1	1
2942	1	1
2943	1	1
2945	1	1
2946	1	1
2949	1	1
2952	1	1
2955	1	1
2958	1	1
2961	1	1
2964	1	1
2967	1	1
2970	1	1
2973	1	1
2976	1	1
2979	1	1
2982	1	1
2985	1	1
2988	1	1
2991	1	1
2994	1	1
2996	1	1
2997	1	1
2999	1	1
3001	1	1
3003	1	1
3004	1	1
3006	1	1
3008	1	1
3010	1	1
3012	1	1
3014	1	1
3016	1	1
3018	1	1
3020	1	1
3022	1	1
3026	1	1
3027	1	1
3028	1	1
3029	1	1
3030	1	1
3031	1	1
3032	1	1
3033	1	1
3034	1	1
3035	1	1
3036	1	1
3037	1	1
3038	1	1
3039	1	1
3040	1	1
3041	1	1
3042	1	1
3043	1	1
3044	1	1
3045	1	1
3046	1	1
3047	1	1
3048	1	1
3049	1	1
3050	1	1
3051	1	1
3052	1	1
3053	1	1
3054	1	1
3055	1	1
3056	1	1
3057	1	1
3058	1	1
3059	1	1
3060	1	1
3061	1	1
3062	1	1
3063	1	1
3064	1	1
3065	1	1
3066	1	1
3067	1	1
3068	1	1
3069	1	1
3070	1	1
3071	1	1
3072	1	1
3073	1	1
3074	1	1
3075	1	1
3076	1	1
3077	1	1
3078	1	1
3079	1	1
3084	1	1
3085	1	1
3087	1	1
3091	1	1
3095	1	1
3099	1	1
3100	1	1
3104	1	1
3108	1	1
3112	1	1
3113	1	1
3114	1	1
3115	1	1
3119	1	1
3123	1	1
3127	1	1
3131	1	1
3135	1	1
3136	1	1
3137	1	1
3141	1	1
3145	1	1
3149	1	1
3153	1	1
3157	1	1
3161	1	1
3165	1	1
3169	1	1
3173	1	1
3177	1	1
3181	1	1
3185	1	1
3189	1	1
3193	1	1
3197	1	1
3201	1	1
3205	1	1
3209	1	1
3213	1	1
3217	1	1
3221	1	1
3225	1	1
3229	1	1
3233	1	1
3237	1	1
3241	1	1
3245	1	1
3249	1	1
3253	1	1
3257	1	1
3261	1	1
3265	1	1
3269	1	1
3273	1	1
3277	1	1
3281	1	1
3285	1	1
3289	1	1
3293	1	1
3294	1	1
3295	1	1
3299	1	1
3300	1	1
3301	1	1
3302	1	1
3303	1	1
3304	1	1
3305	1	1
3306	1	1
3307	1	1
3308	1	1
3309	1	1
3310	1	1
3311	1	1
3312	1	1
3316	1	1
3317	1	1
3318	1	1
3319	1	1
3320	1	1
3321	1	1
3322	1	1
3323	1	1
3324	1	1
3338	1	1
3339	1	1
3341	1	1
3346	1	1
3347	1	1
3349	1	1
3354	1	1
3357	1	1
3365	1	1
3375	1	1
3383	1	1
3384	1	1

---

Cond Coverage for Module : keymgr_dpe_reg_top

	Total	Covered	Percent
Conditions	643	612	95.18
Logical	643	612	95.18
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
65-2843	94.63
2848-3354	96.28

---

Branch Coverage for Module : keymgr_dpe_reg_top

	Line No.	Total	Covered	Percent
Branches		63	63	100.00
TERNARY	2773	2	2	100.00
IF	75	3	3	100.00
CASE	3085	54	54	100.00
IF	3338	2	2	100.00
IF	3346	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_dpe_0.1/rtl/keymgr_dpe_reg_top.sv' or '../src/lowrisc_ip_keymgr_dpe_0.1/rtl/keymgr_dpe_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	2773	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	75	if ((!rst_ni))
-2-:	77	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T5,T6,T7
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	3085	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T2,T3,T4
addr_hit[2]	Covered	T2,T3,T4
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T2,T3,T4
addr_hit[5]	Covered	T2,T3,T4
addr_hit[6]	Covered	T2,T3,T4
addr_hit[7]	Covered	T2,T3,T4
addr_hit[8]	Covered	T2,T3,T4
addr_hit[9]	Covered	T2,T3,T4
addr_hit[10]	Covered	T2,T3,T4
addr_hit[11]	Covered	T1,T2,T3
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T2,T3,T4
addr_hit[14]	Covered	T1,T2,T3
addr_hit[15]	Covered	T2,T3,T4
addr_hit[16]	Covered	T1,T2,T3
addr_hit[17]	Covered	T2,T3,T4
addr_hit[18]	Covered	T2,T3,T4
addr_hit[19]	Covered	T2,T3,T4
addr_hit[20]	Covered	T2,T3,T4
addr_hit[21]	Covered	T2,T3,T4
addr_hit[22]	Covered	T2,T3,T4
addr_hit[23]	Covered	T2,T3,T4
addr_hit[24]	Covered	T1,T2,T3
addr_hit[25]	Covered	T2,T3,T4
addr_hit[26]	Covered	T1,T2,T3
addr_hit[27]	Covered	T2,T3,T4
addr_hit[28]	Covered	T2,T3,T4
addr_hit[29]	Covered	T2,T3,T4
addr_hit[30]	Covered	T1,T2,T3
addr_hit[31]	Covered	T1,T2,T3
addr_hit[32]	Covered	T2,T3,T4
addr_hit[33]	Covered	T2,T3,T4
addr_hit[34]	Covered	T1,T2,T3
addr_hit[35]	Covered	T1,T2,T3
addr_hit[36]	Covered	T1,T2,T3
addr_hit[37]	Covered	T1,T2,T3
addr_hit[38]	Covered	T1,T2,T3
addr_hit[39]	Covered	T2,T3,T4
addr_hit[40]	Covered	T2,T3,T4
addr_hit[41]	Covered	T2,T3,T4
addr_hit[42]	Covered	T2,T3,T4
addr_hit[43]	Covered	T2,T3,T4
addr_hit[44]	Covered	T2,T3,T4
addr_hit[45]	Covered	T2,T3,T4
addr_hit[46]	Covered	T1,T2,T3
addr_hit[47]	Covered	T2,T3,T4
addr_hit[48]	Covered	T1,T2,T3
addr_hit[49]	Covered	T2,T3,T4
addr_hit[50]	Covered	T2,T3,T4
addr_hit[51]	Covered	T2,T3,T4
addr_hit[52]	Covered	T2,T3,T4
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	3338	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	3346	if ((!rst_shadowed_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : keymgr_dpe_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	9917020	1264099	0	0
reAfterRv	9917020	1264098	0	0
rePulse	9917020	1127212	0	0
wePulse	9917020	136886	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	9917020	1264099	0	0
T1	1021	20	0	0
T2	69502	6491	0	0
T3	55023	5011	0	0
T4	25577	7998	0	0
T5	19392	1255	0	0
T6	35485	2805	0	0
T8	33528	8728	0	0
T15	1036	20	0	0
T16	1699	21	0	0
T17	1161	13	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	9917020	1264098	0	0
T1	1021	20	0	0
T2	69502	6491	0	0
T3	55023	5011	0	0
T4	25577	7998	0	0
T5	19392	1255	0	0
T6	35485	2805	0	0
T8	33528	8728	0	0
T15	1036	20	0	0
T16	1699	21	0	0
T17	1161	13	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	9917020	1127212	0	0
T1	1021	1	0	0
T2	69502	4786	0	0
T3	55023	3869	0	0
T4	25577	6731	0	0
T5	19392	713	0	0
T6	35485	1713	0	0
T8	33528	7344	0	0
T15	1036	1	0	0
T16	1699	1	0	0
T17	1161	1	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	9917020	136886	0	0
T1	1021	19	0	0
T2	69502	1705	0	0
T3	55023	1142	0	0
T4	25577	1267	0	0
T5	19392	542	0	0
T6	35485	1092	0	0
T8	33528	1384	0	0
T15	1036	19	0	0
T16	1699	20	0	0
T17	1161	12	0	0