Unified Coverage Report :: Module :: keymgr_dpe_csr_assert_fpv

Module : keymgr_dpe_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_dpe_csr_assert_0/keymgr_dpe_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_dpe_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_dpe_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.39	100.00	80.22	53.88		97.83	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_dpe_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	22	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	22	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	9917020	10275	0	0
intr_enable_rd_A	9917020	2010	0	0
key_version_rd_A	9917020	1823	0	0
reseed_interval_regwen_rd_A	9917020	969	0	0
salt_0_rd_A	9917020	1968	0	0
salt_1_rd_A	9917020	1711	0	0
salt_2_rd_A	9917020	1768	0	0
salt_3_rd_A	9917020	1868	0	0
salt_4_rd_A	9917020	1938	0	0
salt_5_rd_A	9917020	1955	0	0
salt_6_rd_A	9917020	1805	0	0
salt_7_rd_A	9917020	1859	0	0
sideload_clear_rd_A	9917020	1721	0	0
slot_policy_rd_A	9917020	2660	0	0
sw_binding_0_rd_A	9917020	1812	0	0
sw_binding_1_rd_A	9917020	1738	0	0
sw_binding_2_rd_A	9917020	1710	0	0
sw_binding_3_rd_A	9917020	1881	0	0
sw_binding_4_rd_A	9917020	1783	0	0
sw_binding_5_rd_A	9917020	1788	0	0
sw_binding_6_rd_A	9917020	1962	0	0
sw_binding_7_rd_A	9917020	1909	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9917020	10275	0	0
T18	2870	26	0	0
T19	16296	389	0	0
T20	1136	7	0	0
T24	8134	4	0	0
T25	1733	148	0	0
T26	10386	4	0	0
T27	0	1	0	0
T28	0	356	0	0
T57	15561	0	0	0
T59	6823	0	0	0
T60	864	0	0	0
T61	894	7	0	0
T67	0	12	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9917020	2010	0	0
T19	16296	11	0	0
T30	25516	160	0	0
T36	1249	20	0	0
T57	15561	35	0	0
T58	6581	0	0	0
T60	864	0	0	0
T61	894	0	0	0
T62	880	0	0	0
T63	6471	0	0	0
T67	0	9	0	0
T68	0	84	0	0
T79	29296	341	0	0
T91	0	8	0	0
T92	0	45	0	0
T93	0	14	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9917020	1823	0	0
T19	16296	13	0	0
T30	25516	167	0	0
T57	15561	33	0	0
T58	6581	0	0	0
T60	864	0	0	0
T61	894	0	0	0
T62	880	0	0	0
T63	6471	0	0	0
T67	0	11	0	0
T68	0	69	0	0
T79	29296	339	0	0
T92	0	22	0	0
T93	0	4	0	0
T94	0	7	0	0
T95	0	52	0	0
T96	3756	0	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9917020	969	0	0
T19	16296	25	0	0
T30	25516	28	0	0
T57	15561	53	0	0
T58	6581	0	0	0
T60	864	0	0	0
T61	894	0	0	0
T62	880	0	0	0
T63	6471	0	0	0
T67	0	19	0	0
T68	0	27	0	0
T79	29296	319	0	0
T92	0	15	0	0
T93	0	12	0	0
T95	0	26	0	0
T96	3756	0	0	0
T97	0	21	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9917020	1968	0	0
T19	16296	31	0	0
T30	25516	155	0	0
T57	15561	37	0	0
T58	6581	0	0	0
T60	864	0	0	0
T61	894	0	0	0
T62	880	0	0	0
T63	6471	0	0	0
T67	0	7	0	0
T68	0	107	0	0
T79	29296	348	0	0
T92	0	66	0	0
T93	0	5	0	0
T94	0	7	0	0
T95	0	104	0	0
T96	3756	0	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9917020	1711	0	0
T19	16296	14	0	0
T30	25516	168	0	0
T57	15561	34	0	0
T58	6581	0	0	0
T60	864	0	0	0
T61	894	0	0	0
T62	880	0	0	0
T63	6471	0	0	0
T67	0	11	0	0
T68	0	76	0	0
T79	29296	354	0	0
T92	0	35	0	0
T93	0	3	0	0
T94	0	7	0	0
T95	0	66	0	0
T96	3756	0	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9917020	1768	0	0
T30	25516	142	0	0
T57	15561	25	0	0
T58	6581	0	0	0
T60	864	0	0	0
T61	894	0	0	0
T62	880	0	0	0
T63	6471	0	0	0
T67	0	3	0	0
T68	0	86	0	0
T79	29296	333	0	0
T82	28672	0	0	0
T92	0	41	0	0
T93	0	2	0	0
T94	0	13	0	0
T95	0	91	0	0
T96	3756	0	0	0
T98	0	3	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9917020	1868	0	0
T19	16296	18	0	0
T30	25516	157	0	0
T57	15561	38	0	0
T58	6581	0	0	0
T60	864	0	0	0
T61	894	0	0	0
T62	880	0	0	0
T63	6471	0	0	0
T67	0	11	0	0
T68	0	80	0	0
T79	29296	390	0	0
T92	0	47	0	0
T93	0	11	0	0
T94	0	7	0	0
T95	0	94	0	0
T96	3756	0	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9917020	1938	0	0
T19	16296	17	0	0
T30	25516	166	0	0
T57	15561	25	0	0
T58	6581	0	0	0
T60	864	0	0	0
T61	894	0	0	0
T62	880	0	0	0
T63	6471	0	0	0
T67	0	8	0	0
T68	0	102	0	0
T79	29296	411	0	0
T92	0	39	0	0
T93	0	5	0	0
T94	0	16	0	0
T95	0	105	0	0
T96	3756	0	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9917020	1955	0	0
T19	16296	25	0	0
T30	25516	182	0	0
T57	15561	44	0	0
T58	6581	0	0	0
T60	864	0	0	0
T61	894	0	0	0
T62	880	0	0	0
T63	6471	0	0	0
T67	0	11	0	0
T68	0	77	0	0
T79	29296	405	0	0
T92	0	41	0	0
T93	0	7	0	0
T94	0	12	0	0
T95	0	85	0	0
T96	3756	0	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9917020	1805	0	0
T19	16296	18	0	0
T30	25516	166	0	0
T57	15561	27	0	0
T58	6581	0	0	0
T60	864	0	0	0
T61	894	0	0	0
T62	880	0	0	0
T63	6471	0	0	0
T67	0	17	0	0
T68	0	95	0	0
T79	29296	332	0	0
T92	0	46	0	0
T94	0	15	0	0
T95	0	98	0	0
T96	3756	0	0	0
T98	0	9	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9917020	1859	0	0
T19	16296	26	0	0
T30	25516	187	0	0
T57	15561	43	0	0
T58	6581	0	0	0
T60	864	0	0	0
T61	894	0	0	0
T62	880	0	0	0
T63	6471	0	0	0
T67	0	10	0	0
T68	0	80	0	0
T79	29296	372	0	0
T92	0	33	0	0
T93	0	5	0	0
T94	0	12	0	0
T95	0	88	0	0
T96	3756	0	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9917020	1721	0	0
T19	16296	19	0	0
T30	25516	156	0	0
T57	15561	31	0	0
T58	6581	0	0	0
T60	864	0	0	0
T61	894	0	0	0
T62	880	0	0	0
T63	6471	0	0	0
T67	0	8	0	0
T68	0	101	0	0
T79	29296	309	0	0
T92	0	28	0	0
T93	0	6	0	0
T94	0	4	0	0
T95	0	103	0	0
T96	3756	0	0	0

slot_policy_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9917020	2660	0	0
T19	16296	28	0	0
T30	25516	338	0	0
T57	15561	32	0	0
T58	6581	0	0	0
T60	864	0	0	0
T61	894	0	0	0
T62	880	0	0	0
T63	6471	0	0	0
T67	0	7	0	0
T68	0	132	0	0
T79	29296	336	0	0
T92	0	84	0	0
T93	0	7	0	0
T94	0	34	0	0
T95	0	106	0	0
T96	3756	0	0	0

sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9917020	1812	0	0
T19	16296	24	0	0
T30	25516	163	0	0
T57	15561	65	0	0
T58	6581	0	0	0
T60	864	0	0	0
T61	894	0	0	0
T62	880	0	0	0
T63	6471	0	0	0
T67	0	1	0	0
T68	0	104	0	0
T79	29296	322	0	0
T92	0	39	0	0
T93	0	5	0	0
T94	0	11	0	0
T95	0	82	0	0
T96	3756	0	0	0

sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9917020	1738	0	0
T19	16296	46	0	0
T30	25516	152	0	0
T57	15561	56	0	0
T58	6581	0	0	0
T60	864	0	0	0
T61	894	0	0	0
T62	880	0	0	0
T63	6471	0	0	0
T67	0	3	0	0
T68	0	67	0	0
T79	29296	352	0	0
T92	0	34	0	0
T93	0	21	0	0
T94	0	6	0	0
T95	0	52	0	0
T96	3756	0	0	0

sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9917020	1710	0	0
T19	16296	14	0	0
T30	25516	120	0	0
T57	15561	38	0	0
T58	6581	0	0	0
T60	864	0	0	0
T61	894	0	0	0
T62	880	0	0	0
T63	6471	0	0	0
T67	0	8	0	0
T68	0	88	0	0
T79	29296	341	0	0
T92	0	78	0	0
T94	0	4	0	0
T95	0	79	0	0
T96	3756	0	0	0
T98	0	1	0	0

sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9917020	1881	0	0
T19	16296	26	0	0
T30	25516	153	0	0
T57	15561	31	0	0
T58	6581	0	0	0
T60	864	0	0	0
T61	894	0	0	0
T62	880	0	0	0
T63	6471	0	0	0
T67	0	2	0	0
T68	0	94	0	0
T79	29296	378	0	0
T92	0	65	0	0
T93	0	5	0	0
T94	0	13	0	0
T95	0	66	0	0
T96	3756	0	0	0

sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9917020	1783	0	0
T19	16296	2	0	0
T30	25516	161	0	0
T57	15561	51	0	0
T58	6581	0	0	0
T60	864	0	0	0
T61	894	0	0	0
T62	880	0	0	0
T63	6471	0	0	0
T67	0	2	0	0
T68	0	77	0	0
T79	29296	365	0	0
T92	0	18	0	0
T93	0	7	0	0
T94	0	13	0	0
T95	0	85	0	0
T96	3756	0	0	0

sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9917020	1788	0	0
T19	16296	42	0	0
T30	25516	178	0	0
T57	15561	22	0	0
T58	6581	0	0	0
T60	864	0	0	0
T61	894	0	0	0
T62	880	0	0	0
T63	6471	0	0	0
T67	0	7	0	0
T68	0	85	0	0
T79	29296	345	0	0
T92	0	40	0	0
T94	0	3	0	0
T95	0	65	0	0
T96	3756	0	0	0
T98	0	5	0	0

sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9917020	1962	0	0
T19	16296	8	0	0
T30	25516	169	0	0
T57	15561	46	0	0
T58	6581	0	0	0
T60	864	0	0	0
T61	894	0	0	0
T62	880	0	0	0
T63	6471	0	0	0
T67	0	11	0	0
T68	0	96	0	0
T79	29296	368	0	0
T92	0	45	0	0
T93	0	3	0	0
T94	0	9	0	0
T95	0	119	0	0
T96	3756	0	0	0

sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9917020	1909	0	0
T19	16296	39	0	0
T30	25516	185	0	0
T57	15561	42	0	0
T58	6581	0	0	0
T60	864	0	0	0
T61	894	0	0	0
T62	880	0	0	0
T63	6471	0	0	0
T67	0	13	0	0
T68	0	103	0	0
T79	29296	334	0	0
T92	0	49	0	0
T93	0	8	0	0
T94	0	10	0	0
T95	0	117	0	0
T96	3756	0	0	0