Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	913107	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

246743

1

T1

3397

T2

8

T3

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1017453	1			T1	40196		T2	1		T3	1
values[0x0]	70544	1			T1	783		T2	10		T3	10
values[0x1]	71853	1			T1	779		T2	3		T3	15

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	624307	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

535543

1

T1

15903

T2

8

T3

6

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2723	1			T4	32		T5	1		T8	24
valid_sources[0x01]	2670	1			T4	23		T5	3		T8	30
valid_sources[0x02]	3169	1			T4	21		T5	8		T8	25
valid_sources[0x03]	2675	1			T4	30		T5	5		T8	38
valid_sources[0x04]	2846	1			T4	34		T5	5		T8	26
valid_sources[0x05]	2819	1			T3	1		T4	20		T5	6
valid_sources[0x06]	2394	1			T4	14		T5	7		T8	28
valid_sources[0x07]	3032	1			T4	23		T5	4		T8	22
valid_sources[0x08]	2855	1			T4	26		T5	9		T8	13
valid_sources[0x09]	2789	1			T4	30		T5	9		T8	34
valid_sources[0x0a]	2825	1			T4	31		T5	7		T8	22
valid_sources[0x0b]	2619	1			T3	1		T4	27		T5	3
valid_sources[0x0c]	2625	1			T4	18		T5	6		T8	23
valid_sources[0x0d]	2724	1			T4	25		T5	3		T8	24
valid_sources[0x0e]	9323	1			T4	20		T5	6		T8	28
valid_sources[0x0f]	2886	1			T4	26		T5	7		T8	20
valid_sources[0x10]	3156	1			T4	29		T5	5		T8	38
valid_sources[0x11]	3073	1			T4	27		T5	3		T8	29
valid_sources[0x12]	2801	1			T4	21		T5	8		T8	24
valid_sources[0x13]	10945	1			T4	15		T5	5		T8	43
valid_sources[0x14]	3031	1			T4	15		T5	3		T8	25
valid_sources[0x15]	2473	1			T4	21		T5	5		T8	31
valid_sources[0x16]	2816	1			T4	22		T5	5		T8	29
valid_sources[0x17]	2624	1			T4	23		T5	9		T8	28
valid_sources[0x18]	2573	1			T4	27		T5	5		T8	26
valid_sources[0x19]	2907	1			T4	24		T5	3		T8	33
valid_sources[0x1a]	2526	1			T4	27		T5	3		T8	40
valid_sources[0x1b]	2783	1			T4	17		T5	4		T8	28
valid_sources[0x1c]	2762	1			T4	27		T5	4		T8	41
valid_sources[0x1d]	2717	1			T4	21		T5	9		T8	17
valid_sources[0x1e]	2916	1			T4	14		T5	4		T8	34
valid_sources[0x1f]	3406	1			T3	1		T4	15		T5	3
valid_sources[0x20]	2765	1			T4	27		T5	2		T8	17
valid_sources[0x21]	2722	1			T4	23		T5	7		T8	19
valid_sources[0x22]	3227	1			T4	21		T5	7		T8	36
valid_sources[0x23]	2663	1			T4	25		T5	8		T8	20
valid_sources[0x24]	5038	1			T3	1		T4	22		T5	8
valid_sources[0x25]	2704	1			T4	29		T5	6		T8	23
valid_sources[0x26]	2660	1			T4	24		T5	5		T8	37
valid_sources[0x27]	2913	1			T4	38		T5	6		T8	29
valid_sources[0x28]	2944	1			T4	24		T5	4		T8	25
valid_sources[0x29]	2674	1			T4	21		T5	6		T8	25
valid_sources[0x2a]	2718	1			T4	27		T5	5		T8	28
valid_sources[0x2b]	2793	1			T4	26		T5	6		T8	26
valid_sources[0x2c]	7802	1			T4	24		T5	7		T8	32
valid_sources[0x2d]	3105	1			T4	27		T5	5		T8	27
valid_sources[0x2e]	2986	1			T4	23		T5	2		T8	25
valid_sources[0x2f]	4626	1			T4	21		T5	3		T8	24
valid_sources[0x30]	2827	1			T4	19		T5	3		T8	33
valid_sources[0x31]	2682	1			T4	33		T5	5		T8	23
valid_sources[0x32]	3049	1			T4	30		T5	6		T8	33
valid_sources[0x33]	3220	1			T4	28		T5	6		T8	29
valid_sources[0x34]	2806	1			T4	20		T5	4		T8	20
valid_sources[0x35]	2871	1			T4	33		T5	5		T8	16
valid_sources[0x36]	3153	1			T4	19		T5	7		T8	34
valid_sources[0x37]	2572	1			T4	19		T5	3		T8	24
valid_sources[0x38]	2794	1			T4	28		T5	11		T8	32
valid_sources[0x39]	2812	1			T4	21		T5	5		T8	38
valid_sources[0x3a]	2836	1			T4	25		T5	4		T8	30
valid_sources[0x3b]	2761	1			T4	10		T5	9		T8	19
valid_sources[0x3c]	2630	1			T4	17		T5	5		T8	22
valid_sources[0x3d]	2978	1			T4	33		T5	5		T8	45
valid_sources[0x3e]	2970	1			T4	25		T5	2		T8	24
valid_sources[0x3f]	2733	1			T4	19		T5	2		T8	26
valid_sources[0x40]	35278	1			T4	19		T5	6		T8	27
valid_sources[0x41]	5101	1			T4	29		T5	7		T8	17
valid_sources[0x42]	2747	1			T4	21		T5	5		T8	35
valid_sources[0x43]	2901	1			T4	33		T5	4		T8	23
valid_sources[0x44]	2896	1			T4	29		T5	5		T8	17
valid_sources[0x45]	21240	1			T4	22		T5	6		T8	15
valid_sources[0x46]	2914	1			T4	32		T5	5		T8	25
valid_sources[0x47]	2718	1			T3	1		T4	24		T5	7
valid_sources[0x48]	2579	1			T3	1		T4	18		T8	25
valid_sources[0x49]	2903	1			T4	23		T5	4		T8	35
valid_sources[0x4a]	2982	1			T4	23		T5	4		T8	30
valid_sources[0x4b]	2568	1			T4	34		T5	2		T8	22
valid_sources[0x4c]	3006	1			T4	26		T5	4		T8	24
valid_sources[0x4d]	3021	1			T4	17		T5	8		T8	26
valid_sources[0x4e]	2937	1			T4	29		T5	4		T8	32
valid_sources[0x4f]	3064	1			T4	25		T5	9		T8	32
valid_sources[0x50]	3063	1			T4	25		T5	3		T8	15
valid_sources[0x51]	2648	1			T4	27		T5	3		T8	31
valid_sources[0x52]	3110	1			T3	1		T4	26		T5	5
valid_sources[0x53]	5879	1			T4	31		T5	6		T8	25
valid_sources[0x54]	3029	1			T4	27		T5	5		T8	39
valid_sources[0x55]	2797	1			T4	20		T5	7		T8	26
valid_sources[0x56]	3322	1			T4	14		T5	4		T8	26
valid_sources[0x57]	2706	1			T4	22		T5	7		T8	29
valid_sources[0x58]	2846	1			T4	22		T5	4		T8	28
valid_sources[0x59]	2650	1			T4	21		T5	5		T8	14
valid_sources[0x5a]	2720	1			T3	1		T4	20		T5	3
valid_sources[0x5b]	2487	1			T4	29		T5	2		T8	34
valid_sources[0x5c]	2728	1			T4	26		T5	5		T8	30
valid_sources[0x5d]	2738	1			T3	1		T4	14		T5	5
valid_sources[0x5e]	2678	1			T4	16		T5	10		T8	31
valid_sources[0x5f]	2623	1			T4	28		T5	9		T8	33
valid_sources[0x60]	2601	1			T4	22		T5	5		T8	44
valid_sources[0x61]	2708	1			T2	14		T4	25		T5	5
valid_sources[0x62]	2880	1			T3	1		T4	35		T5	2
valid_sources[0x63]	2802	1			T4	28		T5	5		T8	19
valid_sources[0x64]	3221	1			T4	26		T5	5		T8	26
valid_sources[0x65]	13681	1			T1	10943		T3	1		T4	17
valid_sources[0x66]	2772	1			T4	28		T5	8		T8	26
valid_sources[0x67]	2638	1			T4	21		T5	1		T8	25
valid_sources[0x68]	2768	1			T4	25		T5	5		T8	11
valid_sources[0x69]	3511	1			T3	1		T4	24		T5	7
valid_sources[0x6a]	2791	1			T4	27		T5	6		T8	21
valid_sources[0x6b]	2784	1			T4	25		T5	2		T8	23
valid_sources[0x6c]	2662	1			T4	22		T5	7		T8	25
valid_sources[0x6d]	2976	1			T4	21		T5	6		T8	20
valid_sources[0x6e]	2728	1			T4	25		T5	5		T8	17
valid_sources[0x6f]	2931	1			T4	23		T5	2		T8	23
valid_sources[0x70]	2955	1			T4	25		T5	6		T8	28
valid_sources[0x71]	2750	1			T4	18		T5	1		T8	20
valid_sources[0x72]	3035	1			T4	21		T5	10		T8	33
valid_sources[0x73]	32369	1			T1	29468		T4	30		T5	2
valid_sources[0x74]	2740	1			T3	3		T4	25		T5	6
valid_sources[0x75]	2661	1			T4	22		T5	3		T8	24
valid_sources[0x76]	2465	1			T4	19		T5	1		T8	19
valid_sources[0x77]	2840	1			T4	24		T5	4		T8	17
valid_sources[0x78]	2880	1			T4	19		T5	5		T8	27
valid_sources[0x79]	2962	1			T4	20		T5	8		T8	25
valid_sources[0x7a]	2555	1			T4	29		T5	4		T8	13
valid_sources[0x7b]	2893	1			T4	23		T5	5		T8	28
valid_sources[0x7c]	2628	1			T4	29		T5	6		T8	33
valid_sources[0x7d]	2684	1			T4	19		T5	5		T8	37
valid_sources[0x7e]	2703	1			T4	27		T5	6		T8	31
valid_sources[0x7f]	2836	1			T4	33		T8	30		T6	2
valid_sources[0x80]	2954	1			T4	17		T5	4		T8	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

137875

1

T1

2281

T4

2105

T5

314

values[0x0]

all_enables

biggest_size

57935

1

T1

605

T2

7

T3

1

values[0x1]

all_enables

biggest_size

50933

1

T1

511

T2

1

T3

3