Unified Coverage Report :: Module :: keymgr_dpe_csr_assert_fpv

Module : keymgr_dpe_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_dpe_csr_assert_0/keymgr_dpe_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_dpe_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_dpe_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.39	100.00	80.22	53.88		97.83	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_dpe_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	22	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	22	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	8038535	9757	0	0
intr_enable_rd_A	8038535	2454	0	0
key_version_rd_A	8038535	2166	0	0
reseed_interval_regwen_rd_A	8038535	1056	0	0
salt_0_rd_A	8038535	2153	0	0
salt_1_rd_A	8038535	1970	0	0
salt_2_rd_A	8038535	2155	0	0
salt_3_rd_A	8038535	2115	0	0
salt_4_rd_A	8038535	2115	0	0
salt_5_rd_A	8038535	2080	0	0
salt_6_rd_A	8038535	2130	0	0
salt_7_rd_A	8038535	2121	0	0
sideload_clear_rd_A	8038535	2242	0	0
slot_policy_rd_A	8038535	2612	0	0
sw_binding_0_rd_A	8038535	2133	0	0
sw_binding_1_rd_A	8038535	2210	0	0
sw_binding_2_rd_A	8038535	2079	0	0
sw_binding_3_rd_A	8038535	2185	0	0
sw_binding_4_rd_A	8038535	2212	0	0
sw_binding_5_rd_A	8038535	2235	0	0
sw_binding_6_rd_A	8038535	2202	0	0
sw_binding_7_rd_A	8038535	2180	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8038535	9757	0	0
T18	7356	3	0	0
T19	2137	15	0	0
T20	1903	18	0	0
T28	3965	666	0	0
T29	11906	585	0	0
T30	0	7	0	0
T31	12605	3	0	0
T36	0	1	0	0
T46	0	5	0	0
T64	1511	0	0	0
T65	2079	0	0	0
T66	1336	0	0	0
T67	7556	0	0	0
T68	0	2	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8038535	2454	0	0
T19	2137	2	0	0
T28	3965	0	0	0
T29	11906	0	0	0
T32	0	2	0	0
T34	12618	55	0	0
T38	884	19	0	0
T64	1511	4	0	0
T65	2079	0	0	0
T66	1336	0	0	0
T67	7556	24	0	0
T72	0	1	0	0
T83	0	136	0	0
T84	0	88	0	0
T91	965	5	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8038535	2166	0	0
T19	2137	14	0	0
T28	3965	0	0	0
T29	11906	0	0	0
T32	0	5	0	0
T34	12618	52	0	0
T54	0	30	0	0
T64	1511	2	0	0
T65	2079	0	0	0
T66	1336	0	0	0
T67	7556	21	0	0
T68	1407	0	0	0
T69	930	0	0	0
T72	0	3	0	0
T83	0	160	0	0
T84	0	35	0	0
T92	0	9	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8038535	1056	0	0
T19	2137	14	0	0
T28	3965	0	0	0
T29	11906	0	0	0
T30	17265	0	0	0
T32	0	15	0	0
T34	12618	26	0	0
T36	16861	0	0	0
T46	7740	0	0	0
T67	7556	24	0	0
T68	1407	0	0	0
T69	930	0	0	0
T83	0	26	0	0
T84	0	40	0	0
T92	0	2	0	0
T93	0	5	0	0
T94	0	3	0	0
T95	0	15	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8038535	2153	0	0
T28	3965	0	0	0
T29	11906	0	0	0
T30	17265	0	0	0
T34	12618	57	0	0
T54	0	27	0	0
T64	1511	2	0	0
T65	2079	0	0	0
T66	1336	0	0	0
T67	7556	43	0	0
T68	1407	0	0	0
T69	930	0	0	0
T72	0	1	0	0
T83	0	133	0	0
T84	0	41	0	0
T92	0	5	0	0
T93	0	1	0	0
T96	0	6	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8038535	1970	0	0
T19	2137	10	0	0
T28	3965	0	0	0
T29	11906	0	0	0
T32	0	8	0	0
T34	12618	49	0	0
T54	0	16	0	0
T64	1511	1	0	0
T65	2079	0	0	0
T66	1336	0	0	0
T67	7556	25	0	0
T68	1407	0	0	0
T69	930	0	0	0
T72	0	5	0	0
T83	0	162	0	0
T84	0	23	0	0
T92	0	5	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8038535	2155	0	0
T19	2137	8	0	0
T28	3965	0	0	0
T29	11906	0	0	0
T32	0	6	0	0
T34	12618	47	0	0
T54	0	19	0	0
T64	1511	1	0	0
T65	2079	0	0	0
T66	1336	0	0	0
T67	7556	32	0	0
T68	1407	0	0	0
T69	930	0	0	0
T72	0	1	0	0
T83	0	152	0	0
T84	0	29	0	0
T92	0	2	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8038535	2115	0	0
T19	2137	19	0	0
T28	3965	0	0	0
T29	11906	0	0	0
T32	0	9	0	0
T34	12618	62	0	0
T54	0	27	0	0
T64	1511	7	0	0
T65	2079	0	0	0
T66	1336	0	0	0
T67	7556	28	0	0
T68	1407	0	0	0
T69	930	0	0	0
T72	0	9	0	0
T83	0	122	0	0
T84	0	37	0	0
T92	0	1	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8038535	2115	0	0
T19	2137	4	0	0
T28	3965	0	0	0
T29	11906	0	0	0
T30	17265	0	0	0
T34	12618	57	0	0
T36	16861	0	0	0
T46	7740	0	0	0
T54	0	11	0	0
T67	7556	24	0	0
T68	1407	0	0	0
T69	930	0	0	0
T72	0	8	0	0
T83	0	161	0	0
T84	0	75	0	0
T92	0	9	0	0
T93	0	3	0	0
T96	0	2	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8038535	2080	0	0
T19	2137	4	0	0
T28	3965	0	0	0
T29	11906	0	0	0
T34	12618	37	0	0
T54	0	20	0	0
T64	1511	3	0	0
T65	2079	0	0	0
T66	1336	0	0	0
T67	7556	20	0	0
T68	1407	0	0	0
T69	930	0	0	0
T72	0	9	0	0
T83	0	164	0	0
T84	0	40	0	0
T92	0	1	0	0
T96	0	6	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8038535	2130	0	0
T19	2137	11	0	0
T28	3965	0	0	0
T29	11906	0	0	0
T32	0	11	0	0
T34	12618	48	0	0
T54	0	21	0	0
T64	1511	6	0	0
T65	2079	0	0	0
T66	1336	0	0	0
T67	7556	25	0	0
T68	1407	0	0	0
T69	930	0	0	0
T72	0	6	0	0
T83	0	131	0	0
T84	0	69	0	0
T92	0	7	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8038535	2121	0	0
T19	2137	7	0	0
T28	3965	0	0	0
T29	11906	0	0	0
T32	0	7	0	0
T34	12618	38	0	0
T54	0	23	0	0
T64	1511	2	0	0
T65	2079	0	0	0
T66	1336	0	0	0
T67	7556	34	0	0
T68	1407	0	0	0
T69	930	0	0	0
T72	0	4	0	0
T83	0	135	0	0
T84	0	49	0	0
T92	0	1	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8038535	2242	0	0
T19	2137	14	0	0
T28	3965	0	0	0
T29	11906	0	0	0
T32	0	20	0	0
T34	12618	71	0	0
T54	0	21	0	0
T64	1511	7	0	0
T65	2079	0	0	0
T66	1336	0	0	0
T67	7556	19	0	0
T68	1407	0	0	0
T69	930	0	0	0
T72	0	3	0	0
T83	0	130	0	0
T84	0	52	0	0
T92	0	5	0	0

slot_policy_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8038535	2612	0	0
T19	2137	6	0	0
T28	3965	0	0	0
T29	11906	0	0	0
T32	0	1	0	0
T34	12618	80	0	0
T54	0	46	0	0
T64	1511	3	0	0
T65	2079	0	0	0
T66	1336	0	0	0
T67	7556	36	0	0
T68	1407	0	0	0
T69	930	0	0	0
T72	0	5	0	0
T83	0	242	0	0
T84	0	24	0	0
T92	0	1	0	0

sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8038535	2133	0	0
T19	2137	16	0	0
T28	3965	0	0	0
T29	11906	0	0	0
T30	17265	0	0	0
T32	0	11	0	0
T34	12618	76	0	0
T36	16861	0	0	0
T46	7740	0	0	0
T54	0	18	0	0
T67	7556	22	0	0
T68	1407	0	0	0
T69	930	0	0	0
T72	0	2	0	0
T83	0	146	0	0
T84	0	26	0	0
T92	0	3	0	0
T96	0	3	0	0

sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8038535	2210	0	0
T19	2137	7	0	0
T28	3965	0	0	0
T29	11906	0	0	0
T34	12618	44	0	0
T54	0	10	0	0
T64	1511	8	0	0
T65	2079	0	0	0
T66	1336	0	0	0
T67	7556	42	0	0
T68	1407	0	0	0
T69	930	0	0	0
T72	0	2	0	0
T83	0	162	0	0
T84	0	23	0	0
T92	0	2	0	0
T96	0	3	0	0

sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8038535	2079	0	0
T19	2137	5	0	0
T28	3965	0	0	0
T29	11906	0	0	0
T34	12618	43	0	0
T54	0	14	0	0
T64	1511	5	0	0
T65	2079	0	0	0
T66	1336	0	0	0
T67	7556	23	0	0
T68	1407	0	0	0
T69	930	0	0	0
T83	0	153	0	0
T84	0	76	0	0
T94	0	3	0	0
T96	0	3	0	0
T97	0	4	0	0

sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8038535	2185	0	0
T19	2137	2	0	0
T28	3965	0	0	0
T29	11906	0	0	0
T32	0	14	0	0
T34	12618	44	0	0
T54	0	12	0	0
T64	1511	5	0	0
T65	2079	0	0	0
T66	1336	0	0	0
T67	7556	30	0	0
T68	1407	0	0	0
T69	930	0	0	0
T72	0	7	0	0
T83	0	136	0	0
T84	0	23	0	0
T92	0	4	0	0

sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8038535	2212	0	0
T19	2137	8	0	0
T28	3965	0	0	0
T29	11906	0	0	0
T30	17265	0	0	0
T32	0	14	0	0
T34	12618	44	0	0
T36	16861	0	0	0
T46	7740	0	0	0
T54	0	28	0	0
T67	7556	33	0	0
T68	1407	0	0	0
T69	930	0	0	0
T72	0	6	0	0
T83	0	133	0	0
T84	0	12	0	0
T92	0	4	0	0
T96	0	7	0	0

sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8038535	2235	0	0
T19	2137	9	0	0
T28	3965	0	0	0
T29	11906	0	0	0
T32	0	20	0	0
T34	12618	48	0	0
T54	0	23	0	0
T64	1511	3	0	0
T65	2079	0	0	0
T66	1336	0	0	0
T67	7556	25	0	0
T68	1407	0	0	0
T69	930	0	0	0
T72	0	7	0	0
T83	0	164	0	0
T84	0	44	0	0
T92	0	10	0	0

sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8038535	2202	0	0
T19	2137	4	0	0
T28	3965	0	0	0
T29	11906	0	0	0
T34	12618	52	0	0
T54	0	16	0	0
T64	1511	5	0	0
T65	2079	0	0	0
T66	1336	0	0	0
T67	7556	17	0	0
T68	1407	0	0	0
T69	930	0	0	0
T72	0	5	0	0
T83	0	146	0	0
T84	0	14	0	0
T92	0	10	0	0
T96	0	6	0	0

sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8038535	2180	0	0
T19	2137	1	0	0
T28	3965	0	0	0
T29	11906	0	0	0
T30	17265	0	0	0
T32	0	7	0	0
T34	12618	70	0	0
T36	16861	0	0	0
T46	7740	0	0	0
T54	0	23	0	0
T67	7556	29	0	0
T68	1407	0	0	0
T69	930	0	0	0
T72	0	4	0	0
T83	0	169	0	0
T84	0	26	0	0
T92	0	6	0	0
T96	0	1	0	0