Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1022393	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

243520

1

T1

2

T2

4

T3

2198

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1124487	1			T1	1		T2	1		T3	85563
values[0x0]	70380	1			T1	7		T2	15		T3	545
values[0x1]	71046	1			T1	11		T2	6		T3	602

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	697098	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

568815

1

T1

5

T2

4

T3

30106

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3365	1			T3	295		T4	27		T9	16
valid_sources[0x01]	3603	1			T3	326		T4	33		T9	20
valid_sources[0x02]	3545	1			T3	288		T4	10		T17	2
valid_sources[0x03]	3432	1			T3	308		T4	41		T9	23
valid_sources[0x04]	3480	1			T1	1		T3	342		T4	15
valid_sources[0x05]	3651	1			T3	412		T4	12		T9	26
valid_sources[0x06]	16952	1			T3	342		T4	59		T9	32
valid_sources[0x07]	3765	1			T3	363		T4	19		T9	33
valid_sources[0x08]	3356	1			T3	355		T4	10		T9	27
valid_sources[0x09]	3628	1			T3	351		T4	28		T9	29
valid_sources[0x0a]	14728	1			T3	333		T4	12		T9	33
valid_sources[0x0b]	3322	1			T3	327		T4	16		T9	24
valid_sources[0x0c]	3503	1			T3	364		T4	11		T17	7
valid_sources[0x0d]	3663	1			T3	359		T4	34		T9	25
valid_sources[0x0e]	3633	1			T3	352		T4	21		T9	24
valid_sources[0x0f]	3223	1			T3	346		T4	28		T16	3
valid_sources[0x10]	3508	1			T3	381		T4	32		T9	44
valid_sources[0x11]	3697	1			T3	349		T4	34		T9	38
valid_sources[0x12]	3418	1			T3	375		T4	31		T9	20
valid_sources[0x13]	3644	1			T3	381		T4	28		T9	31
valid_sources[0x14]	3383	1			T3	376		T4	12		T9	34
valid_sources[0x15]	3655	1			T3	342		T4	30		T9	36
valid_sources[0x16]	10120	1			T2	5		T3	312		T4	30
valid_sources[0x17]	3411	1			T3	322		T4	25		T9	38
valid_sources[0x18]	3559	1			T3	367		T4	13		T9	37
valid_sources[0x19]	3472	1			T3	364		T4	15		T9	29
valid_sources[0x1a]	3424	1			T3	315		T4	15		T9	33
valid_sources[0x1b]	3301	1			T3	324		T4	23		T9	36
valid_sources[0x1c]	3703	1			T3	374		T4	32		T9	38
valid_sources[0x1d]	3355	1			T3	334		T4	30		T9	33
valid_sources[0x1e]	3252	1			T3	332		T4	32		T9	30
valid_sources[0x1f]	3397	1			T3	337		T4	12		T9	27
valid_sources[0x20]	3647	1			T3	329		T4	46		T9	27
valid_sources[0x21]	3382	1			T3	367		T4	25		T9	31
valid_sources[0x22]	3554	1			T3	337		T4	18		T9	29
valid_sources[0x23]	3589	1			T3	337		T4	29		T9	30
valid_sources[0x24]	3775	1			T3	341		T4	23		T9	33
valid_sources[0x25]	3527	1			T3	350		T4	15		T9	29
valid_sources[0x26]	3499	1			T3	349		T4	26		T9	43
valid_sources[0x27]	4097	1			T3	362		T4	22		T9	31
valid_sources[0x28]	3407	1			T3	333		T4	30		T9	38
valid_sources[0x29]	3422	1			T3	360		T4	29		T9	28
valid_sources[0x2a]	3628	1			T3	401		T4	70		T9	31
valid_sources[0x2b]	20075	1			T3	323		T4	30		T9	23
valid_sources[0x2c]	3505	1			T3	344		T4	26		T9	35
valid_sources[0x2d]	3699	1			T3	315		T4	26		T9	40
valid_sources[0x2e]	11311	1			T3	424		T4	7		T9	29
valid_sources[0x2f]	3400	1			T3	292		T4	24		T9	28
valid_sources[0x30]	3362	1			T3	323		T4	11		T9	44
valid_sources[0x31]	3511	1			T3	346		T4	30		T9	29
valid_sources[0x32]	3486	1			T3	308		T4	30		T9	24
valid_sources[0x33]	3665	1			T3	358		T4	8		T9	30
valid_sources[0x34]	3683	1			T3	365		T4	8		T9	15
valid_sources[0x35]	3522	1			T3	353		T4	21		T9	33
valid_sources[0x36]	3495	1			T1	3		T3	329		T4	20
valid_sources[0x37]	3591	1			T3	360		T4	12		T9	25
valid_sources[0x38]	3632	1			T3	435		T4	27		T9	23
valid_sources[0x39]	3405	1			T3	264		T4	8		T16	1
valid_sources[0x3a]	3537	1			T3	346		T4	15		T9	30
valid_sources[0x3b]	5386	1			T3	353		T4	41		T9	18
valid_sources[0x3c]	3451	1			T3	325		T4	17		T16	1
valid_sources[0x3d]	3413	1			T3	330		T4	37		T9	19
valid_sources[0x3e]	3429	1			T3	344		T4	16		T9	29
valid_sources[0x3f]	3218	1			T3	320		T4	11		T9	26
valid_sources[0x40]	3944	1			T3	317		T4	30		T9	23
valid_sources[0x41]	3478	1			T3	342		T4	19		T9	23
valid_sources[0x42]	3445	1			T3	406		T4	5		T9	48
valid_sources[0x43]	3492	1			T2	1		T3	351		T4	27
valid_sources[0x44]	3621	1			T3	292		T4	18		T9	23
valid_sources[0x45]	3474	1			T3	328		T4	13		T9	27
valid_sources[0x46]	3623	1			T3	316		T4	19		T9	23
valid_sources[0x47]	3586	1			T3	330		T4	26		T9	29
valid_sources[0x48]	11429	1			T3	329		T4	31		T9	29
valid_sources[0x49]	3389	1			T3	343		T4	17		T16	2
valid_sources[0x4a]	3407	1			T3	334		T4	40		T9	32
valid_sources[0x4b]	3539	1			T3	348		T4	45		T9	34
valid_sources[0x4c]	3483	1			T3	377		T4	34		T9	30
valid_sources[0x4d]	3390	1			T3	324		T4	37		T16	2
valid_sources[0x4e]	12054	1			T3	329		T4	12		T9	20
valid_sources[0x4f]	3488	1			T3	325		T4	28		T9	30
valid_sources[0x50]	3569	1			T3	295		T4	25		T9	33
valid_sources[0x51]	7368	1			T3	303		T4	15		T9	37
valid_sources[0x52]	3333	1			T3	357		T4	18		T9	41
valid_sources[0x53]	3644	1			T3	344		T4	29		T9	25
valid_sources[0x54]	3625	1			T3	390		T4	13		T9	29
valid_sources[0x55]	3671	1			T3	360		T4	44		T9	30
valid_sources[0x56]	3475	1			T3	324		T4	15		T9	33
valid_sources[0x57]	11003	1			T3	387		T4	29		T9	28
valid_sources[0x58]	3427	1			T3	329		T4	14		T9	17
valid_sources[0x59]	16973	1			T3	357		T4	9		T16	1
valid_sources[0x5a]	3358	1			T3	305		T4	23		T9	27
valid_sources[0x5b]	3407	1			T3	335		T4	29		T9	43
valid_sources[0x5c]	3553	1			T3	357		T4	15		T9	39
valid_sources[0x5d]	3206	1			T3	290		T4	8		T9	21
valid_sources[0x5e]	3390	1			T3	343		T4	9		T9	32
valid_sources[0x5f]	3566	1			T3	356		T4	37		T9	35
valid_sources[0x60]	5598	1			T3	294		T4	30		T9	23
valid_sources[0x61]	3464	1			T1	2		T3	274		T4	35
valid_sources[0x62]	3780	1			T3	366		T4	19		T9	25
valid_sources[0x63]	3332	1			T3	322		T4	11		T9	31
valid_sources[0x64]	3368	1			T3	307		T4	15		T9	30
valid_sources[0x65]	3530	1			T3	368		T4	17		T9	16
valid_sources[0x66]	3457	1			T3	341		T4	19		T9	42
valid_sources[0x67]	3360	1			T3	350		T4	9		T9	30
valid_sources[0x68]	3535	1			T3	359		T4	25		T9	20
valid_sources[0x69]	3445	1			T3	320		T4	22		T9	37
valid_sources[0x6a]	4004	1			T3	315		T4	10		T16	1
valid_sources[0x6b]	3344	1			T3	362		T4	13		T9	27
valid_sources[0x6c]	6134	1			T3	379		T4	14		T9	26
valid_sources[0x6d]	3691	1			T3	369		T4	39		T9	28
valid_sources[0x6e]	3859	1			T3	352		T4	6		T9	28
valid_sources[0x6f]	3368	1			T3	302		T4	29		T9	25
valid_sources[0x70]	3499	1			T3	375		T4	17		T9	38
valid_sources[0x71]	3597	1			T3	329		T4	22		T9	28
valid_sources[0x72]	3422	1			T3	365		T4	15		T9	30
valid_sources[0x73]	3569	1			T3	292		T4	36		T9	30
valid_sources[0x74]	4882	1			T3	342		T4	25		T9	33
valid_sources[0x75]	3498	1			T3	351		T4	9		T16	1
valid_sources[0x76]	45878	1			T2	1		T3	333		T4	11
valid_sources[0x77]	3844	1			T3	387		T4	17		T9	26
valid_sources[0x78]	3817	1			T3	372		T4	12		T9	19
valid_sources[0x79]	3694	1			T2	1		T3	333		T4	28
valid_sources[0x7a]	3940	1			T3	368		T4	20		T9	30
valid_sources[0x7b]	3665	1			T2	1		T3	330		T4	25
valid_sources[0x7c]	3516	1			T3	317		T4	18		T9	22
valid_sources[0x7d]	6719	1			T3	331		T4	33		T5	3086
valid_sources[0x7e]	3471	1			T3	353		T4	24		T9	21
valid_sources[0x7f]	3522	1			T3	320		T4	12		T9	26
valid_sources[0x80]	23984	1			T3	394		T4	38		T16	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

135011

1

T3

1416

T4

1662

T17

1

values[0x0]

all_enables

biggest_size

57980

1

T1

2

T2

3

T3

422

values[0x1]

all_enables

biggest_size

50529

1

T2

1

T3

360

T4

389