Unified Coverage Report :: Module :: keymgr_cfg_en

Module : keymgr_cfg_en

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.31	89.47	73.68			77.78

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_common_0.1/rtl/keymgr_cfg_en.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sw_binding_regwen	67.84	78.95	57.89			66.67
tb.dut.u_slot_policy_regwen	67.84	78.95	57.89			66.67
tb.dut.u_max_key_ver_regwen	67.84	78.95	57.89			66.67
tb.dut.u_cfgen	79.82	89.47	72.22			77.78

---

Module Instance : tb.dut.u_sw_binding_regwen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
67.84	78.95	57.89			66.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
67.84	78.95	57.89			66.67

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.39	100.00	80.22	53.88		97.83	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_slot_policy_regwen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
67.84	78.95	57.89			66.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
67.84	78.95	57.89			66.67

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.39	100.00	80.22	53.88		97.83	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_max_key_ver_regwen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
67.84	78.95	57.89			66.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
67.84	78.95	57.89			66.67

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.39	100.00	80.22	53.88		97.83	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_cfgen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.82	89.47	72.22			77.78

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.82	89.47	72.22			77.78

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.39	100.00	80.22	53.88		97.83	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : keymgr_cfg_en

	Line No.	Total	Covered	Percent
TOTAL		19	17	89.47
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	31	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	37	1	1	100.00
CONT_ASSIGN	38	1	1	100.00
ALWAYS	41	6	5	83.33
ALWAYS	52	8	7	87.50

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_common_0.1/rtl/keymgr_cfg_en.sv' or '../src/lowrisc_ip_keymgr_common_0.1/rtl/keymgr_cfg_en.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
30	1	1
31	1	1
32	1	1
37	1	1
38	1	1
41	1	1
42	1	1
43	1	1
44	0	1
45	1	1
46	1	1
			MISSING_ELSE
52	1	1
53	1	1
54	1	1
55	0	1
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE

---

Cond Coverage for Module : keymgr_cfg_en

	Total	Covered	Percent
Conditions	19	14	73.68
Logical	19	14	73.68
Non-Logical	0	0
Event	0	0

 LINE       30
 EXPRESSION (init_q && clr_i)
             ---1--    --2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       31
 EXPRESSION (init_q && set_i)
             ---1--    --2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       32
 EXPRESSION (init_q && ((!en_i)))
             ---1--    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       38
 EXPRESSION (((~out_clr)) & out_q & en_i)
             ------1-----   --2--   --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T5
1	0	1	Not Covered
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (init_q && ((!en_i)))
             ---1--    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       45
 EXPRESSION (init_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : keymgr_cfg_en

	Line No.	Total	Covered	Percent
Branches		9	7	77.78
IF	41	4	3	75.00
IF	52	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_common_0.1/rtl/keymgr_cfg_en.sv' or '../src/lowrisc_ip_keymgr_common_0.1/rtl/keymgr_cfg_en.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	41	if ((!rst_ni))
-2-:	43	if ((init_q && (!en_i)))
-3-:	45	if ((init_i && en_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	52	if ((!rst_ni))
-2-:	54	if (vld_dis)
-3-:	56	if (vld_set)
-4-:	58	if (out_clr)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	-	Covered	T3,T4,T5
0	0	0	1	Covered	T3,T4,T5
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sw_binding_regwen

	Line No.	Total	Covered	Percent
TOTAL		19	15	78.95
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	31	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	37	1	0	0.00
CONT_ASSIGN	38	1	1	100.00
ALWAYS	41	6	5	83.33
ALWAYS	52	8	6	75.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_common_0.1/rtl/keymgr_cfg_en.sv' or '../src/lowrisc_ip_keymgr_common_0.1/rtl/keymgr_cfg_en.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
30	1	1
31	1	1
32	1	1
37	0	1
38	1	1
41	1	1
42	1	1
43	1	1
44	0	1
45	1	1
46	1	1
			MISSING_ELSE
52	1	1
53	1	1
54	1	1
55	0	1
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sw_binding_regwen

	Total	Covered	Percent
Conditions	19	11	57.89
Logical	19	11	57.89
Non-Logical	0	0
Event	0	0

 LINE       30
 EXPRESSION (init_q && clr_i)
             ---1--    --2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T4,T5
1	1	Not Covered

 LINE       31
 EXPRESSION (init_q && set_i)
             ---1--    --2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       32
 EXPRESSION (init_q && ((!en_i)))
             ---1--    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Not Covered

 LINE       38
 EXPRESSION (((~out_clr)) & out_q & en_i)
             ------1-----   --2--   --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (init_q && ((!en_i)))
             ---1--    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Not Covered

 LINE       45
 EXPRESSION (init_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T5

---

Branch Coverage for Instance : tb.dut.u_sw_binding_regwen

	Line No.	Total	Covered	Percent
Branches		9	6	66.67
IF	41	4	3	75.00
IF	52	5	3	60.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_common_0.1/rtl/keymgr_cfg_en.sv' or '../src/lowrisc_ip_keymgr_common_0.1/rtl/keymgr_cfg_en.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	41	if ((!rst_ni))
-2-:	43	if ((init_q && (!en_i)))
-3-:	45	if ((init_i && en_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Covered	T3,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	52	if ((!rst_ni))
-2-:	54	if (vld_dis)
-3-:	56	if (vld_set)
-4-:	58	if (out_clr)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	-	Covered	T3,T4,T5
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_slot_policy_regwen

	Line No.	Total	Covered	Percent
TOTAL		19	15	78.95
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	31	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	37	1	0	0.00
CONT_ASSIGN	38	1	1	100.00
ALWAYS	41	6	5	83.33
ALWAYS	52	8	6	75.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_common_0.1/rtl/keymgr_cfg_en.sv' or '../src/lowrisc_ip_keymgr_common_0.1/rtl/keymgr_cfg_en.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
30	1	1
31	1	1
32	1	1
37	0	1
38	1	1
41	1	1
42	1	1
43	1	1
44	0	1
45	1	1
46	1	1
			MISSING_ELSE
52	1	1
53	1	1
54	1	1
55	0	1
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_slot_policy_regwen

	Total	Covered	Percent
Conditions	19	11	57.89
Logical	19	11	57.89
Non-Logical	0	0
Event	0	0

 LINE       30
 EXPRESSION (init_q && clr_i)
             ---1--    --2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T4,T5
1	1	Not Covered

 LINE       31
 EXPRESSION (init_q && set_i)
             ---1--    --2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       32
 EXPRESSION (init_q && ((!en_i)))
             ---1--    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Not Covered

 LINE       38
 EXPRESSION (((~out_clr)) & out_q & en_i)
             ------1-----   --2--   --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (init_q && ((!en_i)))
             ---1--    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Not Covered

 LINE       45
 EXPRESSION (init_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T5

---

Branch Coverage for Instance : tb.dut.u_slot_policy_regwen

	Line No.	Total	Covered	Percent
Branches		9	6	66.67
IF	41	4	3	75.00
IF	52	5	3	60.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_common_0.1/rtl/keymgr_cfg_en.sv' or '../src/lowrisc_ip_keymgr_common_0.1/rtl/keymgr_cfg_en.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	41	if ((!rst_ni))
-2-:	43	if ((init_q && (!en_i)))
-3-:	45	if ((init_i && en_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Covered	T3,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	52	if ((!rst_ni))
-2-:	54	if (vld_dis)
-3-:	56	if (vld_set)
-4-:	58	if (out_clr)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	-	Covered	T3,T4,T5
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_max_key_ver_regwen

	Line No.	Total	Covered	Percent
TOTAL		19	15	78.95
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	31	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	37	1	0	0.00
CONT_ASSIGN	38	1	1	100.00
ALWAYS	41	6	5	83.33
ALWAYS	52	8	6	75.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_common_0.1/rtl/keymgr_cfg_en.sv' or '../src/lowrisc_ip_keymgr_common_0.1/rtl/keymgr_cfg_en.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
30	1	1
31	1	1
32	1	1
37	0	1
38	1	1
41	1	1
42	1	1
43	1	1
44	0	1
45	1	1
46	1	1
			MISSING_ELSE
52	1	1
53	1	1
54	1	1
55	0	1
56	1	1
57	1	1
58	1	1
59	0	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_max_key_ver_regwen

	Total	Covered	Percent
Conditions	19	11	57.89
Logical	19	11	57.89
Non-Logical	0	0
Event	0	0

 LINE       30
 EXPRESSION (init_q && clr_i)
             ---1--    --2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T4,T5
1	1	Not Covered

 LINE       31
 EXPRESSION (init_q && set_i)
             ---1--    --2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       32
 EXPRESSION (init_q && ((!en_i)))
             ---1--    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Not Covered

 LINE       38
 EXPRESSION (((~out_clr)) & out_q & en_i)
             ------1-----   --2--   --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (init_q && ((!en_i)))
             ---1--    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Not Covered

 LINE       45
 EXPRESSION (init_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T5

---

Branch Coverage for Instance : tb.dut.u_max_key_ver_regwen

	Line No.	Total	Covered	Percent
Branches		9	6	66.67
IF	41	4	3	75.00
IF	52	5	3	60.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_common_0.1/rtl/keymgr_cfg_en.sv' or '../src/lowrisc_ip_keymgr_common_0.1/rtl/keymgr_cfg_en.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	41	if ((!rst_ni))
-2-:	43	if ((init_q && (!en_i)))
-3-:	45	if ((init_i && en_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Covered	T3,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	52	if ((!rst_ni))
-2-:	54	if (vld_dis)
-3-:	56	if (vld_set)
-4-:	58	if (out_clr)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	-	Covered	T3,T4,T5
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cfgen

	Line No.	Total	Covered	Percent
TOTAL		19	17	89.47
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	31	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	37	1	1	100.00
CONT_ASSIGN	38	1	1	100.00
ALWAYS	41	6	5	83.33
ALWAYS	52	8	7	87.50

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_common_0.1/rtl/keymgr_cfg_en.sv' or '../src/lowrisc_ip_keymgr_common_0.1/rtl/keymgr_cfg_en.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
30	1	1
31	1	1
32	1	1
37	1	1
38	1	1
41	1	1
42	1	1
43	1	1
44	0	1
45	1	1
46	1	1
			MISSING_ELSE
52	1	1
53	1	1
54	1	1
55	0	1
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_cfgen

	Total	Covered	Percent
Conditions	18	13	72.22
Logical	18	13	72.22
Non-Logical	0	0
Event	0	0

 LINE       30
 EXPRESSION (init_q && clr_i)
             ---1--    --2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       31
 EXPRESSION (init_q && set_i)
             ---1--    --2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       32
 EXPRESSION (init_q && ((!en_i)))
             ---1--    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       38
 EXPRESSION (((~out_clr)) & out_q & en_i)
             ------1-----   --2--   --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T5
1	0	1	Not Covered
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (init_q && ((!en_i)))
             ---1--    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       45
 EXPRESSION (init_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_cfgen

	Line No.	Total	Covered	Percent
Branches		9	7	77.78
IF	41	4	3	75.00
IF	52	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_common_0.1/rtl/keymgr_cfg_en.sv' or '../src/lowrisc_ip_keymgr_common_0.1/rtl/keymgr_cfg_en.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	41	if ((!rst_ni))
-2-:	43	if ((init_q && (!en_i)))
-3-:	45	if ((init_i && en_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	52	if ((!rst_ni))
-2-:	54	if (vld_dis)
-3-:	56	if (vld_set)
-4-:	58	if (out_clr)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	-	Covered	T3,T4,T5
0	0	0	1	Covered	T3,T4,T5
0	0	0	0	Covered	T1,T2,T3