Unified Coverage Report :: Module :: keymgr_dpe_csr_assert_fpv

Module : keymgr_dpe_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_dpe_csr_assert_0/keymgr_dpe_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_dpe_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_dpe_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.39	100.00	80.22	53.88		97.83	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_dpe_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	22	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	22	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	8600657	8323	0	0
intr_enable_rd_A	8600657	1611	0	0
key_version_rd_A	8600657	1515	0	0
reseed_interval_regwen_rd_A	8600657	625	0	0
salt_0_rd_A	8600657	1404	0	0
salt_1_rd_A	8600657	1412	0	0
salt_2_rd_A	8600657	1430	0	0
salt_3_rd_A	8600657	1448	0	0
salt_4_rd_A	8600657	1429	0	0
salt_5_rd_A	8600657	1329	0	0
salt_6_rd_A	8600657	1465	0	0
salt_7_rd_A	8600657	1359	0	0
sideload_clear_rd_A	8600657	1371	0	0
slot_policy_rd_A	8600657	2025	0	0
sw_binding_0_rd_A	8600657	1462	0	0
sw_binding_1_rd_A	8600657	1451	0	0
sw_binding_2_rd_A	8600657	1481	0	0
sw_binding_3_rd_A	8600657	1396	0	0
sw_binding_4_rd_A	8600657	1358	0	0
sw_binding_5_rd_A	8600657	1413	0	0
sw_binding_6_rd_A	8600657	1385	0	0
sw_binding_7_rd_A	8600657	1435	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8600657	8323	0	0
T22	2769	318	0	0
T23	14201	451	0	0
T24	14657	1	0	0
T36	7574	448	0	0
T41	2004	120	0	0
T42	10224	396	0	0
T54	0	472	0	0
T55	0	94	0	0
T68	20298	0	0	0
T73	857	0	0	0
T74	1830	0	0	0
T75	5282	0	0	0
T91	0	12	0	0
T92	0	10	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8600657	1611	0	0
T23	14201	7	0	0
T24	14657	40	0	0
T42	10224	0	0	0
T50	4784	13	0	0
T54	3480	0	0	0
T55	1701	0	0	0
T67	26734	109	0	0
T69	0	42	0	0
T75	5282	35	0	0
T76	4088	0	0	0
T92	0	7	0	0
T93	0	15	0	0
T94	0	10	0	0
T95	0	8	0	0
T96	729	0	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8600657	1515	0	0
T23	14201	14	0	0
T24	14657	39	0	0
T42	10224	0	0	0
T46	0	2	0	0
T50	4784	40	0	0
T54	3480	0	0	0
T55	1701	0	0	0
T67	26734	74	0	0
T69	0	40	0	0
T75	5282	33	0	0
T76	4088	0	0	0
T92	0	4	0	0
T94	0	4	0	0
T96	729	0	0	0
T97	0	2	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8600657	625	0	0
T23	14201	21	0	0
T42	10224	0	0	0
T50	4784	17	0	0
T54	3480	0	0	0
T55	1701	0	0	0
T67	26734	16	0	0
T69	0	3	0	0
T75	5282	1	0	0
T76	4088	0	0	0
T86	1327	0	0	0
T92	0	1	0	0
T94	0	9	0	0
T95	0	6	0	0
T96	729	0	0	0
T97	0	1	0	0
T98	0	12	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8600657	1404	0	0
T24	14657	22	0	0
T42	10224	0	0	0
T50	4784	6	0	0
T54	3480	0	0	0
T55	1701	0	0	0
T67	26734	77	0	0
T69	0	56	0	0
T75	5282	72	0	0
T76	4088	0	0	0
T86	1327	0	0	0
T94	0	7	0	0
T96	729	0	0	0
T97	0	9	0	0
T98	0	7	0	0
T99	0	54	0	0
T100	0	26	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8600657	1412	0	0
T24	14657	43	0	0
T46	6856	8	0	0
T50	4784	38	0	0
T67	26734	85	0	0
T69	14445	42	0	0
T85	1463	6	0	0
T91	2492	0	0	0
T92	1988	3	0	0
T94	1817	15	0	0
T95	0	10	0	0
T97	1525	5	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8600657	1430	0	0
T23	14201	4	0	0
T24	14657	50	0	0
T42	10224	0	0	0
T54	3480	0	0	0
T55	1701	0	0	0
T67	26734	106	0	0
T69	0	48	0	0
T75	5282	27	0	0
T76	4088	0	0	0
T86	1327	0	0	0
T92	0	4	0	0
T94	0	9	0	0
T95	0	6	0	0
T96	729	0	0	0
T98	0	7	0	0
T99	0	42	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8600657	1448	0	0
T23	14201	3	0	0
T24	14657	46	0	0
T42	10224	0	0	0
T50	4784	28	0	0
T54	3480	0	0	0
T55	1701	0	0	0
T67	26734	88	0	0
T69	0	51	0	0
T75	5282	37	0	0
T76	4088	0	0	0
T85	1463	3	0	0
T92	0	2	0	0
T94	0	1	0	0
T97	0	3	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8600657	1429	0	0
T23	14201	13	0	0
T24	14657	34	0	0
T42	10224	0	0	0
T46	0	7	0	0
T50	4784	24	0	0
T54	3480	0	0	0
T55	1701	0	0	0
T67	26734	79	0	0
T69	0	31	0	0
T75	5282	25	0	0
T76	4088	0	0	0
T92	0	2	0	0
T94	0	10	0	0
T96	729	0	0	0
T97	0	3	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8600657	1329	0	0
T23	14201	9	0	0
T24	14657	41	0	0
T42	10224	0	0	0
T50	4784	8	0	0
T54	3480	0	0	0
T55	1701	0	0	0
T67	26734	63	0	0
T69	0	65	0	0
T75	5282	4	0	0
T76	4088	0	0	0
T92	0	6	0	0
T94	0	8	0	0
T95	0	8	0	0
T96	729	0	0	0
T97	0	4	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8600657	1465	0	0
T23	14201	16	0	0
T24	14657	46	0	0
T46	6856	5	0	0
T50	4784	54	0	0
T67	26734	66	0	0
T69	14445	62	0	0
T85	1463	3	0	0
T91	2492	0	0	0
T92	1988	2	0	0
T94	0	6	0	0
T97	1525	3	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8600657	1359	0	0
T23	14201	9	0	0
T24	14657	42	0	0
T42	10224	0	0	0
T46	0	10	0	0
T50	4784	54	0	0
T54	3480	0	0	0
T55	1701	0	0	0
T67	26734	71	0	0
T69	0	38	0	0
T75	5282	28	0	0
T76	4088	0	0	0
T92	0	2	0	0
T94	0	9	0	0
T96	729	0	0	0
T97	0	3	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8600657	1371	0	0
T23	14201	4	0	0
T24	14657	43	0	0
T42	10224	0	0	0
T46	0	8	0	0
T50	4784	50	0	0
T54	3480	0	0	0
T55	1701	0	0	0
T67	26734	92	0	0
T69	0	54	0	0
T75	5282	18	0	0
T76	4088	0	0	0
T92	0	8	0	0
T94	0	5	0	0
T96	729	0	0	0
T97	0	4	0	0

slot_policy_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8600657	2025	0	0
T24	14657	90	0	0
T42	10224	0	0	0
T46	0	6	0	0
T50	4784	4	0	0
T54	3480	0	0	0
T55	1701	0	0	0
T67	26734	136	0	0
T69	0	70	0	0
T75	5282	34	0	0
T76	4088	0	0	0
T85	1463	2	0	0
T94	0	11	0	0
T95	0	8	0	0
T96	729	0	0	0
T97	0	2	0	0

sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8600657	1462	0	0
T23	14201	12	0	0
T24	14657	29	0	0
T42	10224	0	0	0
T46	0	7	0	0
T50	4784	21	0	0
T54	3480	0	0	0
T55	1701	0	0	0
T67	26734	114	0	0
T69	0	42	0	0
T75	5282	35	0	0
T76	4088	0	0	0
T92	0	13	0	0
T94	0	9	0	0
T96	729	0	0	0
T97	0	4	0	0

sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8600657	1451	0	0
T23	14201	9	0	0
T24	14657	24	0	0
T42	10224	0	0	0
T46	0	7	0	0
T50	4784	52	0	0
T54	3480	0	0	0
T55	1701	0	0	0
T67	26734	78	0	0
T69	0	62	0	0
T75	5282	16	0	0
T76	4088	0	0	0
T92	0	1	0	0
T94	0	7	0	0
T96	729	0	0	0
T97	0	8	0	0

sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8600657	1481	0	0
T23	14201	4	0	0
T24	14657	29	0	0
T42	10224	0	0	0
T46	0	2	0	0
T50	4784	37	0	0
T54	3480	0	0	0
T55	1701	0	0	0
T67	26734	74	0	0
T69	0	36	0	0
T75	5282	52	0	0
T76	4088	0	0	0
T85	1463	6	0	0
T92	0	2	0	0
T97	0	2	0	0

sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8600657	1396	0	0
T23	14201	6	0	0
T24	14657	40	0	0
T42	10224	0	0	0
T46	0	12	0	0
T50	4784	16	0	0
T54	3480	0	0	0
T55	1701	0	0	0
T67	26734	65	0	0
T69	0	33	0	0
T75	5282	8	0	0
T76	4088	0	0	0
T92	0	8	0	0
T94	0	10	0	0
T96	729	0	0	0
T97	0	4	0	0

sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8600657	1358	0	0
T23	14201	13	0	0
T24	14657	32	0	0
T42	10224	0	0	0
T50	4784	4	0	0
T54	3480	0	0	0
T55	1701	0	0	0
T67	26734	64	0	0
T69	0	45	0	0
T75	5282	25	0	0
T76	4088	0	0	0
T92	0	4	0	0
T94	0	12	0	0
T95	0	1	0	0
T96	729	0	0	0
T97	0	3	0	0

sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8600657	1413	0	0
T23	14201	7	0	0
T24	14657	44	0	0
T42	10224	0	0	0
T46	0	5	0	0
T50	4784	27	0	0
T54	3480	0	0	0
T55	1701	0	0	0
T67	26734	103	0	0
T69	0	46	0	0
T75	5282	15	0	0
T76	4088	0	0	0
T85	1463	7	0	0
T94	0	2	0	0
T97	0	8	0	0

sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8600657	1385	0	0
T23	14201	2	0	0
T24	14657	37	0	0
T42	10224	0	0	0
T46	0	6	0	0
T50	4784	21	0	0
T54	3480	0	0	0
T55	1701	0	0	0
T67	26734	78	0	0
T69	0	51	0	0
T75	5282	28	0	0
T76	4088	0	0	0
T94	0	11	0	0
T95	0	6	0	0
T96	729	0	0	0
T97	0	2	0	0

sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8600657	1435	0	0
T24	14657	43	0	0
T42	10224	0	0	0
T46	0	13	0	0
T50	4784	20	0	0
T54	3480	0	0	0
T55	1701	0	0	0
T67	26734	63	0	0
T69	0	53	0	0
T75	5282	21	0	0
T76	4088	0	0	0
T86	1327	0	0	0
T94	0	19	0	0
T95	0	10	0	0
T96	729	0	0	0
T97	0	8	0	0
T98	0	7	0	0