Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	572268	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

247294

1

T1

4

T2

4

T3

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	675718	1			T1	1		T2	1		T3	1
values[0x0]	71408	1			T1	8		T2	6		T3	15
values[0x1]	72436	1			T1	12		T2	7		T3	18

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	396553	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

423009

1

T1

5

T2

5

T3

10

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2788	1			T5	86		T6	122		T10	90
valid_sources[0x01]	2845	1			T5	72		T6	142		T10	45
valid_sources[0x02]	2716	1			T5	68		T6	151		T10	69
valid_sources[0x03]	2816	1			T5	65		T6	115		T10	54
valid_sources[0x04]	2873	1			T5	71		T6	156		T10	61
valid_sources[0x05]	2733	1			T5	60		T6	155		T10	89
valid_sources[0x06]	2485	1			T5	65		T6	142		T10	57
valid_sources[0x07]	3135	1			T5	61		T6	162		T10	52
valid_sources[0x08]	2827	1			T5	95		T6	141		T10	53
valid_sources[0x09]	2701	1			T5	60		T6	142		T10	72
valid_sources[0x0a]	2971	1			T5	75		T6	143		T10	52
valid_sources[0x0b]	2605	1			T5	69		T6	151		T10	47
valid_sources[0x0c]	2441	1			T5	48		T6	164		T10	49
valid_sources[0x0d]	2828	1			T5	66		T6	162		T10	57
valid_sources[0x0e]	2809	1			T5	69		T6	145		T10	55
valid_sources[0x0f]	2844	1			T5	59		T6	133		T10	43
valid_sources[0x10]	2709	1			T5	69		T6	141		T10	72
valid_sources[0x11]	2644	1			T5	84		T6	133		T10	52
valid_sources[0x12]	2991	1			T5	60		T6	131		T10	56
valid_sources[0x13]	2814	1			T5	70		T6	187		T10	65
valid_sources[0x14]	2844	1			T5	60		T6	146		T10	67
valid_sources[0x15]	3306	1			T5	79		T6	146		T10	67
valid_sources[0x16]	2748	1			T20	18		T5	75		T6	142
valid_sources[0x17]	2782	1			T5	76		T6	128		T10	54
valid_sources[0x18]	2641	1			T5	62		T6	139		T10	47
valid_sources[0x19]	2725	1			T5	70		T6	145		T10	51
valid_sources[0x1a]	2685	1			T5	61		T6	158		T10	67
valid_sources[0x1b]	2573	1			T5	69		T6	122		T10	52
valid_sources[0x1c]	2746	1			T5	57		T6	155		T10	73
valid_sources[0x1d]	2868	1			T5	71		T6	150		T10	50
valid_sources[0x1e]	2782	1			T5	79		T6	143		T10	55
valid_sources[0x1f]	2945	1			T5	67		T6	132		T10	51
valid_sources[0x20]	2932	1			T5	71		T6	140		T10	54
valid_sources[0x21]	2805	1			T5	59		T6	111		T10	83
valid_sources[0x22]	3030	1			T5	55		T6	137		T10	89
valid_sources[0x23]	2976	1			T5	89		T6	142		T10	59
valid_sources[0x24]	3014	1			T5	59		T6	144		T10	64
valid_sources[0x25]	2827	1			T5	72		T6	154		T10	73
valid_sources[0x26]	2956	1			T5	70		T6	146		T10	74
valid_sources[0x27]	2813	1			T5	53		T6	117		T10	50
valid_sources[0x28]	2678	1			T5	69		T6	126		T10	62
valid_sources[0x29]	9081	1			T5	64		T6	111		T10	43
valid_sources[0x2a]	2773	1			T5	40		T6	146		T10	61
valid_sources[0x2b]	2940	1			T5	67		T6	151		T10	65
valid_sources[0x2c]	2770	1			T5	70		T6	130		T10	69
valid_sources[0x2d]	2616	1			T5	74		T6	168		T10	42
valid_sources[0x2e]	2849	1			T5	84		T6	106		T10	40
valid_sources[0x2f]	2727	1			T5	69		T6	147		T10	99
valid_sources[0x30]	2640	1			T5	59		T6	130		T10	38
valid_sources[0x31]	3051	1			T5	54		T6	152		T10	62
valid_sources[0x32]	2811	1			T5	91		T6	115		T10	87
valid_sources[0x33]	2761	1			T5	68		T6	149		T10	63
valid_sources[0x34]	2754	1			T5	70		T6	137		T10	51
valid_sources[0x35]	2683	1			T5	72		T6	163		T10	55
valid_sources[0x36]	2660	1			T5	62		T6	106		T10	91
valid_sources[0x37]	4800	1			T5	75		T6	141		T10	65
valid_sources[0x38]	2801	1			T1	2		T5	68		T6	123
valid_sources[0x39]	2730	1			T5	50		T6	174		T10	37
valid_sources[0x3a]	3003	1			T5	74		T6	145		T10	77
valid_sources[0x3b]	2853	1			T5	62		T6	119		T10	45
valid_sources[0x3c]	2695	1			T5	65		T6	153		T10	70
valid_sources[0x3d]	6526	1			T5	63		T6	161		T10	82
valid_sources[0x3e]	2871	1			T5	76		T6	127		T10	68
valid_sources[0x3f]	2611	1			T5	44		T6	179		T10	60
valid_sources[0x40]	2943	1			T5	64		T6	148		T10	54
valid_sources[0x41]	2780	1			T5	50		T6	162		T10	73
valid_sources[0x42]	2712	1			T5	69		T6	163		T10	70
valid_sources[0x43]	2778	1			T5	70		T6	164		T10	68
valid_sources[0x44]	2895	1			T5	65		T6	149		T10	77
valid_sources[0x45]	8317	1			T5	46		T6	128		T10	48
valid_sources[0x46]	2777	1			T5	80		T6	150		T10	51
valid_sources[0x47]	3088	1			T5	72		T6	145		T10	46
valid_sources[0x48]	3008	1			T5	89		T6	116		T10	88
valid_sources[0x49]	2849	1			T5	55		T6	118		T10	51
valid_sources[0x4a]	2781	1			T5	64		T6	110		T10	45
valid_sources[0x4b]	2638	1			T5	71		T6	124		T10	61
valid_sources[0x4c]	2586	1			T5	54		T6	140		T10	49
valid_sources[0x4d]	3113	1			T5	87		T6	186		T10	59
valid_sources[0x4e]	2732	1			T5	67		T6	133		T10	52
valid_sources[0x4f]	2671	1			T5	76		T6	137		T10	82
valid_sources[0x50]	3223	1			T5	76		T6	145		T10	49
valid_sources[0x51]	2720	1			T5	68		T6	143		T10	51
valid_sources[0x52]	2798	1			T5	55		T6	148		T10	70
valid_sources[0x53]	2766	1			T5	68		T6	123		T10	61
valid_sources[0x54]	2710	1			T5	65		T6	172		T10	53
valid_sources[0x55]	45816	1			T4	42799		T5	65		T6	151
valid_sources[0x56]	2911	1			T5	77		T6	169		T10	66
valid_sources[0x57]	2737	1			T5	56		T6	138		T10	45
valid_sources[0x58]	2951	1			T5	65		T6	142		T10	82
valid_sources[0x59]	2829	1			T5	77		T6	110		T10	42
valid_sources[0x5a]	2681	1			T5	74		T6	126		T10	57
valid_sources[0x5b]	2799	1			T5	68		T6	122		T10	49
valid_sources[0x5c]	4536	1			T5	76		T6	129		T10	63
valid_sources[0x5d]	2986	1			T5	66		T6	132		T10	71
valid_sources[0x5e]	2673	1			T5	62		T6	124		T10	70
valid_sources[0x5f]	2947	1			T1	1		T5	49		T6	149
valid_sources[0x60]	2898	1			T5	65		T6	164		T10	72
valid_sources[0x61]	2789	1			T19	4		T5	74		T6	137
valid_sources[0x62]	2899	1			T5	68		T6	103		T10	77
valid_sources[0x63]	2599	1			T5	68		T6	116		T10	61
valid_sources[0x64]	2709	1			T5	64		T6	128		T10	47
valid_sources[0x65]	2753	1			T5	71		T6	141		T10	54
valid_sources[0x66]	2722	1			T5	81		T6	173		T10	53
valid_sources[0x67]	2597	1			T5	87		T6	134		T10	72
valid_sources[0x68]	2779	1			T5	73		T6	128		T10	55
valid_sources[0x69]	3344	1			T5	81		T6	146		T10	66
valid_sources[0x6a]	2611	1			T5	82		T6	174		T10	63
valid_sources[0x6b]	2717	1			T5	47		T6	161		T10	84
valid_sources[0x6c]	2703	1			T5	65		T6	139		T10	69
valid_sources[0x6d]	2969	1			T5	45		T6	128		T10	50
valid_sources[0x6e]	2957	1			T5	60		T6	193		T10	82
valid_sources[0x6f]	2573	1			T5	72		T6	139		T10	91
valid_sources[0x70]	2794	1			T5	72		T6	150		T10	56
valid_sources[0x71]	2817	1			T5	66		T6	147		T10	54
valid_sources[0x72]	2765	1			T1	10		T5	49		T6	160
valid_sources[0x73]	2638	1			T5	70		T6	164		T10	46
valid_sources[0x74]	6399	1			T5	69		T6	132		T10	44
valid_sources[0x75]	2593	1			T5	70		T6	141		T10	58
valid_sources[0x76]	2738	1			T5	70		T6	134		T10	81
valid_sources[0x77]	2626	1			T5	83		T6	138		T10	59
valid_sources[0x78]	2658	1			T5	75		T6	122		T10	69
valid_sources[0x79]	2740	1			T5	67		T6	134		T10	60
valid_sources[0x7a]	2706	1			T5	57		T6	134		T10	54
valid_sources[0x7b]	2962	1			T5	74		T6	151		T10	91
valid_sources[0x7c]	3055	1			T5	67		T6	149		T10	69
valid_sources[0x7d]	7221	1			T5	77		T6	161		T10	81
valid_sources[0x7e]	2752	1			T5	81		T6	156		T10	51
valid_sources[0x7f]	2683	1			T5	68		T6	127		T10	46
valid_sources[0x80]	2754	1			T5	58		T6	155		T10	45

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

137049

1

T3

1

T20

1

T4

1866

values[0x0]

all_enables

biggest_size

58693

1

T1

2

T2

2

T3

3

values[0x1]

all_enables

biggest_size

51552

1

T1

2

T2

2

T3

3