Unified Coverage Report :: Module :: keymgr_dpe_csr_assert_fpv

Module : keymgr_dpe_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_dpe_csr_assert_0/keymgr_dpe_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_dpe_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_dpe_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.39	100.00	80.22	53.88		97.83	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_dpe_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	22	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	22	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	5694633	10307	0	0
intr_enable_rd_A	5694633	2165	0	0
key_version_rd_A	5694633	1883	0	0
reseed_interval_regwen_rd_A	5694633	665	0	0
salt_0_rd_A	5694633	1857	0	0
salt_1_rd_A	5694633	1843	0	0
salt_2_rd_A	5694633	1931	0	0
salt_3_rd_A	5694633	1878	0	0
salt_4_rd_A	5694633	1948	0	0
salt_5_rd_A	5694633	1964	0	0
salt_6_rd_A	5694633	1913	0	0
salt_7_rd_A	5694633	1820	0	0
sideload_clear_rd_A	5694633	1779	0	0
slot_policy_rd_A	5694633	2718	0	0
sw_binding_0_rd_A	5694633	1760	0	0
sw_binding_1_rd_A	5694633	1954	0	0
sw_binding_2_rd_A	5694633	1853	0	0
sw_binding_3_rd_A	5694633	1863	0	0
sw_binding_4_rd_A	5694633	1859	0	0
sw_binding_5_rd_A	5694633	1936	0	0
sw_binding_6_rd_A	5694633	1889	0	0
sw_binding_7_rd_A	5694633	1845	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5694633	10307	0	0
T21	20169	3	0	0
T22	12791	568	0	0
T23	1402	1	0	0
T32	9341	3	0	0
T33	4304	2	0	0
T34	0	546	0	0
T35	0	372	0	0
T44	0	2	0	0
T61	2402	7	0	0
T74	1249	24	0	0
T75	7468	0	0	0
T76	1275	0	0	0
T77	1279	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5694633	2165	0	0
T21	20169	36	0	0
T34	14427	10	0	0
T36	15091	173	0	0
T40	1142	20	0	0
T42	10416	48	0	0
T44	0	40	0	0
T68	0	94	0	0
T69	810	0	0	0
T70	2432	0	0	0
T76	1275	18	0	0
T77	1279	18	0	0
T93	85260	417	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5694633	1883	0	0
T21	20169	25	0	0
T35	8853	0	0	0
T36	15091	180	0	0
T38	11679	0	0	0
T42	10416	36	0	0
T44	10454	39	0	0
T51	9482	0	0	0
T59	12769	0	0	0
T64	0	23	0	0
T65	0	44	0	0
T66	0	76	0	0
T68	0	86	0	0
T93	85260	445	0	0
T94	0	18	0	0
T95	1965	0	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5694633	665	0	0
T34	14427	18	0	0
T36	15091	172	0	0
T42	10416	49	0	0
T58	7305	0	0	0
T60	9822	0	0	0
T64	0	7	0	0
T65	0	46	0	0
T66	0	22	0	0
T69	810	0	0	0
T70	2432	0	0	0
T71	1653	0	0	0
T72	1164	0	0	0
T73	3039	0	0	0
T94	0	83	0	0
T96	0	51	0	0
T97	0	17	0	0
T98	0	1	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5694633	1857	0	0
T21	20169	61	0	0
T34	14427	14	0	0
T36	15091	147	0	0
T42	10416	51	0	0
T44	0	21	0	0
T64	0	24	0	0
T65	0	42	0	0
T68	0	79	0	0
T69	810	0	0	0
T70	2432	0	0	0
T71	1653	0	0	0
T72	1164	0	0	0
T73	3039	0	0	0
T93	85260	416	0	0
T94	0	5	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5694633	1843	0	0
T21	20169	45	0	0
T34	14427	8	0	0
T36	15091	185	0	0
T42	10416	50	0	0
T44	0	34	0	0
T64	0	18	0	0
T65	0	46	0	0
T68	0	96	0	0
T69	810	0	0	0
T70	2432	0	0	0
T71	1653	0	0	0
T72	1164	0	0	0
T73	3039	0	0	0
T93	85260	402	0	0
T94	0	7	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5694633	1931	0	0
T21	20169	34	0	0
T34	14427	8	0	0
T36	15091	177	0	0
T42	10416	44	0	0
T44	0	47	0	0
T64	0	12	0	0
T65	0	34	0	0
T68	0	67	0	0
T69	810	0	0	0
T70	2432	0	0	0
T71	1653	0	0	0
T72	1164	0	0	0
T73	3039	0	0	0
T93	85260	478	0	0
T94	0	22	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5694633	1878	0	0
T21	20169	64	0	0
T34	14427	14	0	0
T36	15091	188	0	0
T42	10416	31	0	0
T44	0	53	0	0
T64	0	3	0	0
T65	0	27	0	0
T68	0	102	0	0
T69	810	0	0	0
T70	2432	0	0	0
T71	1653	0	0	0
T72	1164	0	0	0
T73	3039	0	0	0
T93	85260	424	0	0
T94	0	14	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5694633	1948	0	0
T21	20169	33	0	0
T34	14427	22	0	0
T36	15091	169	0	0
T42	10416	36	0	0
T44	0	40	0	0
T64	0	1	0	0
T65	0	35	0	0
T68	0	112	0	0
T69	810	0	0	0
T70	2432	0	0	0
T71	1653	0	0	0
T72	1164	0	0	0
T73	3039	0	0	0
T93	85260	486	0	0
T94	0	23	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5694633	1964	0	0
T21	20169	32	0	0
T34	14427	16	0	0
T36	15091	174	0	0
T42	10416	53	0	0
T44	0	46	0	0
T64	0	11	0	0
T65	0	40	0	0
T68	0	86	0	0
T69	810	0	0	0
T70	2432	0	0	0
T71	1653	0	0	0
T72	1164	0	0	0
T73	3039	0	0	0
T93	85260	464	0	0
T94	0	18	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5694633	1913	0	0
T21	20169	44	0	0
T34	14427	22	0	0
T36	15091	168	0	0
T42	10416	35	0	0
T44	0	44	0	0
T64	0	11	0	0
T65	0	47	0	0
T68	0	78	0	0
T69	810	0	0	0
T70	2432	0	0	0
T71	1653	0	0	0
T72	1164	0	0	0
T73	3039	0	0	0
T93	85260	480	0	0
T94	0	22	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5694633	1820	0	0
T21	20169	42	0	0
T34	14427	19	0	0
T36	15091	182	0	0
T42	10416	29	0	0
T44	0	51	0	0
T64	0	9	0	0
T65	0	36	0	0
T68	0	65	0	0
T69	810	0	0	0
T70	2432	0	0	0
T71	1653	0	0	0
T72	1164	0	0	0
T73	3039	0	0	0
T93	85260	383	0	0
T94	0	17	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5694633	1779	0	0
T21	20169	30	0	0
T34	14427	12	0	0
T36	15091	164	0	0
T42	10416	40	0	0
T44	0	46	0	0
T64	0	13	0	0
T65	0	35	0	0
T66	0	61	0	0
T68	0	80	0	0
T69	810	0	0	0
T70	2432	0	0	0
T71	1653	0	0	0
T72	1164	0	0	0
T73	3039	0	0	0
T93	85260	439	0	0

slot_policy_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5694633	2718	0	0
T21	20169	100	0	0
T34	14427	17	0	0
T36	15091	181	0	0
T42	10416	49	0	0
T44	0	105	0	0
T64	0	16	0	0
T65	0	38	0	0
T68	0	186	0	0
T69	810	0	0	0
T70	2432	0	0	0
T71	1653	0	0	0
T72	1164	0	0	0
T73	3039	0	0	0
T93	85260	478	0	0
T94	0	17	0	0

sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5694633	1760	0	0
T21	20169	45	0	0
T34	14427	17	0	0
T36	15091	169	0	0
T42	10416	25	0	0
T44	0	23	0	0
T64	0	4	0	0
T65	0	33	0	0
T68	0	78	0	0
T69	810	0	0	0
T70	2432	0	0	0
T71	1653	0	0	0
T72	1164	0	0	0
T73	3039	0	0	0
T93	85260	402	0	0
T94	0	52	0	0

sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5694633	1954	0	0
T21	20169	34	0	0
T34	14427	3	0	0
T36	15091	157	0	0
T42	10416	46	0	0
T44	0	58	0	0
T64	0	15	0	0
T65	0	45	0	0
T68	0	90	0	0
T69	810	0	0	0
T70	2432	0	0	0
T71	1653	0	0	0
T72	1164	0	0	0
T73	3039	0	0	0
T93	85260	432	0	0
T94	0	38	0	0

sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5694633	1853	0	0
T21	20169	40	0	0
T34	14427	18	0	0
T36	15091	161	0	0
T42	10416	40	0	0
T44	0	47	0	0
T65	0	42	0	0
T66	0	73	0	0
T68	0	99	0	0
T69	810	0	0	0
T70	2432	0	0	0
T71	1653	0	0	0
T72	1164	0	0	0
T73	3039	0	0	0
T93	85260	458	0	0
T94	0	20	0	0

sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5694633	1863	0	0
T21	20169	31	0	0
T34	14427	17	0	0
T36	15091	178	0	0
T42	10416	43	0	0
T44	0	51	0	0
T64	0	5	0	0
T65	0	30	0	0
T68	0	75	0	0
T69	810	0	0	0
T70	2432	0	0	0
T71	1653	0	0	0
T72	1164	0	0	0
T73	3039	0	0	0
T93	85260	423	0	0
T94	0	43	0	0

sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5694633	1859	0	0
T21	20169	23	0	0
T34	14427	8	0	0
T36	15091	183	0	0
T42	10416	41	0	0
T44	0	41	0	0
T64	0	11	0	0
T65	0	35	0	0
T68	0	65	0	0
T69	810	0	0	0
T70	2432	0	0	0
T71	1653	0	0	0
T72	1164	0	0	0
T73	3039	0	0	0
T93	85260	430	0	0
T94	0	18	0	0

sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5694633	1936	0	0
T21	20169	62	0	0
T34	14427	17	0	0
T36	15091	199	0	0
T42	10416	40	0	0
T44	0	44	0	0
T64	0	12	0	0
T65	0	45	0	0
T68	0	82	0	0
T69	810	0	0	0
T70	2432	0	0	0
T71	1653	0	0	0
T72	1164	0	0	0
T73	3039	0	0	0
T93	85260	438	0	0
T94	0	3	0	0

sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5694633	1889	0	0
T21	20169	53	0	0
T34	14427	12	0	0
T36	15091	181	0	0
T42	10416	28	0	0
T44	0	39	0	0
T64	0	10	0	0
T65	0	26	0	0
T68	0	93	0	0
T69	810	0	0	0
T70	2432	0	0	0
T71	1653	0	0	0
T72	1164	0	0	0
T73	3039	0	0	0
T93	85260	453	0	0
T94	0	6	0	0

sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5694633	1845	0	0
T21	20169	29	0	0
T35	8853	0	0	0
T36	15091	180	0	0
T38	11679	0	0	0
T42	10416	43	0	0
T44	10454	26	0	0
T51	9482	0	0	0
T59	12769	0	0	0
T64	0	15	0	0
T65	0	46	0	0
T66	0	91	0	0
T68	0	70	0	0
T93	85260	466	0	0
T94	0	17	0	0
T95	1965	0	0	0