Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	768622	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

241728

1

T1

4

T2

3246

T3

2864

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	869056	1			T1	1		T2	12495		T3	4826
values[0x0]	70280	1			T1	10		T2	769		T3	700
values[0x1]	71014	1			T1	14		T2	833		T3	672

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	527598	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

482752

1

T1

7

T2

6564

T3

3755

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3329	1			T2	56		T3	26		T4	43
valid_sources[0x01]	3338	1			T2	43		T3	28		T4	35
valid_sources[0x02]	3892	1			T2	60		T3	31		T4	60
valid_sources[0x03]	3753	1			T2	49		T3	42		T4	35
valid_sources[0x04]	3290	1			T2	65		T3	16		T4	39
valid_sources[0x05]	3727	1			T2	64		T3	22		T4	33
valid_sources[0x06]	3653	1			T2	50		T3	17		T4	58
valid_sources[0x07]	3475	1			T2	57		T3	48		T4	42
valid_sources[0x08]	3275	1			T2	44		T3	21		T4	31
valid_sources[0x09]	3613	1			T2	34		T3	17		T4	15
valid_sources[0x0a]	3596	1			T2	55		T3	17		T4	46
valid_sources[0x0b]	3355	1			T2	36		T3	24		T4	36
valid_sources[0x0c]	3399	1			T2	51		T3	35		T4	29
valid_sources[0x0d]	3855	1			T1	1		T2	59		T3	39
valid_sources[0x0e]	3671	1			T2	54		T3	18		T4	25
valid_sources[0x0f]	3534	1			T1	1		T2	43		T3	15
valid_sources[0x10]	3429	1			T2	56		T3	17		T4	41
valid_sources[0x11]	3257	1			T2	44		T3	22		T4	36
valid_sources[0x12]	3418	1			T2	40		T3	12		T4	41
valid_sources[0x13]	3389	1			T2	66		T3	9		T4	38
valid_sources[0x14]	3449	1			T2	43		T3	25		T4	42
valid_sources[0x15]	3468	1			T2	65		T3	46		T4	25
valid_sources[0x16]	3429	1			T2	48		T3	28		T4	26
valid_sources[0x17]	3636	1			T2	46		T3	38		T4	43
valid_sources[0x18]	3710	1			T1	1		T2	52		T3	19
valid_sources[0x19]	3713	1			T2	59		T3	14		T4	32
valid_sources[0x1a]	3388	1			T2	57		T3	31		T4	35
valid_sources[0x1b]	3964	1			T2	45		T3	35		T4	33
valid_sources[0x1c]	3340	1			T1	1		T2	45		T3	18
valid_sources[0x1d]	3289	1			T2	61		T3	20		T4	33
valid_sources[0x1e]	4102	1			T2	88		T3	22		T4	37
valid_sources[0x1f]	3334	1			T2	69		T3	20		T4	36
valid_sources[0x20]	3273	1			T2	66		T3	15		T4	23
valid_sources[0x21]	3396	1			T2	36		T3	20		T4	26
valid_sources[0x22]	3398	1			T2	42		T3	32		T4	26
valid_sources[0x23]	3424	1			T2	31		T3	31		T4	58
valid_sources[0x24]	3571	1			T2	49		T3	44		T4	24
valid_sources[0x25]	3677	1			T1	1		T2	60		T3	32
valid_sources[0x26]	3571	1			T2	45		T3	28		T4	41
valid_sources[0x27]	3297	1			T2	36		T3	15		T4	39
valid_sources[0x28]	3749	1			T2	26		T3	25		T4	22
valid_sources[0x29]	3749	1			T2	39		T3	20		T4	32
valid_sources[0x2a]	3700	1			T2	65		T3	28		T4	24
valid_sources[0x2b]	3620	1			T2	65		T3	32		T4	28
valid_sources[0x2c]	3492	1			T2	51		T3	12		T4	48
valid_sources[0x2d]	3602	1			T1	1		T2	60		T3	21
valid_sources[0x2e]	3678	1			T2	44		T3	6		T4	40
valid_sources[0x2f]	3650	1			T2	62		T3	21		T4	35
valid_sources[0x30]	3785	1			T2	44		T3	24		T4	47
valid_sources[0x31]	3695	1			T2	57		T3	28		T4	25
valid_sources[0x32]	13952	1			T2	33		T3	31		T4	27
valid_sources[0x33]	3579	1			T2	77		T3	11		T4	42
valid_sources[0x34]	4788	1			T2	40		T3	10		T4	41
valid_sources[0x35]	3703	1			T2	57		T3	21		T4	33
valid_sources[0x36]	3383	1			T2	63		T3	19		T4	36
valid_sources[0x37]	3758	1			T2	51		T3	17		T4	43
valid_sources[0x38]	3663	1			T2	51		T3	28		T4	52
valid_sources[0x39]	3512	1			T2	51		T3	27		T4	37
valid_sources[0x3a]	3597	1			T2	59		T3	13		T4	29
valid_sources[0x3b]	3568	1			T2	49		T3	27		T4	37
valid_sources[0x3c]	3418	1			T2	60		T3	14		T4	33
valid_sources[0x3d]	3654	1			T2	47		T3	28		T4	68
valid_sources[0x3e]	3253	1			T2	36		T3	21		T4	36
valid_sources[0x3f]	3380	1			T2	48		T3	27		T4	23
valid_sources[0x40]	7002	1			T2	64		T3	28		T4	31
valid_sources[0x41]	3343	1			T2	54		T3	16		T4	48
valid_sources[0x42]	3534	1			T2	66		T3	29		T4	26
valid_sources[0x43]	3532	1			T2	58		T3	17		T4	48
valid_sources[0x44]	3592	1			T2	44		T3	29		T4	20
valid_sources[0x45]	3586	1			T2	57		T3	17		T4	36
valid_sources[0x46]	3272	1			T2	79		T3	19		T4	38
valid_sources[0x47]	3245	1			T2	48		T3	34		T4	34
valid_sources[0x48]	7685	1			T2	56		T3	15		T4	33
valid_sources[0x49]	3450	1			T2	57		T3	14		T4	48
valid_sources[0x4a]	3686	1			T2	44		T3	16		T4	40
valid_sources[0x4b]	3526	1			T2	53		T3	35		T4	45
valid_sources[0x4c]	3634	1			T2	65		T3	34		T4	40
valid_sources[0x4d]	3619	1			T2	57		T3	10		T4	55
valid_sources[0x4e]	3862	1			T2	65		T3	24		T4	54
valid_sources[0x4f]	3410	1			T2	59		T3	28		T4	39
valid_sources[0x50]	5525	1			T2	53		T3	26		T4	27
valid_sources[0x51]	3416	1			T2	36		T3	13		T4	23
valid_sources[0x52]	3597	1			T2	61		T3	46		T4	28
valid_sources[0x53]	3583	1			T2	58		T3	30		T4	47
valid_sources[0x54]	3659	1			T2	81		T3	23		T4	26
valid_sources[0x55]	3648	1			T2	60		T3	25		T4	32
valid_sources[0x56]	3436	1			T2	48		T3	50		T4	26
valid_sources[0x57]	3581	1			T2	65		T3	38		T4	43
valid_sources[0x58]	3264	1			T2	31		T3	19		T4	38
valid_sources[0x59]	5556	1			T2	59		T3	32		T4	42
valid_sources[0x5a]	3492	1			T2	71		T3	20		T4	23
valid_sources[0x5b]	9198	1			T2	49		T3	20		T4	27
valid_sources[0x5c]	3601	1			T2	44		T3	27		T4	59
valid_sources[0x5d]	3802	1			T1	1		T2	59		T3	15
valid_sources[0x5e]	3793	1			T2	39		T3	33		T4	39
valid_sources[0x5f]	4884	1			T2	53		T3	13		T4	26
valid_sources[0x60]	9822	1			T2	37		T3	27		T4	44
valid_sources[0x61]	3314	1			T2	48		T3	36		T4	31
valid_sources[0x62]	3401	1			T2	45		T3	24		T4	30
valid_sources[0x63]	3612	1			T2	80		T3	31		T4	59
valid_sources[0x64]	3428	1			T2	62		T3	17		T4	30
valid_sources[0x65]	3615	1			T1	1		T2	72		T3	20
valid_sources[0x66]	3581	1			T1	1		T2	49		T3	22
valid_sources[0x67]	3398	1			T2	67		T3	20		T4	46
valid_sources[0x68]	4165	1			T2	39		T3	24		T4	40
valid_sources[0x69]	3565	1			T2	62		T3	32		T4	22
valid_sources[0x6a]	3472	1			T2	72		T3	23		T4	27
valid_sources[0x6b]	3704	1			T2	58		T3	14		T4	30
valid_sources[0x6c]	3558	1			T2	63		T3	21		T4	31
valid_sources[0x6d]	3569	1			T2	51		T3	39		T4	36
valid_sources[0x6e]	3615	1			T2	55		T3	20		T4	44
valid_sources[0x6f]	3631	1			T2	76		T3	23		T4	37
valid_sources[0x70]	3689	1			T2	65		T3	21		T4	31
valid_sources[0x71]	3500	1			T2	65		T3	27		T4	38
valid_sources[0x72]	3388	1			T2	49		T3	15		T4	30
valid_sources[0x73]	3521	1			T2	56		T3	23		T4	44
valid_sources[0x74]	3526	1			T2	44		T3	8		T4	22
valid_sources[0x75]	3636	1			T2	68		T3	33		T4	42
valid_sources[0x76]	3538	1			T2	68		T3	48		T4	62
valid_sources[0x77]	3458	1			T2	60		T3	29		T4	36
valid_sources[0x78]	3481	1			T2	54		T3	20		T4	27
valid_sources[0x79]	3552	1			T2	62		T3	31		T4	56
valid_sources[0x7a]	3558	1			T2	47		T3	35		T4	39
valid_sources[0x7b]	4141	1			T2	45		T3	37		T4	45
valid_sources[0x7c]	3438	1			T2	59		T3	14		T4	39
valid_sources[0x7d]	3327	1			T1	2		T2	60		T3	32
valid_sources[0x7e]	3582	1			T2	65		T3	15		T4	26
valid_sources[0x7f]	3456	1			T2	46		T3	13		T4	40
valid_sources[0x80]	3319	1			T2	43		T3	23		T4	25

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

133297

1

T2

2164

T3

1915

T4

2036

values[0x0]

all_enables

biggest_size

57604

1

T1

1

T2

577

T3

538

values[0x1]

all_enables

biggest_size

50827

1

T1

3

T2

505

T3

411